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net: macb: Flush correct cache portion when sending

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The end address of the cache flush must be cache-line-aligned since
otherwise (at least on ARM926-EJS) the request is ignored. When the cache
is enabled this means that packets are not sent.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
This commit is contained in:
Simon Glass 2016-05-05 07:28:10 -06:00 committed by Andreas Bießmann
parent d5555b70e6
commit f589f8cca6
1 changed files with 1 additions and 1 deletions
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2
drivers/net/macb.c
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@ -280,7 +280,7 @@ static int _macb_send(struct macb_device *macb, const char *name, void *packet,
barrier();
macb_flush_ring_desc(macb, TX);
/* Do we need check paddr and length is dcache line aligned? */
flush_dcache_range(paddr, paddr + length);
flush_dcache_range(paddr, paddr + ALIGN(length, ARCH_DMA_MINALIGN));
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
/*