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at91: Move at91 global data into arch_global_data

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Move these fields into arch_global_data.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2012-12-13 20:48:31 +00:00 committed by Tom Rini
parent 5cb48582ac
commit f47e6ecd5d
5 changed files with 45 additions and 41 deletions
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24
arch/arm/cpu/arm920t/at91/clock.c
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@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
case AT91_PMC_MCKR_CSS_SLOW: case AT91_PMC_MCKR_CSS_SLOW:
return CONFIG_SYS_AT91_SLOW_CLOCK; return CONFIG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN: case AT91_PMC_MCKR_CSS_MAIN:
return gd->main_clk_rate_hz; return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA: case AT91_PMC_MCKR_CSS_PLLA:
return gd->plla_rate_hz; return gd->arch.plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB: case AT91_PMC_MCKR_CSS_PLLB:
return gd->pllb_rate_hz; return gd->arch.pllb_rate_hz;
} }
return 0; return 0;
@ -124,10 +124,10 @@ int at91_clock_init(unsigned long main_clock)
main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
} }
#endif #endif
gd->main_clk_rate_hz = main_clock; gd->arch.main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */ /* report if PLLA is more than mildly overclocked */
gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL #ifdef CONFIG_USB_ATMEL
/* /*
@ -136,9 +136,10 @@ int at91_clock_init(unsigned long main_clock)
* *
* REVISIT: assumes MCK doesn't derive from PLLB! * REVISIT: assumes MCK doesn't derive from PLLB!
*/ */
gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2; AT91_PMC_PLLBR_USBDIV_2;
gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init); gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
gd->arch.at91_pllb_usb_init);
#endif #endif
/* /*
@ -146,13 +147,14 @@ int at91_clock_init(unsigned long main_clock)
* For now, assume this parentage won't change. * For now, assume this parentage won't change.
*/ */
mckr = readl(&pmc->mckr); mckr = readl(&pmc->mckr);
gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = gd->mck_rate_hz; freq = gd->arch.mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
/* mdiv */ /* mdiv */
gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); gd->arch.mck_rate_hz = freq /
gd->cpu_clk_rate_hz = freq; (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
gd->arch.cpu_clk_rate_hz = freq;
return 0; return 0;
} }

30
arch/arm/cpu/arm926ejs/at91/clock.c
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@ -29,11 +29,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
case AT91_PMC_MCKR_CSS_SLOW: case AT91_PMC_MCKR_CSS_SLOW:
return CONFIG_SYS_AT91_SLOW_CLOCK; return CONFIG_SYS_AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN: case AT91_PMC_MCKR_CSS_MAIN:
return gd->main_clk_rate_hz; return gd->arch.main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA: case AT91_PMC_MCKR_CSS_PLLA:
return gd->plla_rate_hz; return gd->arch.plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB: case AT91_PMC_MCKR_CSS_PLLB:
return gd->pllb_rate_hz; return gd->arch.pllb_rate_hz;
} }
return 0; return 0;
@ -132,10 +132,10 @@ int at91_clock_init(unsigned long main_clock)
main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16);
} }
#endif #endif
gd->main_clk_rate_hz = main_clock; gd->arch.main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */ /* report if PLLA is more than mildly overclocked */
gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL #ifdef CONFIG_USB_ATMEL
/* /*
@ -144,9 +144,10 @@ int at91_clock_init(unsigned long main_clock)
* *
* REVISIT: assumes MCK doesn't derive from PLLB! * REVISIT: assumes MCK doesn't derive from PLLB!
*/ */
gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2; AT91_PMC_PLLBR_USBDIV_2;
gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init); gd->arch.pllb_rate_hz = at91_pll_rate(main_clock,
gd->arch.at91_pllb_usb_init);
#endif #endif
/* /*
@ -157,15 +158,15 @@ int at91_clock_init(unsigned long main_clock)
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \
|| defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9X5)
/* plla divisor by 2 */ /* plla divisor by 2 */
gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif #endif
gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = gd->mck_rate_hz; freq = gd->arch.mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91SAM9G20) #if defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */ /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK) if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */ freq /= 2; /* processor clock division */
@ -177,14 +178,15 @@ int at91_clock_init(unsigned long main_clock)
* 2 <==> 4 * 2 <==> 4
* 3 <==> 3 * 3 <==> 3
*/ */
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3 ? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else #else
gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); gd->arch.mck_rate_hz = freq /
(1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif #endif
gd->cpu_clk_rate_hz = freq; gd->arch.cpu_clk_rate_hz = freq;
return 0; return 0;
} }

2
arch/arm/cpu/arm926ejs/at91/timer.c
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@ -79,7 +79,7 @@ int timer_init(void)
/* Enable PITC */ /* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
gd->timer_rate_hz = gd->mck_rate_hz / 16; gd->timer_rate_hz = gd->arch.mck_rate_hz / 16;
gd->tbu = gd->tbl = 0; gd->tbu = gd->tbl = 0;
return 0; return 0;

12
arch/arm/include/asm/arch-at91/clk.h
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@ -31,37 +31,37 @@
static inline unsigned long get_cpu_clk_rate(void) static inline unsigned long get_cpu_clk_rate(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
return gd->cpu_clk_rate_hz; return gd->arch.cpu_clk_rate_hz;
} }
static inline unsigned long get_main_clk_rate(void) static inline unsigned long get_main_clk_rate(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
return gd->main_clk_rate_hz; return gd->arch.main_clk_rate_hz;
} }
static inline unsigned long get_mck_clk_rate(void) static inline unsigned long get_mck_clk_rate(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
return gd->mck_rate_hz; return gd->arch.mck_rate_hz;
} }
static inline unsigned long get_plla_clk_rate(void) static inline unsigned long get_plla_clk_rate(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
return gd->plla_rate_hz; return gd->arch.plla_rate_hz;
} }
static inline unsigned long get_pllb_clk_rate(void) static inline unsigned long get_pllb_clk_rate(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
return gd->pllb_rate_hz; return gd->arch.pllb_rate_hz;
} }
static inline u32 get_pllb_init(void) static inline u32 get_pllb_init(void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
return gd->at91_pllb_usb_init; return gd->arch.at91_pllb_usb_init;
} }
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)

18
arch/arm/include/asm/global_data.h
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@ -26,6 +26,15 @@
/* Architecture-specific global data */ /* Architecture-specific global data */
struct arch_global_data { struct arch_global_data {
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
unsigned long main_clk_rate_hz;
unsigned long mck_rate_hz;
unsigned long plla_rate_hz;
unsigned long pllb_rate_hz;
unsigned long at91_pllb_usb_init;
#endif
}; };
/* /*
@ -50,15 +59,6 @@ typedef struct global_data {
#ifdef CONFIG_FSL_ESDHC #ifdef CONFIG_FSL_ESDHC
unsigned long sdhc_clk; unsigned long sdhc_clk;
#endif #endif
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
unsigned long main_clk_rate_hz;
unsigned long mck_rate_hz;
unsigned long plla_rate_hz;
unsigned long pllb_rate_hz;
unsigned long at91_pllb_usb_init;
#endif
#ifdef CONFIG_ARM #ifdef CONFIG_ARM
/* "static data" needed by most of timer.c on ARM platforms */ /* "static data" needed by most of timer.c on ARM platforms */
unsigned long timer_rate_hz; unsigned long timer_rate_hz;