mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-28 23:23:30 +08:00
VCMA9: various cleanups/code style fixes
Signed-off-by: David Müller <d.mueller@elsoft.ch>
This commit is contained in:
David Müller (ELSOFT AG)
Albert ARIBAUD
parent
6d754843ff
commit
f3108304e4
@ -28,8 +28,8 @@ endif
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LIB = $(obj)lib$(BOARD).o
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COBJS := vcma9.o cmd_vcma9.o
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COBJS += ../common/common_util.o
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COBJS := ../common/common_util.o
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COBJS += $(BOARD).o cmd_$(BOARD).o
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SOBJS := lowlevel_init.o
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@ -43,15 +43,6 @@ static uchar cs8900_chksum(ushort data)
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DECLARE_GLOBAL_DATA_PTR;
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extern void print_vcma9_info(void);
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extern int vcma9_cantest(int);
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extern int vcma9_nandtest(void);
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extern int vcma9_nanderase(void);
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extern int vcma9_nandread(ulong);
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extern int vcma9_nandwrite(ulong);
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extern int vcma9_dactest(int);
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extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
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/* ------------------------------------------------------------------------- */
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int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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@ -60,7 +51,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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char cs8900_name[10];
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if (strcmp(argv[1], "info") == 0)
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{
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print_vcma9_info();
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vcma9_print_info();
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return 0;
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}
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#if defined(CONFIG_CS8900)
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@ -133,48 +124,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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return 0;
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}
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#endif
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#if 0
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if (strcmp(argv[1], "cantest") == 0) {
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if (argc >= 3)
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vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1);
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else
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vcma9_cantest(0);
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return 0;
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}
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if (strcmp(argv[1], "nandtest") == 0) {
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vcma9_nandtest();
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return 0;
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}
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if (strcmp(argv[1], "nanderase") == 0) {
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vcma9_nanderase();
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return 0;
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}
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if (strcmp(argv[1], "nandread") == 0) {
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ulong offset = 0;
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if (argc >= 3)
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offset = simple_strtoul(argv[2], NULL, 16);
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vcma9_nandread(offset);
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return 0;
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}
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if (strcmp(argv[1], "nandwrite") == 0) {
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ulong offset = 0;
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if (argc >= 3)
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offset = simple_strtoul(argv[2], NULL, 16);
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vcma9_nandwrite(offset);
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return 0;
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}
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if (strcmp(argv[1], "dactest") == 0) {
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if (argc >= 3)
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vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1);
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else
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vcma9_dactest(0);
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return 0;
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}
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#endif
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return (do_mplcommon(cmdtp, flag, argc, argv));
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}
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@ -182,5 +131,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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U_BOOT_CMD(
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vcma9, 6, 1, do_vcma9,
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"VCMA9 specific commands",
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"flash mem [SrcAddr]\n - updates U-Boot with image in memory"
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"flash mem [SrcAddr] - updates U-Boot with image in memory\n"
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"vcma9 info - displays board information"
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);
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@ -4,9 +4,9 @@
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for the Samsung SMDK2410 by
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* (C) Copyright 2002
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* Modified for MPL VCMA9 by
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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* (C) Copyright 2002, 2003, 2004, 2005
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -32,12 +32,21 @@
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#include <version.h>
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/* some parameters for the board */
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/* register definitions */
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#define PLD_BASE 0x28000000
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#define MISC_REG 0x103
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#define SDRAM_REG 0x106
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#define BWSCON 0x48000000
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#define PLD_BASE 0x2C000000
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#define SDRAM_REG 0x2C000106
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#define CLKBASE 0x4C000000
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#define LOCKTIME 0x0
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#define MPLLCON 0x4
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#define UPLLCON 0x8
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#define GPIOBASE 0x56000000
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#define GSTATUS1 0xB0
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#define FASTCPU 0x02
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/* some parameters for the board */
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/* BWSCON */
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#define DW8 (0x0)
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#define DW16 (0x1)
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@ -48,83 +57,160 @@
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/* BANKSIZE */
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#define BURST_EN (0x1<<7)
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#define B1_BWSCON (DW16)
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#define B2_BWSCON (DW32)
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#define B3_BWSCON (DW32)
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#define B4_BWSCON (DW16 + WAIT + UBLB)
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#define B5_BWSCON (DW8 + UBLB)
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#define B6_BWSCON (DW32)
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#define B7_BWSCON (DW32)
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/* BANK0CON 200 */
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#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
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#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
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#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
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#define B0_Tcoh_200 0x0 /* 0clk */
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#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */
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#define B0_Tacp_200 0x0 /* page mode is not used */
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#define B0_PMC_200 0x0 /* page mode disabled */
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/* BANK0CON */
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#define B0_Tacs 0x0 /* 0clk */
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#define B0_Tcos 0x1 /* 1clk */
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/*#define B0_Tcos 0x0 0clk */
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#define B0_Tacc 0x7 /* 14clk */
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/*#define B0_Tacc 0x5 8clk */
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#define B0_Tcoh 0x0 /* 0clk */
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#define B0_Tah 0x0 /* 0clk */
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#define B0_Tacp 0x0 /* page mode is not used */
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#define B0_PMC 0x0 /* page mode disabled */
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/* BANK0CON 250 */
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#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
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#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
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#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
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#define B0_Tcoh_250 0x0 /* 0clk */
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#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
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#define B0_Tacp_250 0x0 /* page mode is not used */
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#define B0_PMC_250 0x0 /* page mode disabled */
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/* BANK1CON */
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#define B1_Tacs 0x0 /* 0clk */
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#define B1_Tcos 0x1 /* 1clk */
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/*#define B1_Tcos 0x0 0clk */
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#define B1_Tacc 0x7 /* 14clk */
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/*#define B1_Tacc 0x5 8clk */
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#define B1_Tcoh 0x0 /* 0clk */
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#define B1_Tah 0x0 /* 0clk */
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#define B1_Tacp 0x0 /* page mode is not used */
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#define B1_PMC 0x0 /* page mode disabled */
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/* BANK0CON 266 */
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#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
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#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
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#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
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#define B0_Tcoh_266 0x0 /* 0clk */
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#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
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#define B0_Tacp_266 0x0 /* page mode is not used */
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#define B0_PMC_266 0x0 /* page mode disabled */
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/* BANK1CON 200 */
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#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
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#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
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#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
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#define B1_Tcoh_200 0x0 /* 0clk */
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#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */
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#define B1_Tacp_200 0x0 /* page mode is not used */
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#define B1_PMC_200 0x0 /* page mode disabled */
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/* BANK1CON 250 */
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#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
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#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
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#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
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#define B1_Tcoh_250 0x0 /* 0clk */
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#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
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#define B1_Tacp_250 0x0 /* page mode is not used */
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#define B1_PMC_250 0x0 /* page mode disabled */
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/* BANK1CON 266 */
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#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
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#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
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#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
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#define B1_Tcoh_266 0x0 /* 0clk */
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#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
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#define B1_Tacp_266 0x0 /* page mode is not used */
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#define B1_PMC_266 0x0 /* page mode disabled */
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/* BANK2CON 200 + 250 + 266 */
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#define B2_Tacs 0x3 /* 4clk */
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#define B2_Tcos 0x3 /* 4clk */
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#define B2_Tacc 0x7 /* 14clk */
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#define B2_Tcoh 0x3 /* 4clk */
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#define B2_Tah 0x3 /* 4clk */
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#define B2_Tcah 0x3 /* 4clk */
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#define B2_Tacp 0x0 /* page mode is not used */
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#define B2_PMC 0x0 /* page mode disabled */
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/* BANK3CON 200 + 250 + 266 */
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#define B3_Tacs 0x3 /* 4clk */
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#define B3_Tcos 0x3 /* 4clk */
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#define B3_Tacc 0x7 /* 14clk */
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#define B3_Tcoh 0x3 /* 4clk */
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#define B3_Tah 0x3 /* 4clk */
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#define B3_Tcah 0x3 /* 4clk */
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#define B3_Tacp 0x0 /* page mode is not used */
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#define B3_PMC 0x0 /* page mode disabled */
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#define B4_Tacs 0x3 /* 4clk */
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#define B4_Tcos 0x1 /* 1clk */
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#define B4_Tacc 0x7 /* 14clk */
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#define B4_Tcoh 0x1 /* 1clk */
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#define B4_Tah 0x0 /* 0clk */
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#define B4_Tacp 0x0 /* page mode is not used */
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#define B4_PMC 0x0 /* page mode disabled */
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/* BANK4CON 200 */
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#define B4_Tacs_200 0x1 /* 1clk */
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#define B4_Tcos_200 0x3 /* 4clk */
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#define B4_Tacc_200 0x7 /* 14clk */
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#define B4_Tcoh_200 0x3 /* 4clk */
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#define B4_Tcah_200 0x2 /* 2clk */
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#define B4_Tacp_200 0x0 /* page mode is not used */
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#define B4_PMC_200 0x0 /* page mode disabled */
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#define B5_Tacs 0x0 /* 0clk */
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#define B5_Tcos 0x3 /* 4clk */
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#define B5_Tacc 0x5 /* 8clk */
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#define B5_Tcoh 0x2 /* 2clk */
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#define B5_Tah 0x1 /* 1clk */
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#define B5_Tacp 0x0 /* page mode is not used */
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#define B5_PMC 0x0 /* page mode disabled */
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/* BANK4CON 250 */
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#define B4_Tacs_250 0x1 /* 1clk */
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#define B4_Tcos_250 0x3 /* 4clk */
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#define B4_Tacc_250 0x7 /* 14clk */
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#define B4_Tcoh_250 0x3 /* 4clk */
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#define B4_Tcah_250 0x2 /* 2clk */
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#define B4_Tacp_250 0x0 /* page mode is not used */
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#define B4_PMC_250 0x0 /* page mode disabled */
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/* BANK4CON 266 */
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#define B4_Tacs_266 0x1 /* 1clk */
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#define B4_Tcos_266 0x3 /* 4clk */
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#define B4_Tacc_266 0x7 /* 14clk */
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#define B4_Tcoh_266 0x3 /* 4clk */
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#define B4_Tcah_266 0x2 /* 2clk */
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#define B4_Tacp_266 0x0 /* page mode is not used */
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#define B4_PMC_266 0x0 /* page mode disabled */
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/* BANK5CON 200 */
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#define B5_Tacs_200 0x0 /* 0clk */
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#define B5_Tcos_200 0x3 /* 4clk */
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#define B5_Tacc_200 0x4 /* 6clk */
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#define B5_Tcoh_200 0x3 /* 4clk */
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#define B5_Tcah_200 0x1 /* 1clk */
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#define B5_Tacp_200 0x0 /* page mode is not used */
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#define B5_PMC_200 0x0 /* page mode disabled */
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/* BANK5CON 250 */
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#define B5_Tacs_250 0x0 /* 0clk */
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#define B5_Tcos_250 0x3 /* 4clk */
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#define B5_Tacc_250 0x5 /* 8clk */
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#define B5_Tcoh_250 0x3 /* 4clk */
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#define B5_Tcah_250 0x1 /* 1clk */
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#define B5_Tacp_250 0x0 /* page mode is not used */
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#define B5_PMC_250 0x0 /* page mode disabled */
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/* BANK5CON 266 */
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#define B5_Tacs_266 0x0 /* 0clk */
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#define B5_Tcos_266 0x3 /* 4clk */
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#define B5_Tacc_266 0x5 /* 8clk */
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#define B5_Tcoh_266 0x3 /* 4clk */
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#define B5_Tcah_266 0x1 /* 1clk */
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#define B5_Tacp_266 0x0 /* page mode is not used */
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#define B5_PMC_266 0x0 /* page mode disabled */
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#define B6_MT 0x3 /* SDRAM */
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#define B6_Trcd 0x1 /* 3clk */
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#define B6_Trcd_200 0x0 /* 2clk */
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#define B6_Trcd_250 0x1 /* 3clk */
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#define B6_Trcd_266 0x1 /* 3clk */
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#define B6_SCAN 0x2 /* 10bit */
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#define B7_MT 0x3 /* SDRAM */
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#define B7_Trcd 0x1 /* 3clk */
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#define B7_Trcd_200 0x0 /* 2clk */
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#define B7_Trcd_250 0x1 /* 3clk */
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#define B7_Trcd_266 0x1 /* 3clk */
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#define B7_SCAN 0x2 /* 10bit */
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/* REFRESH parameter */
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#define REFEN 0x1 /* Refresh enable */
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#define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
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#define Trp 0x0 /* 2clk */
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#define Trc 0x3 /* 7clk */
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#define Tchr 0x2 /* 3clk */
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#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
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#define Trp_200 0x0 /* 2clk */
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#define Trp_250 0x1 /* 3clk */
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#define Trp_266 0x1 /* 3clk */
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#define Tsrc_200 0x1 /* 5clk */
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#define Tsrc_250 0x2 /* 6clk */
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#define Tsrc_266 0x3 /* 7clk */
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/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
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#define REFCNT_200 489
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/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
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#define REFCNT_250 99
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/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
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#define REFCNT_266 0
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/**************************************/
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_TEXT_BASE:
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@ -132,81 +218,304 @@ _TEXT_BASE:
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.globl lowlevel_init
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lowlevel_init:
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/* use r0 to relocate DATA read/write to flash rather than memory ! */
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ldr r0, _TEXT_BASE
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ldr r13, =BWSCON
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/* enable minimal access to PLD */
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ldr r1, [r13] /* load default BWSCON */
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orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */
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str r1, [r13] /* set BWSCON */
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ldr r1, =0x7FF0 /* select slowest timing */
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str r1, [r13, #0x18] /* set BANKCON5 */
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ldr r1, =PLD_BASE
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ldr r2, =SETUPDATA
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ldrb r1, [r1, #MISC_REG]
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sub r2, r2, r0
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tst r1, #FASTCPU /* FASTCPU available ? */
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addeq r2, r2, #SETUPENTRY_SIZE
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/* memory control configuration */
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/* make r0 relative the current location so that it */
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/* reads SMRDATA out of FLASH rather than memory ! */
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ldr r0, =CSDATA
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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ldr r1, =BWSCON /* Bus Width Status Controller */
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add r2, r0, #CSDATA_END-CSDATA
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/* r2 = pointer into timing table */
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/* r13 = pointer to MEM controller regs (starting with BWSCON) */
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add r3, r2, #CSDATA_OFFSET
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add r4, r3, #CSDATAENTRY_SIZE
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0:
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ldr r3, [r0], #4
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str r3, [r1], #4
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cmp r2, r0
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ldr r1, [r3], #4
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str r1, [r13], #4
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cmp r3, r4
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bne 0b
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/* PLD access is now possible */
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/* r0 == SDRAMDATA */
|
||||
/* r1 == SDRAM controller regs */
|
||||
ldr r2, =PLD_BASE
|
||||
ldrb r3, [r2, #SDRAM_REG-PLD_BASE]
|
||||
mov r4, #SDRAMDATA1_END-SDRAMDATA
|
||||
/* r3 = SDRAMDATA
|
||||
/* r13 = pointer to MEM controller regs */
|
||||
ldr r1, =PLD_BASE
|
||||
mov r4, #SDRAMENTRY_SIZE
|
||||
ldrb r1, [r1, #SDRAM_REG]
|
||||
/* calculate start and end point */
|
||||
mla r0, r3, r4, r0
|
||||
add r2, r0, r4
|
||||
mla r3, r4, r1, r3
|
||||
add r4, r3, r4
|
||||
0:
|
||||
ldr r3, [r0], #4
|
||||
str r3, [r1], #4
|
||||
cmp r2, r0
|
||||
ldr r1, [r3], #4
|
||||
str r1, [r13], #4
|
||||
cmp r3, r4
|
||||
bne 0b
|
||||
|
||||
/* setup MPLL registers */
|
||||
ldr r1, =CLKBASE
|
||||
ldr r4, =0xFFFFFF
|
||||
add r3, r2, #4 /* r3 points to PLL values */
|
||||
str r4, [r1, #LOCKTIME]
|
||||
ldmia r3, {r4,r5}
|
||||
str r5, [r1, #UPLLCON] /* writing PLL register */
|
||||
/* !! order seems to be important !! */
|
||||
/* a little delay */
|
||||
ldr r3, =0x4000
|
||||
0:
|
||||
subs r3, r3, #1
|
||||
bne 0b
|
||||
|
||||
str r4, [r1, #MPLLCON] /* writing PLL register */
|
||||
/* !! order seems to be important !! */
|
||||
/* a little delay */
|
||||
ldr r3, =0x4000
|
||||
0:
|
||||
subs r3, r3, #1
|
||||
bne 0b
|
||||
|
||||
/* everything is fine now */
|
||||
mov pc, lr
|
||||
|
||||
.ltorg
|
||||
/* the literal pools origin */
|
||||
|
||||
CSDATA:
|
||||
.word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
|
||||
.word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
|
||||
.word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
|
||||
.word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
|
||||
.word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
|
||||
.word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
|
||||
.word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
|
||||
CSDATA_END:
|
||||
#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
|
||||
((bws1) << 4) + \
|
||||
((bws2) << 8) + \
|
||||
((bws3) << 12) + \
|
||||
((bws4) << 16) + \
|
||||
((bws5) << 20) + \
|
||||
((bws6) << 24) + \
|
||||
((bws7) << 28)
|
||||
|
||||
SDRAMDATA:
|
||||
/* 4Mx8x4 */
|
||||
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
|
||||
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
|
||||
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
SDRAMDATA1_END:
|
||||
#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
|
||||
((tacs) << 13) + \
|
||||
((tcos) << 11) + \
|
||||
((tacc) << 8) + \
|
||||
((tcoh) << 6) + \
|
||||
((tcah) << 4) + \
|
||||
((tacp) << 2) + \
|
||||
(pmc)
|
||||
|
||||
/* 8Mx8x4 (not implemented yet) */
|
||||
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
|
||||
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
|
||||
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
#define MK_BANKCON_SDRAM(trcd, scan) \
|
||||
((0x03) << 15) + \
|
||||
((trcd) << 2) + \
|
||||
(scan)
|
||||
|
||||
/* 2Mx8x4 (not implemented yet) */
|
||||
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
|
||||
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
|
||||
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
|
||||
((enable) << 23) + \
|
||||
((trefmd) << 22) + \
|
||||
((trp) << 20) + \
|
||||
((tsrc) << 18) + \
|
||||
(cnt)
|
||||
|
||||
/* 4Mx8x2 (not implemented yet) */
|
||||
.word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
|
||||
.word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
|
||||
.word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
SETUPDATA:
|
||||
.word 0x32410002
|
||||
/* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
|
||||
.word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
|
||||
/* PLL values for USB clock */
|
||||
.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
|
||||
|
||||
/* timing for 250 MHz*/
|
||||
0:
|
||||
.equiv CSDATA_OFFSET, (. - SETUPDATA)
|
||||
.word MK_BWSCON(DW16, \
|
||||
DW32, \
|
||||
DW32, \
|
||||
DW16 + WAIT + UBLB, \
|
||||
DW8 + UBLB, \
|
||||
DW32, \
|
||||
DW32)
|
||||
|
||||
.word MK_BANKCON(B0_Tacs_250, \
|
||||
B0_Tcos_250, \
|
||||
B0_Tacc_250, \
|
||||
B0_Tcoh_250, \
|
||||
B0_Tcah_250, \
|
||||
B0_Tacp_250, \
|
||||
B0_PMC_250)
|
||||
|
||||
.word MK_BANKCON(B1_Tacs_250, \
|
||||
B1_Tcos_250, \
|
||||
B1_Tacc_250, \
|
||||
B1_Tcoh_250, \
|
||||
B1_Tcah_250, \
|
||||
B1_Tacp_250, \
|
||||
B1_PMC_250)
|
||||
|
||||
.word MK_BANKCON(B2_Tacs, \
|
||||
B2_Tcos, \
|
||||
B2_Tacc, \
|
||||
B2_Tcoh, \
|
||||
B2_Tcah, \
|
||||
B2_Tacp, \
|
||||
B2_PMC)
|
||||
|
||||
.word MK_BANKCON(B3_Tacs, \
|
||||
B3_Tcos, \
|
||||
B3_Tacc, \
|
||||
B3_Tcoh, \
|
||||
B3_Tcah, \
|
||||
B3_Tacp, \
|
||||
B3_PMC)
|
||||
|
||||
.word MK_BANKCON(B4_Tacs_250, \
|
||||
B4_Tcos_250, \
|
||||
B4_Tacc_250, \
|
||||
B4_Tcoh_250, \
|
||||
B4_Tcah_250, \
|
||||
B4_Tacp_250, \
|
||||
B4_PMC_250)
|
||||
|
||||
.word MK_BANKCON(B5_Tacs_250, \
|
||||
B5_Tcos_250, \
|
||||
B5_Tacc_250, \
|
||||
B5_Tcoh_250, \
|
||||
B5_Tcah_250, \
|
||||
B5_Tacp_250, \
|
||||
B5_PMC_250)
|
||||
|
||||
.equiv CSDATAENTRY_SIZE, (. - 0b)
|
||||
/* 4Mx8x4 */
|
||||
0:
|
||||
.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
|
||||
.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
|
||||
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
.equiv SDRAMENTRY_SIZE, (. - 0b)
|
||||
|
||||
/* 8Mx8x4 */
|
||||
.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
|
||||
.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
|
||||
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
|
||||
/* 2Mx8x4 */
|
||||
.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
|
||||
.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
|
||||
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
|
||||
/* 4Mx8x2 */
|
||||
.word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
|
||||
.word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
|
||||
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
|
||||
.equiv SETUPENTRY_SIZE, (. - SETUPDATA)
|
||||
|
||||
.word 0x32410000
|
||||
/* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
|
||||
.word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
|
||||
/* PLL values for USB clock */
|
||||
.word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
|
||||
|
||||
/* timing for 200 MHz and default*/
|
||||
.word MK_BWSCON(DW16, \
|
||||
DW32, \
|
||||
DW32, \
|
||||
DW16 + WAIT + UBLB, \
|
||||
DW8 + UBLB, \
|
||||
DW32, \
|
||||
DW32)
|
||||
|
||||
.word MK_BANKCON(B0_Tacs_200, \
|
||||
B0_Tcos_200, \
|
||||
B0_Tacc_200, \
|
||||
B0_Tcoh_200, \
|
||||
B0_Tcah_200, \
|
||||
B0_Tacp_200, \
|
||||
B0_PMC_200)
|
||||
|
||||
.word MK_BANKCON(B1_Tacs_200, \
|
||||
B1_Tcos_200, \
|
||||
B1_Tacc_200, \
|
||||
B1_Tcoh_200, \
|
||||
B1_Tcah_200, \
|
||||
B1_Tacp_200, \
|
||||
B1_PMC_200)
|
||||
|
||||
.word MK_BANKCON(B2_Tacs, \
|
||||
B2_Tcos, \
|
||||
B2_Tacc, \
|
||||
B2_Tcoh, \
|
||||
B2_Tcah, \
|
||||
B2_Tacp, \
|
||||
B2_PMC)
|
||||
|
||||
.word MK_BANKCON(B3_Tacs, \
|
||||
B3_Tcos, \
|
||||
B3_Tacc, \
|
||||
B3_Tcoh, \
|
||||
B3_Tcah, \
|
||||
B3_Tacp, \
|
||||
B3_PMC)
|
||||
|
||||
.word MK_BANKCON(B4_Tacs_200, \
|
||||
B4_Tcos_200, \
|
||||
B4_Tacc_200, \
|
||||
B4_Tcoh_200, \
|
||||
B4_Tcah_200, \
|
||||
B4_Tacp_200, \
|
||||
B4_PMC_200)
|
||||
|
||||
.word MK_BANKCON(B5_Tacs_200, \
|
||||
B5_Tcos_200, \
|
||||
B5_Tacc_200, \
|
||||
B5_Tcoh_200, \
|
||||
B5_Tcah_200, \
|
||||
B5_Tacp_200, \
|
||||
B5_PMC_200)
|
||||
|
||||
/* 4Mx8x4 */
|
||||
.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
|
||||
.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
|
||||
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
|
||||
/* 8Mx8x4 */
|
||||
.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
|
||||
.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
|
||||
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
|
||||
/* 2Mx8x4 */
|
||||
.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
|
||||
.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
|
||||
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
|
||||
/* 4Mx8x2 */
|
||||
.word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
|
||||
.word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
|
||||
.word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
|
||||
.word 0x32 + BURST_EN
|
||||
.word 0x30
|
||||
.word 0x30
|
||||
|
||||
.equiv SETUPDATA_SIZE, (. - SETUPDATA)
|
||||
|
||||
@ -3,7 +3,7 @@
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* (C) Copyright 2002, 2010
|
||||
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
@ -27,100 +27,51 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/s3c24x0_cpu.h>
|
||||
#include <stdio_dev.h>
|
||||
#include <i2c.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/s3c24x0_cpu.h>
|
||||
|
||||
#include "vcma9.h"
|
||||
#include "../common/common_util.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define FCLK_SPEED 1
|
||||
|
||||
#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
|
||||
#define M_MDIV 0xC3
|
||||
#define M_PDIV 0x4
|
||||
#define M_SDIV 0x1
|
||||
#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
|
||||
#define M_MDIV 0xA1
|
||||
#define M_PDIV 0x3
|
||||
#define M_SDIV 0x1
|
||||
#endif
|
||||
|
||||
#define USB_CLOCK 1
|
||||
|
||||
#if USB_CLOCK==0
|
||||
#define U_M_MDIV 0xA1
|
||||
#define U_M_PDIV 0x3
|
||||
#define U_M_SDIV 0x1
|
||||
#elif USB_CLOCK==1
|
||||
#define U_M_MDIV 0x48
|
||||
#define U_M_PDIV 0x3
|
||||
#define U_M_SDIV 0x2
|
||||
#endif
|
||||
|
||||
static inline void delay(unsigned long loops)
|
||||
{
|
||||
__asm__ volatile ("1:\n"
|
||||
"subs %0, %1, #1\n"
|
||||
"bne 1b":"=r" (loops):"0" (loops));
|
||||
}
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init(void)
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
struct s3c24x0_clock_power * const clk_power =
|
||||
s3c24x0_get_base_clock_power();
|
||||
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
|
||||
|
||||
/* to reduce PLL lock time, adjust the LOCKTIME register */
|
||||
clk_power->locktime = 0xFFFFFF;
|
||||
|
||||
/* configure MPLL */
|
||||
clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
|
||||
|
||||
/* some delay between MPLL and UPLL */
|
||||
delay (4000);
|
||||
|
||||
/* configure UPLL */
|
||||
clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
|
||||
|
||||
/* some delay between MPLL and UPLL */
|
||||
delay (8000);
|
||||
|
||||
/* set up the I/O ports */
|
||||
gpio->gpacon = 0x007FFFFF;
|
||||
gpio->gpbcon = 0x002AAAAA;
|
||||
gpio->gpbup = 0x000002BF;
|
||||
gpio->gpccon = 0xAAAAAAAA;
|
||||
gpio->gpcup = 0x0000FFFF;
|
||||
gpio->gpdcon = 0xAAAAAAAA;
|
||||
gpio->gpdup = 0x0000FFFF;
|
||||
gpio->gpecon = 0xAAAAAAAA;
|
||||
gpio->gpeup = 0x000037F7;
|
||||
gpio->gpfcon = 0x00000000;
|
||||
gpio->gpfup = 0x00000000;
|
||||
gpio->gpgcon = 0xFFEAFF5A;
|
||||
gpio->gpgup = 0x0000F0DC;
|
||||
gpio->gphcon = 0x0028AAAA;
|
||||
gpio->gphup = 0x00000656;
|
||||
writel(0x007FFFFF, &gpio->gpacon);
|
||||
writel(0x002AAAAA, &gpio->gpbcon);
|
||||
writel(0x000002BF, &gpio->gpbup);
|
||||
writel(0xAAAAAAAA, &gpio->gpccon);
|
||||
writel(0x0000FFFF, &gpio->gpcup);
|
||||
writel(0xAAAAAAAA, &gpio->gpdcon);
|
||||
writel(0x0000FFFF, &gpio->gpdup);
|
||||
writel(0xAAAAAAAA, &gpio->gpecon);
|
||||
writel(0x000037F7, &gpio->gpeup);
|
||||
writel(0x00000000, &gpio->gpfcon);
|
||||
writel(0x00000000, &gpio->gpfup);
|
||||
writel(0xFFEAFF5A, &gpio->gpgcon);
|
||||
writel(0x0000F0DC, &gpio->gpgup);
|
||||
writel(0x0028AAAA, &gpio->gphcon);
|
||||
writel(0x00000656, &gpio->gphup);
|
||||
|
||||
/* setup correct IRQ modes for NIC */
|
||||
/* rising edge mode */
|
||||
gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8);
|
||||
/* setup correct IRQ modes for NIC (rising edge mode) */
|
||||
writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2);
|
||||
|
||||
/* select USB port 2 to be host or device (fix to host for now) */
|
||||
gpio->misccr |= 0x08;
|
||||
/* select USB port 2 to be host or device (setup as host for now) */
|
||||
writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
|
||||
|
||||
/* init serial */
|
||||
gd->baudrate = CONFIG_BAUDRATE;
|
||||
gd->have_console = 1;
|
||||
serial_init();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* arch number of VCMA9-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
|
||||
|
||||
@ -133,114 +84,33 @@ int board_init(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* NAND flash initialization.
|
||||
*/
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
extern ulong
|
||||
nand_probe(ulong physadr);
|
||||
|
||||
|
||||
static inline void NF_Reset(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
NF_SetCE(NFCE_LOW);
|
||||
NF_Cmd(0xFF); /* reset command */
|
||||
for(i = 0; i < 10; i++); /* tWB = 100ns. */
|
||||
NF_WaitRB(); /* wait 200~500us; */
|
||||
NF_SetCE(NFCE_HIGH);
|
||||
}
|
||||
|
||||
|
||||
static inline void NF_Init(void)
|
||||
{
|
||||
#if 0 /* a little bit too optimistic */
|
||||
#define TACLS 0
|
||||
#define TWRPH0 3
|
||||
#define TWRPH1 0
|
||||
#else
|
||||
#define TACLS 0
|
||||
#define TWRPH0 4
|
||||
#define TWRPH1 2
|
||||
#endif
|
||||
|
||||
NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
|
||||
/*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
|
||||
/* 1 1 1 1, 1 xxx, r xxx, r xxx */
|
||||
/* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
|
||||
|
||||
NF_Reset();
|
||||
}
|
||||
|
||||
void
|
||||
nand_init(void)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
NF_Init();
|
||||
#ifdef DEBUG
|
||||
printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
|
||||
#endif
|
||||
printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Get some Board/PLD Info
|
||||
*/
|
||||
|
||||
static u8 Get_PLD_ID(void)
|
||||
static u8 get_pld_reg(enum vcma9_pld_regs reg)
|
||||
{
|
||||
VCMA9_PLD * const pld = VCMA9_get_base_PLD();
|
||||
|
||||
return(pld->ID);
|
||||
return readb(VCMA9_PLD_BASE + reg);
|
||||
}
|
||||
|
||||
static u8 Get_PLD_BOARD(void)
|
||||
static u8 get_pld_version(void)
|
||||
{
|
||||
VCMA9_PLD * const pld = VCMA9_get_base_PLD();
|
||||
|
||||
return(pld->BOARD);
|
||||
return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F;
|
||||
}
|
||||
|
||||
static u8 Get_PLD_SDRAM(void)
|
||||
static u8 get_pld_revision(void)
|
||||
{
|
||||
VCMA9_PLD * const pld = VCMA9_get_base_PLD();
|
||||
|
||||
return(pld->SDRAM);
|
||||
return get_pld_reg(VCMA9_PLD_ID) & 0x0F;
|
||||
}
|
||||
|
||||
static u8 Get_PLD_Version(void)
|
||||
static uchar get_board_pcb(void)
|
||||
{
|
||||
return((Get_PLD_ID() >> 4) & 0x0F);
|
||||
return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A';
|
||||
}
|
||||
|
||||
static u8 Get_PLD_Revision(void)
|
||||
static u8 get_nr_chips(void)
|
||||
{
|
||||
return(Get_PLD_ID() & 0x0F);
|
||||
}
|
||||
|
||||
#if 0 /* not used */
|
||||
static int Get_Board_Config(void)
|
||||
{
|
||||
u8 config = Get_PLD_BOARD() & 0x03;
|
||||
|
||||
if (config == 3)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static uchar Get_Board_PCB(void)
|
||||
{
|
||||
return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
|
||||
}
|
||||
|
||||
static u8 Get_SDRAM_ChipNr(void)
|
||||
{
|
||||
switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
|
||||
switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) {
|
||||
case 0: return 4;
|
||||
case 1: return 1;
|
||||
case 2: return 2;
|
||||
@ -248,9 +118,9 @@ static u8 Get_SDRAM_ChipNr(void)
|
||||
}
|
||||
}
|
||||
|
||||
static ulong Get_SDRAM_ChipSize(void)
|
||||
static ulong get_chip_size(void)
|
||||
{
|
||||
switch (Get_PLD_SDRAM() & 0x0F) {
|
||||
switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
|
||||
case 0: return 16 * (1024*1024);
|
||||
case 1: return 32 * (1024*1024);
|
||||
case 2: return 8 * (1024*1024);
|
||||
@ -258,9 +128,10 @@ static ulong Get_SDRAM_ChipSize(void)
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
static const char * Get_SDRAM_ChipGeom(void)
|
||||
|
||||
static const char *get_chip_geom(void)
|
||||
{
|
||||
switch (Get_PLD_SDRAM() & 0x0F) {
|
||||
switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
|
||||
case 0: return "4Mx8x4";
|
||||
case 1: return "8Mx8x4";
|
||||
case 2: return "2Mx8x4";
|
||||
@ -269,23 +140,21 @@ static const char * Get_SDRAM_ChipGeom(void)
|
||||
}
|
||||
}
|
||||
|
||||
static void Show_VCMA9_Info(char *board_name, char *serial)
|
||||
static void vcma9_show_info(char *board_name, char *serial)
|
||||
{
|
||||
printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
|
||||
board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
|
||||
printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
|
||||
board_name, serial,
|
||||
get_board_pcb(), get_pld_version(), get_pld_revision());
|
||||
printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom());
|
||||
}
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
|
||||
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_chip_size() * get_nr_chips();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
*/
|
||||
@ -303,50 +172,35 @@ int checkboard(void)
|
||||
puts ("### No HW ID - assuming VCMA9");
|
||||
} else {
|
||||
b->serial_name[5] = 0;
|
||||
Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
|
||||
vcma9_show_info(b->serial_name, &b->serial_name[6]);
|
||||
}
|
||||
} else {
|
||||
s[5] = 0;
|
||||
Show_VCMA9_Info(s, &s[6]);
|
||||
vcma9_show_info(s, &s[6]);
|
||||
}
|
||||
/*printf("\n");*/
|
||||
return(0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int last_stage_init(void)
|
||||
int board_late_init(void)
|
||||
{
|
||||
checkboard();
|
||||
stdio_print_current_devices();
|
||||
/*
|
||||
* check if environment is healthy, otherwise restore values
|
||||
* from shadow copy
|
||||
*/
|
||||
check_env();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************************
|
||||
* some helping routines
|
||||
*/
|
||||
#if !CONFIG_USB_KEYBOARD
|
||||
int overwrite_console(void)
|
||||
void vcma9_print_info(void)
|
||||
{
|
||||
/* return TRUE if console should be overwritten */
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
char *s = getenv("serial#");
|
||||
|
||||
/************************************************************************
|
||||
* Print VCMA9 Info
|
||||
************************************************************************/
|
||||
void print_vcma9_info(void)
|
||||
{
|
||||
char s[50];
|
||||
int i;
|
||||
|
||||
if ((i = getenv_f("serial#", s, 32)) < 0) {
|
||||
if (!s) {
|
||||
puts ("### No HW ID - assuming VCMA9");
|
||||
printf("i %d", i*24);
|
||||
} else {
|
||||
s[5] = 0;
|
||||
Show_VCMA9_Info(s, &s[6]);
|
||||
vcma9_show_info(s, &s[6]);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -27,108 +27,19 @@
|
||||
|
||||
#include <asm/arch/s3c24x0_cpu.h>
|
||||
|
||||
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
|
||||
extern void vcma9_print_info(void);
|
||||
extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag,
|
||||
int argc, char *const argv[]);
|
||||
|
||||
void print_vcma9_info(void);
|
||||
/* VCMA9 PLD registers */
|
||||
enum vcma9_pld_regs {
|
||||
VCMA9_PLD_ID,
|
||||
VCMA9_PLD_NIC,
|
||||
VCMA9_PLD_CAN,
|
||||
VCMA9_PLD_MISC,
|
||||
VCMA9_PLD_GPCD,
|
||||
VCMA9_PLD_BOARD,
|
||||
VCMA9_PLD_SDRAM
|
||||
};
|
||||
|
||||
#if defined(CONFIG_CMD_NAND)
|
||||
typedef enum {
|
||||
NFCE_LOW,
|
||||
NFCE_HIGH
|
||||
} NFCE_STATE;
|
||||
|
||||
static inline void NF_Conf(u16 conf)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
nand->NFCONF = conf;
|
||||
}
|
||||
|
||||
static inline void NF_Cmd(u8 cmd)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
nand->NFCMD = cmd;
|
||||
}
|
||||
|
||||
static inline void NF_CmdW(u8 cmd)
|
||||
{
|
||||
NF_Cmd(cmd);
|
||||
udelay(1);
|
||||
}
|
||||
|
||||
static inline void NF_Addr(u8 addr)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
nand->NFADDR = addr;
|
||||
}
|
||||
|
||||
static inline void NF_SetCE(NFCE_STATE s)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
switch (s) {
|
||||
case NFCE_LOW:
|
||||
nand->NFCONF &= ~(1<<11);
|
||||
break;
|
||||
|
||||
case NFCE_HIGH:
|
||||
nand->NFCONF |= (1<<11);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static inline void NF_WaitRB(void)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
while (!(nand->NFSTAT & (1<<0)));
|
||||
}
|
||||
|
||||
static inline void NF_Write(u8 data)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
nand->NFDATA = data;
|
||||
}
|
||||
|
||||
static inline u8 NF_Read(void)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
return(nand->NFDATA);
|
||||
}
|
||||
|
||||
static inline void NF_Init_ECC(void)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
nand->NFCONF |= (1<<12);
|
||||
}
|
||||
|
||||
static inline u32 NF_Read_ECC(void)
|
||||
{
|
||||
struct s3c2410_nand * const nand = s3c2410_get_base_nand();
|
||||
|
||||
return(nand->NFECC);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/* VCMA9 PLD regsiters */
|
||||
typedef struct {
|
||||
u8 ID;
|
||||
u8 NIC;
|
||||
u8 CAN;
|
||||
u8 MISC;
|
||||
u8 GPCD;
|
||||
u8 BOARD;
|
||||
u8 SDRAM;
|
||||
} /*__attribute__((__packed__))*/ VCMA9_PLD;
|
||||
|
||||
#define VCMA9_PLD_BASE 0x2C000100
|
||||
static inline VCMA9_PLD *VCMA9_get_base_PLD(void)
|
||||
{
|
||||
return (VCMA9_PLD * const)VCMA9_PLD_BASE;
|
||||
}
|
||||
#define VCMA9_PLD_BASE (0x2C000100)
|
||||
|
||||
@ -33,23 +33,23 @@
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
|
||||
#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
|
||||
#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
|
||||
#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
|
||||
#define CONFIG_ARM920T /* This is an ARM920T Core */
|
||||
#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
|
||||
#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
|
||||
#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
/* input clock of PLL */
|
||||
#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
|
||||
#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
|
||||
|
||||
#define USE_920T_MMU 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
/* input clock of PLL (VCMA9 has 12MHz input clock) */
|
||||
#define CONFIG_SYS_CLK_FREQ 12000000
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
@ -59,7 +59,6 @@
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
#define CONFIG_BOOTP_HOSTNAME
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
@ -70,178 +69,198 @@
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_CMD_REGINFO
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_ELF
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_PING
|
||||
#define CONFIG_CMD_BSP
|
||||
#define CONFIG_CMD_NAND
|
||||
|
||||
#define BOARD_LATE_INIT
|
||||
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
/***********************************************************
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
|
||||
/*
|
||||
* I2C stuff:
|
||||
* the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at
|
||||
* address 0x50 with 16bit addressing
|
||||
***********************************************************/
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
*/
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
|
||||
|
||||
/* we use the built-in I2C controller */
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
|
||||
#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */
|
||||
#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */
|
||||
/* use EEPROM for environment vars */
|
||||
#define CONFIG_ENV_IS_IN_EEPROM 1
|
||||
/* environment starts at offset 0 */
|
||||
#define CONFIG_ENV_OFFSET 0x000
|
||||
/* 2KB should be more than enough */
|
||||
#define CONFIG_ENV_SIZE 0x800
|
||||
|
||||
#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */
|
||||
/* 64 bytes page write mode on 24C256 */
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_CS8900 /* we have a CS8900 on-board */
|
||||
#define CONFIG_CS8900_BASE 0x20000300
|
||||
#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
|
||||
|
||||
#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */
|
||||
#define CONFIG_CS8900 /* we have a CS8900 on-board */
|
||||
#define CONFIG_CS8900_BASE 0x20000300
|
||||
#define CONFIG_CS8900_BUS16
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_S3C24X0_SERIAL
|
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
|
||||
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
|
||||
|
||||
/************************************************************
|
||||
* USB support
|
||||
************************************************************/
|
||||
#define CONFIG_USB_OHCI 1
|
||||
#define CONFIG_USB_KEYBOARD 1
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
/* USB support (currently only works with D-cache off) */
|
||||
#define CONFIG_USB_OHCI
|
||||
#define CONFIG_USB_KEYBOARD
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* Enable needed helper functions */
|
||||
#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
|
||||
#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
|
||||
|
||||
/************************************************************
|
||||
* RTC
|
||||
************************************************************/
|
||||
#define CONFIG_RTC_S3C24X0 1
|
||||
/* RTC */
|
||||
#define CONFIG_RTC_S3C24X0
|
||||
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
|
||||
/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
#define CONFIG_BOOT_RETRY_TIME -1
|
||||
#define CONFIG_RESET_TO_RETRY
|
||||
#define CONFIG_ZERO_BOOTDELAY_CHECK
|
||||
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 10.0.0.110
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
#define CONFIG_IPADDR 10.0.0.110
|
||||
#define CONFIG_SERVERIP 10.0.0.1
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
|
||||
/* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_BAUDRATE 115200
|
||||
/* what's this ? it's not used anywhere */
|
||||
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
/* Miscellaneous configurable options */
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_SYS_PROMPT "VCMA9 # "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
/* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
/* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */
|
||||
/* to be activated as soon as s3c24x0 has print_cpuinfo support */
|
||||
/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */
|
||||
#define CONFIG_DISPLAY_BOARDINFO /* Display board info */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
|
||||
#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
|
||||
|
||||
#define CONFIG_SYS_ALT_MEMTEST
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x30800000
|
||||
|
||||
/* we configure PWM Timer 4 to 1us ~ 1MHz */
|
||||
/*#define CONFIG_SYS_HZ 1000000 */
|
||||
#define CONFIG_SYS_HZ 1562500
|
||||
/* we configure PWM Timer 4 to 1ms 1000Hz */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* valid baudrates */
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/* support BZIP2 compression */
|
||||
#define CONFIG_BZIP2 1
|
||||
/* support additional compression methods */
|
||||
#define CONFIG_BZIP2
|
||||
#define CONFIG_LZO
|
||||
#define CONFIG_LZMA
|
||||
|
||||
/************************************************************
|
||||
* Ident
|
||||
************************************************************/
|
||||
/* Ident */
|
||||
/*#define VERSION_TAG "released"*/
|
||||
#define VERSION_TAG "unstable"
|
||||
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG
|
||||
#define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \
|
||||
"MEV-10080-001 " VERSION_TAG
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
/* Physical Memory Map */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
/* FLASH and environment organization */
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_FLASH_CFI_LEGACY
|
||||
#define CONFIG_SYS_FLASH_LEGACY_512Kx16
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT (19)
|
||||
|
||||
#if 0
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
* BZIP2 / LZO / LZMA need a lot of RAM
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
|
||||
/* NAND configuration */
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
#define CONFIG_NAND_S3C2410
|
||||
#define CONFIG_SYS_S3C2410_NAND_HWECC
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x4E000000
|
||||
#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING
|
||||
#define CONFIG_S3C24XX_TACLS 1
|
||||
#define CONFIG_S3C24XX_TWRPH0 5
|
||||
#define CONFIG_S3C24XX_TWRPH1 3
|
||||
#endif
|
||||
|
||||
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
|
||||
|
||||
#define CONFIG_SYS_JFFS2_FIRST_BANK 0
|
||||
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
|
||||
|
||||
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
|
||||
/* File system */
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_UBI
|
||||
#define CONFIG_CMD_UBIFS
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_YAFFS2
|
||||
#define CONFIG_RBTREE
|
||||
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
|
||||
#define CONFIG_MTD_PARTITIONS
|
||||
#define CONFIG_CMD_MTDPARTS
|
||||
#define CONFIG_LZO
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user