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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

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This commit is contained in:
Wolfgang Denk 2010-10-23 21:59:42 +02:00
commit f2b382ea06
47 changed files with 1521 additions and 477 deletions
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9
MAINTAINERS
View File

@ -462,10 +462,11 @@ Rune Torgersen <runet@innovsys.com>
Peter Tyser <ptyser@xes-inc.com>
XPEDITE1000 PPC440GX
XPEDITE5170 MPC8640
XPEDITE5200 MPC8548
XPEDITE5370 MPC8572
xpedite1000 PPC440GX
xpedite5170 MPC8640
xpedite5200 MPC8548
xpedite5370 MPC8572
xpedite5500 P2020
David Updegraff <dave@cray.com>

4
board/xes/common/Makefile
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@ -32,7 +32,11 @@ LIB = $(obj)lib$(VENDOR).a
COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o
COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o
COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o
COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o
COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o
COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o
COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)

64
board/xes/common/board.c Normal file
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@ -0,0 +1,64 @@
/*
* Copyright 2009 Extreme Engineering Solutions, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*/
#include <common.h>
#include "fsl_8xxx_misc.h"
int checkboard(void)
{
char name[] = CONFIG_SYS_BOARD_NAME;
char *s;
#ifdef CONFIG_SYS_FORM_CUSTOM
s = "Custom";
#elif CONFIG_SYS_FORM_6U_CPCI
s = "6U CompactPCI";
#elif CONFIG_SYS_FORM_ATCA_PMC
s = "ATCA w/PMC";
#elif CONFIG_SYS_FORM_ATCA_AMC
s = "ATCA w/AMC";
#elif CONFIG_SYS_FORM_VME
s = "VME";
#elif CONFIG_SYS_FORM_6U_VPX
s = "6U VPX";
#elif CONFIG_SYS_FORM_PMC
s = "PMC";
#elif CONFIG_SYS_FORM_PCI
s = "PCI";
#elif CONFIG_SYS_FORM_3U_CPCI
s = "3U CompactPCI";
#elif CONFIG_SYS_FORM_AMC
s = "AdvancedMC";
#elif CONFIG_SYS_FORM_XMC
s = "XMC";
#elif CONFIG_SYS_FORM_PMC_XMC
s = "PMC/XMC";
#elif CONFIG_SYS_FORM_PCI_EXPRESS
s = "PCI Express";
#elif CONFIG_SYS_FORM_3U_VPX
s = "3U VPX";
#else
#error "Form factor not defined"
#endif
name[strlen(name) - 1] += get_board_derivative();
printf("Board: X-ES %s %s SBC\n", name, s);
/* Display board specific information */
puts(" ");
if ((s = getenv("board_rev")))
printf("Rev %s, ", s);
if ((s = getenv("serial#")))
printf("Serial# %s, ", s);
if ((s = getenv("board_cfg")))
printf("Cfg %s", s);
puts("\n");
return 0;
}

11
board/xes/common/fsl_8xxx_clk.c
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@ -38,7 +38,11 @@ unsigned long get_board_sys_clk(ulong dummy)
if (in_be32(&gur->gpporcr) & 0x10000)
return 66666666;
else
#ifdef CONFIG_P2020
return 100000000;
#else
return 50000000;
#endif
}
#ifdef CONFIG_MPC85xx
@ -54,6 +58,13 @@ unsigned long get_board_ddr_clk(ulong dummy)
if (ddr_ratio == 0x7)
return get_board_sys_clk(dummy);
#ifdef CONFIG_P2020
if (in_be32(&gur->gpporcr) & 0x20000)
return 66666666;
else
return 100000000;
#else
return 66666666;
#endif
}
#endif

62
board/xes/common/fsl_8xxx_misc.c Normal file
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@ -0,0 +1,62 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
#ifdef CONFIG_PCA953X
#include <pca953x.h>
/*
* Determine if a board's flashes are write protected
*/
int board_flash_wp_on(void)
{
if (pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_NVM_WP)
return 1;
return 0;
}
#endif
/*
* Return a board's derivative model number. For example:
* return 2 for the XPedite5372 and return 1 for the XPedite5201.
*/
uint get_board_derivative(void)
{
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#elif defined(CONFIG_MPC86xx)
volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR;
volatile ccsr_gur_t *gur = &immap->im_gur;
#endif
/*
* The top 4 lines of the local bus address are pulled low/high and
* can be read to determine the least significant digit of a board's
* model number.
*/
return gur->gpporcr >> 28;
}

28
board/xes/common/fsl_8xxx_misc.h Normal file
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@ -0,0 +1,28 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FSL_8XXX_MISC_H___
#define __FSL_8XXX_MISC_H___
uint get_board_derivative(void);
#endif /* __FSL_8XXX_MISC_H__ */

322
board/xes/common/fsl_8xxx_pci.c
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@ -25,10 +25,10 @@
#include <pci.h>
#include <asm/fsl_pci.h>
#include <asm/io.h>
#include <linux/compiler.h>
#include <libfdt.h>
#include <fdt_support.h>
int first_free_busno = 0;
#ifdef CONFIG_PCI1
static struct pci_controller pci1_hose;
@ -43,111 +43,6 @@ static struct pci_controller pcie2_hose;
static struct pci_controller pcie3_hose;
#endif
#ifdef CONFIG_MPC8572
/* Correlate host/agent POR bits to usable info. Table 4-14 */
struct host_agent_cfg_t {
uchar pcie_root[3];
uchar rio_host;
} host_agent_cfg[8] = {
{{0, 0, 0}, 0},
{{0, 1, 1}, 1},
{{1, 0, 1}, 0},
{{1, 1, 0}, 1},
{{0, 0, 1}, 0},
{{0, 1, 0}, 1},
{{1, 0, 0}, 0},
{{1, 1, 1}, 1}
};
/* Correlate port width POR bits to usable info. Table 4-15 */
struct io_port_cfg_t {
uchar pcie_width[3];
uchar rio_width;
} io_port_cfg[16] = {
{{0, 0, 0}, 0},
{{0, 0, 0}, 0},
{{4, 0, 0}, 0},
{{4, 4, 0}, 0},
{{0, 0, 0}, 0},
{{0, 0, 0}, 0},
{{0, 0, 0}, 4},
{{4, 2, 2}, 0},
{{0, 0, 0}, 0},
{{0, 0, 0}, 0},
{{0, 0, 0}, 0},
{{4, 0, 0}, 4},
{{4, 0, 0}, 4},
{{0, 0, 0}, 4},
{{0, 0, 0}, 4},
{{8, 0, 0}, 0},
};
#elif defined CONFIG_MPC8548
/* Correlate host/agent POR bits to usable info. Table 4-12 */
struct host_agent_cfg_t {
uchar pci_host[2];
uchar pcie_root[1];
uchar rio_host;
} host_agent_cfg[8] = {
{{1, 1}, {0}, 0},
{{1, 1}, {1}, 0},
{{1, 1}, {0}, 1},
{{0, 0}, {0}, 0}, /* reserved */
{{0, 1}, {1}, 0},
{{1, 1}, {1}, 0},
{{0, 1}, {1}, 1},
{{1, 1}, {1}, 1}
};
/* Correlate port width POR bits to usable info. Table 4-13 */
struct io_port_cfg_t {
uchar pcie_width[1];
uchar rio_width;
} io_port_cfg[8] = {
{{0}, 0},
{{0}, 0},
{{0}, 0},
{{4}, 4},
{{4}, 4},
{{0}, 4},
{{0}, 4},
{{8}, 0},
};
#elif defined CONFIG_MPC86xx
/* Correlate host/agent POR bits to usable info. Table 4-17 */
struct host_agent_cfg_t {
uchar pcie_root[2];
uchar rio_host;
} host_agent_cfg[8] = {
{{0, 0}, 0},
{{1, 0}, 1},
{{0, 1}, 0},
{{1, 1}, 1}
};
/* Correlate port width POR bits to usable info. Table 4-16 */
struct io_port_cfg_t {
uchar pcie_width[2];
uchar rio_width;
} io_port_cfg[16] = {
{{0, 0}, 0},
{{0, 0}, 0},
{{8, 0}, 0},
{{8, 8}, 0},
{{0, 0}, 0},
{{8, 0}, 4},
{{8, 0}, 4},
{{8, 0}, 4},
{{0, 0}, 0},
{{0, 0}, 4},
{{0, 0}, 4},
{{0, 0}, 4},
{{0, 0}, 0},
{{0, 0}, 0},
{{0, 8}, 0},
{{8, 8}, 0},
};
#endif
/*
* 85xx and 86xx share naming conventions, but different layout.
* Correlate names to CPU-specific values to share common
@ -173,22 +68,22 @@ struct io_port_cfg_t {
void pci_init_board(void)
{
struct pci_controller *hose;
volatile ccsr_fsl_pci_t *pci;
int width;
int host;
struct fsl_pci_info pci_info[3];
int first_free_busno = 0;
int num = 0;
int pcie_ep;
__maybe_unused int pcie_configured;
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#elif defined(CONFIG_MPC86xx)
immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_gur_t *gur = &immap->im_gur;
#endif
uint devdisr = in_be32(&gur->devdisr);
uint io_sel = (in_be32(&gur->pordevsr) & MPC8xxx_PORDEVSR_IO_SEL) >>
u32 devdisr = in_be32(&gur->devdisr);
u32 pordevsr = in_be32(&gur->pordevsr);
__maybe_unused uint io_sel = (pordevsr & MPC8xxx_PORDEVSR_IO_SEL) >>
MPC8xxx_PORDEVSR_IO_SEL_SHIFT;
uint host_agent = (in_be32(&gur->porbmsr) & MPC8xxx_PORBMSR_HA) >>
MPC8xxx_PORBMSR_HA_SHIFT;
struct pci_region *r;
#ifdef CONFIG_PCI1
uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
@ -197,49 +92,19 @@ void pci_init_board(void)
uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
width = 0; /* Silence compiler warning... */
io_sel &= 0xf; /* Silence compiler warning... */
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
hose = &pci1_hose;
host = host_agent_cfg[host_agent].pci_host[0];
r = hose->regions;
if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
SET_STD_PCI_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
pci_32 ? 32 : 64,
pcix ? "PCIX" : "PCI",
pci_spd_norm ? ">=" : "<=",
pcix ? freq * 2 : freq,
host ? "host" : "agent",
pcie_ep ? "agent" : "host",
pci_arb ? "arbiter" : "external-arbiter");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCI1_MEM_BASE,
CONFIG_SYS_PCI1_MEM_PHYS,
CONFIG_SYS_PCI1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCI1_IO_BASE,
CONFIG_SYS_PCI1_IO_PHYS,
CONFIG_SYS_PCI1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
/* Unlock inbound PCI configuration cycles */
if (!host)
fsl_pci_config_unlock(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCI1 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pci1_hose, first_free_busno);
} else {
printf(" PCI1: disabled\n");
}
@ -247,148 +112,53 @@ void pci_init_board(void)
/* PCI1 not present on MPC8572 */
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
#endif
#ifdef CONFIG_PCIE1
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
hose = &pcie1_hose;
host = host_agent_cfg[host_agent].pcie_root[0];
width = io_port_cfg[io_sel].pcie_width[0];
r = hose->regions;
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
printf("\n PCIE1 connected as %s (x%d)",
host ? "Root Complex" : "Endpoint", width);
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug(" with errors. Clearing. Now 0x%08x",
in_be32(&pci->pme_msg_det));
}
printf("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE1_MEM_BASE,
CONFIG_SYS_PCIE1_MEM_PHYS,
CONFIG_SYS_PCIE1_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE1_IO_BASE,
CONFIG_SYS_PCIE1_IO_PHYS,
CONFIG_SYS_PCIE1_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
/* Unlock inbound PCI configuration cycles */
if (!host)
fsl_pci_config_unlock(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCIE1 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf(" PCIE1 connected as %s\n",
pcie_ep ? "Endpoint" : "Root Complex");
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf(" PCIE1: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
#endif /* CONFIG_PCIE1 */
#ifdef CONFIG_PCIE2
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
hose = &pcie2_hose;
host = host_agent_cfg[host_agent].pcie_root[1];
width = io_port_cfg[io_sel].pcie_width[1];
r = hose->regions;
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
printf("\n PCIE2 connected as %s (x%d)",
host ? "Root Complex" : "Endpoint", width);
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug(" with errors. Clearing. Now 0x%08x",
in_be32(&pci->pme_msg_det));
}
printf("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE2_MEM_BASE,
CONFIG_SYS_PCIE2_MEM_PHYS,
CONFIG_SYS_PCIE2_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE2_IO_BASE,
CONFIG_SYS_PCIE2_IO_PHYS,
CONFIG_SYS_PCIE2_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
/* Unlock inbound PCI configuration cycles */
if (!host)
fsl_pci_config_unlock(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCIE2 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf(" PCIE2 connected as %s\n",
pcie_ep ? "Endpoint" : "Root Complex");
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
printf(" PCIE2: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
#endif /* CONFIG_PCIE2 */
#ifdef CONFIG_PCIE3
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
hose = &pcie3_hose;
host = host_agent_cfg[host_agent].pcie_root[2];
width = io_port_cfg[io_sel].pcie_width[2];
r = hose->regions;
pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
if (width && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
printf("\n PCIE3 connected as %s (x%d)",
host ? "Root Complex" : "Endpoint", width);
if (in_be32(&pci->pme_msg_det)) {
out_be32(&pci->pme_msg_det, 0xffffffff);
debug(" with errors. Clearing. Now 0x%08x",
in_be32(&pci->pme_msg_det));
}
printf("\n");
/* outbound memory */
pci_set_region(r++,
CONFIG_SYS_PCIE3_MEM_BASE,
CONFIG_SYS_PCIE3_MEM_PHYS,
CONFIG_SYS_PCIE3_MEM_SIZE,
PCI_REGION_MEM);
/* outbound io */
pci_set_region(r++,
CONFIG_SYS_PCIE3_IO_BASE,
CONFIG_SYS_PCIE3_IO_PHYS,
CONFIG_SYS_PCIE3_IO_SIZE,
PCI_REGION_IO);
hose->region_count = r - hose->regions;
hose->first_busno = first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
/* Unlock inbound PCI configuration cycles */
if (!host)
fsl_pci_config_unlock(hose);
first_free_busno = hose->last_busno + 1;
printf(" PCIE3 on bus %02x - %02x\n",
hose->first_busno, hose->last_busno);
if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf(" PCIE3 connected as %s\n",
pcie_ep ? "Endpoint" : "Root Complex");
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
} else {
printf(" PCIE3: disabled\n");
}
#else
setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);

0
board/xes/xpedite5170/Makefile → board/xes/xpedite517x/Makefile
View File

0
board/xes/xpedite5170/ddr.c → board/xes/xpedite517x/ddr.c
View File

0
board/xes/xpedite5170/law.c → board/xes/xpedite517x/law.c
View File

20
board/xes/xpedite5170/xpedite5170.c → board/xes/xpedite517x/xpedite517x.c
View File

@ -26,30 +26,12 @@
#include <asm/io.h>
#include <fdt_support.h>
#include <pca953x.h>
#include "../common/fsl_8xxx_misc.h"
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_PCI)
extern void ft_board_pci_setup(void *blob, bd_t *bd);
#endif
int checkboard(void)
{
char *s;
printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
printf(" ");
s = getenv("board_rev");
if (s)
printf("Rev %s, ", s);
s = getenv("serial#");
if (s)
printf("Serial# %s, ", s);
s = getenv("board_cfg");
if (s)
printf("Cfg %s", s);
printf("\n");
return 0;
}
/*
* Print out which flash was booted from and if booting from the 2nd flash,
* swap flash chip selects to maintain consistent flash numbering/addresses.

0
board/xes/xpedite5200/Makefile → board/xes/xpedite520x/Makefile
View File

0
board/xes/xpedite5200/ddr.c → board/xes/xpedite520x/ddr.c
View File

0
board/xes/xpedite5200/law.c → board/xes/xpedite520x/law.c
View File

0
board/xes/xpedite5200/tlb.c → board/xes/xpedite520x/tlb.c
View File

27
board/xes/xpedite5200/xpedite5200.c → board/xes/xpedite520x/xpedite520x.c
View File

@ -36,33 +36,6 @@
extern void ft_board_pci_setup(void *blob, bd_t *bd);
int checkboard(void)
{
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
char *s;
printf("Board: X-ES %s PMC\n", CONFIG_SYS_BOARD_NAME);
printf(" ");
s = getenv("board_rev");
if (s)
printf("Rev %s, ", s);
s = getenv("serial#");
if (s)
printf("Serial# %s, ", s);
s = getenv("board_cfg");
if (s)
printf("Cfg %s", s);
printf("\n");
out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error IRQs */
out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error IRQs */
out_be32(&ecm->eedr, 0xffffffff); /* Clear ecm errors */
out_be32(&ecm->eeer, 0xffffffff); /* Enable ecm errors */
return 0;
}
static void flash_cs_fixup(void)
{
int flash_sel;

0
board/xes/xpedite5370/Makefile → board/xes/xpedite537x/Makefile
View File

0
board/xes/xpedite5370/ddr.c → board/xes/xpedite537x/ddr.c
View File

0
board/xes/xpedite5370/law.c → board/xes/xpedite537x/law.c
View File

0
board/xes/xpedite5370/tlb.c → board/xes/xpedite537x/tlb.c
View File

20
board/xes/xpedite5370/xpedite5370.c → board/xes/xpedite537x/xpedite537x.c
View File

@ -36,26 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
extern void ft_board_pci_setup(void *blob, bd_t *bd);
int checkboard(void)
{
char *s;
printf("Board: X-ES %s 3U VPX SBC\n", CONFIG_SYS_BOARD_NAME);
printf(" ");
s = getenv("board_rev");
if (s)
printf("Rev %s, ", s);
s = getenv("serial#");
if (s)
printf("Serial# %s, ", s);
s = getenv("board_cfg");
if (s)
printf("Cfg %s", s);
printf("\n");
return 0;
}
static void flash_cs_fixup(void)
{
int flash_sel;

39
board/xes/xpedite550x/Makefile Normal file
View File

@ -0,0 +1,39 @@
#
# Copyright 2007-2008 Freescale Semiconductor, Inc.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += ddr.o
COBJS-y += law.o
COBJS-y += tlb.o
SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
SOBJS := $(addprefix $(obj),$(SOBJS-y))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS) $(SOBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

165
board/xes/xpedite550x/ddr.c Normal file
View File

@ -0,0 +1,165 @@
/*
* Copyright 2010 Extreme Engineering Solutions, Inc.
* Copyright 2007-2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#include <asm/fsl_ddr_sdram.h>
#include <asm/fsl_ddr_dimm_params.h>
static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
{
i2c_read(i2c_address, SPD_EEPROM_OFFSET, 2, (uchar *)spd,
sizeof(ddr3_spd_eeprom_t));
}
void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
unsigned int ctrl_num)
{
unsigned int i;
unsigned int i2c_address = 0;
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
if (ctrl_num == 0 && i == 0)
i2c_address = SPD_EEPROM_ADDRESS1;
get_spd(&(ctrl_dimms_spd[i]), i2c_address);
}
}
unsigned int fsl_ddr_get_mem_data_rate(void)
{
return get_ddr_freq(0);
}
/*
* There are traditionally three board-specific SDRAM timing parameters
* which must be calculated based on the particular PCB artwork. These are:
* 1.) CPO (Read Capture Delay)
* - TIMING_CFG_2 register
* Source: Calculation based on board trace lengths and
* chip-specific internal delays.
* 2.) CLK_ADJUST (Clock and Addr/Cmd alignment control)
* - DDR_SDRAM_CLK_CNTL register
* Source: Signal Integrity Simulations
* 3.) 2T Timing on Addr/Ctl
* - TIMING_CFG_2 register
* Source: Signal Integrity Simulations
* Usually only needed with heavy load/very high speed (>DDR2-800)
*
* ====== XPedite550x DDR3-800 read delay calculations ======
*
* The P2020 processor provides an autoleveling option. Setting CPO to
* 0x1f enables this auto configuration.
*/
typedef struct {
unsigned short datarate_mhz_low;
unsigned short datarate_mhz_high;
unsigned char clk_adjust;
unsigned char cpo;
} board_specific_parameters_t;
const board_specific_parameters_t board_specific_parameters[][20] = {
{
/* Controller 0 */
{
/* DDR3-600/667 */
.datarate_mhz_low = 500,
.datarate_mhz_high = 750,
.clk_adjust = 5,
.cpo = 31,
},
{
/* DDR3-800 */
.datarate_mhz_low = 750,
.datarate_mhz_high = 850,
.clk_adjust = 5,
.cpo = 31,
},
},
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const board_specific_parameters_t *pbsp =
&(board_specific_parameters[ctrl_num][0]);
u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
sizeof(board_specific_parameters[0][0]);
u32 i;
ulong ddr_freq;
/*
* Set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
* that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
* there are two dimms in the controller, set odt_rd_cfg to 3 and
* odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
*/
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i&1) { /* odd CS */
popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 0;
} else { /* even CS */
if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
popts->cs_local_opts[i].odt_rd_cfg = 0;
popts->cs_local_opts[i].odt_wr_cfg = 4;
} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
popts->cs_local_opts[i].odt_rd_cfg = 3;
popts->cs_local_opts[i].odt_wr_cfg = 3;
}
}
}
/*
* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
for (i = 0; i < num_params; i++) {
if (ddr_freq >= pbsp->datarate_mhz_low &&
ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->cpo_override = pbsp->cpo;
popts->twoT_en = 0;
}
pbsp++;
}
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Enable on-die termination.
* From the Micron Technical Node TN-41-04, RTT_Nom should typically
* be 30 to 40 ohms, while RTT_WR should be 120 ohms. Setting RTT_WR
* is handled in the Freescale DDR3 driver. Set RTT_Nom here.
*/
popts->rtt_override = 1;
popts->rtt_override_value = 3;
}

54
board/xes/xpedite550x/law.c Normal file
View File

@ -0,0 +1,54 @@
/*
* Copyright 2010 Extreme Engineering Solutions, Inc.
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
/*
* Notes:
* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
* If flash is 8M at default position (last 8M), no LAW needed.
*/
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE2, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_NAND_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_1G, LAW_TRGT_IF_PCIE_1),
SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
#endif
#ifdef CONFIG_SYS_PCIE2_MEM_PHYS
SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_2),
#endif
#ifdef CONFIG_SYS_PCIE3_MEM_PHYS
SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_3),
SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_3),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

98
board/xes/xpedite550x/tlb.c Normal file
View File

@ -0,0 +1,98 @@
/*
* Copyright 2008 Extreme Engineering Solutions, Inc.
* Copyright 2008 Freescale Semiconductor, Inc.
*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* W**G* - NOR flashes */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE2, CONFIG_SYS_FLASH_BASE2,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1),
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_1M, 1),
/* *I*G* - NAND flash */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 2, BOOKE_PAGESZ_1M, 1),
/* **M** - Boot page for secondary processors */
SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR, CONFIG_BPTR_VIRT_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
0, 3, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_PCIE1
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_1G, 1),
#endif
#ifdef CONFIG_PCIE2
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_PHYS, CONFIG_SYS_PCIE2_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 5, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_PCIE3
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_256M, 1),
#endif
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
/* *I*G* - PCIe */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_64M, 1),
#endif
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

107
board/xes/xpedite550x/xpedite550x.c Normal file
View File

@ -0,0 +1,107 @@
/*
* Copyright 2010 Extreme Engineering Solutions, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_pci.h>
#include <asm/io.h>
#include <asm/cache.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <pca953x.h>
DECLARE_GLOBAL_DATA_PTR;
extern void ft_board_pci_setup(void *blob, bd_t *bd);
static void flash_cs_fixup(void)
{
int flash_sel;
/*
* Print boot dev and swap flash flash chip selects if booted from 2nd
* flash. Swapping chip selects presents user with a common memory
* map regardless of which flash was booted from.
*/
flash_sel = !((pca953x_get_val(CONFIG_SYS_I2C_PCA953X_ADDR0) &
CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS));
printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
if (flash_sel) {
set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
}
}
int board_early_init_r(void)
{
/* Initialize PCA9557 devices */
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR0, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR1, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR2, 0xff, 0);
pca953x_set_pol(CONFIG_SYS_I2C_PCA953X_ADDR3, 0xff, 0);
/*
* Remap NOR flash region to caching-inhibited
* so that flash can be erased/programmed properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
/* Invalidate existing TLB entry for NOR flash */
disable_tlb(0);
set_tlb(1, (CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
(CONFIG_SYS_FLASH_BASE2 & 0xf0000000),
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256M, 1);
flash_cs_fixup();
return 0;
}
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
#ifdef CONFIG_PCI
ft_board_pci_setup(blob, bd);
#endif
ft_cpu_setup(blob, bd);
}
#endif
#ifdef CONFIG_MP
extern void cpu_mp_lmb_reserve(struct lmb *lmb);
void board_lmb_reserve(struct lmb *lmb)
{
cpu_mp_lmb_reserve(lmb);
}
#endif

9
boards.cfg
View File

@ -556,8 +556,9 @@ MPC8540ADS powerpc mpc85xx mpc8540ads freescale
MPC8544DS powerpc mpc85xx mpc8544ds freescale
MPC8560ADS powerpc mpc85xx mpc8560ads freescale
MPC8568MDS powerpc mpc85xx mpc8568mds freescale
XPEDITE5200 powerpc mpc85xx xpedite5200 xes
XPEDITE5370 powerpc mpc85xx xpedite5370 xes
xpedite520x powerpc mpc85xx - xes
xpedite537x powerpc mpc85xx - xes
xpedite550x powerpc mpc85xx - xes
sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540
sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33
@ -597,7 +598,7 @@ P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,NAND
P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SDCARD
sbc8641d powerpc mpc86xx
MPC8610HPCD powerpc mpc86xx mpc8610hpcd freescale
XPEDITE5170 powerpc mpc86xx xpedite5170 xes
xpedite517x powerpc mpc86xx - xes
MPC8641HPCN powerpc mpc86xx mpc8641hpcn freescale - MPC8641HPCN
cogent_mpc8xx powerpc mpc8xx cogent
ESTEEM192E powerpc mpc8xx esteem192e
@ -648,7 +649,7 @@ CPCIISER4 powerpc ppc4xx cpciiser4 esd
DASA_SIM powerpc ppc4xx dasa_sim esd
PMC405DE powerpc ppc4xx pmc405de esd
METROBOX powerpc ppc4xx metrobox sandburst
XPEDITE1000 powerpc ppc4xx xpedite1000 xes
xpedite1000 powerpc ppc4xx - xes
korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT
haleakala powerpc ppc4xx kilauea amcc - kilauea:HALEAKALA
sycamore powerpc ppc4xx walnut amcc - walnut

13
common/cmd_pci.c
View File

@ -497,6 +497,10 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
if ((bdf = get_pci_dev(argv[2])) == -1)
return 1;
break;
#ifdef CONFIG_CMD_PCI_ENUM
case 'e':
break;
#endif
default: /* scan bus */
value = 1; /* short listing */
bdf = 0; /* bus number */
@ -518,6 +522,11 @@ int do_pci (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
return 0;
case 'd': /* display */
return pci_cfg_display(bdf, addr, size, value);
#ifdef CONFIG_CMD_PCI_ENUM
case 'e':
pci_init();
return 0;
#endif
case 'n': /* next */
if (argc < 4)
goto usage;
@ -545,6 +554,10 @@ U_BOOT_CMD(
"list and access PCI Configuration Space",
"[bus] [long]\n"
" - short or long list of PCI devices on bus 'bus'\n"
#ifdef CONFIG_CMD_PCI_ENUM
"pci enum\n"
" - re-enumerate PCI buses\n"
#endif
"pci header b.d.f\n"
" - show header of PCI device 'bus.device.function'\n"
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"

19
doc/README.POST
View File

@ -659,12 +659,19 @@ not need any modifications for porting them to another board/CPU.
2.2.2.1. I2C test
For verifying the I2C bus, a full I2C bus scanning will be performed
using the i2c_probe() routine. If any I2C device is found, the test
will be considered as passed, otherwise failed. This particular way
will be used because it provides the most common method of testing.
For example, using the internal loopback mode of the CPM I2C
controller for testing would not work on boards where the software
I2C driver (also known as bit-banged driver) is used.
using the i2c_probe() routine. If a board defines
CONFIG_SYS_POST_I2C_ADDRS the I2C test will pass if all devices
listed in CONFIG_SYS_POST_I2C_ADDRS are found, and no additional
devices are detected. If CONFIG_SYS_POST_I2C_ADDRS is not defined
the test will pass if any I2C device is found.
The CONFIG_SYS_POST_I2C_IGNORES define can be used to list I2C
devices which may or may not be present when using
CONFIG_SYS_POST_I2C_ADDRS. The I2C POST test will pass regardless
if the devices in CONFIG_SYS_POST_I2C_IGNORES are found or not.
This is useful in cases when I2C devices are optional (eg on a
daughtercard that may or may not be present) or not critical
to board operation.
2.2.2.2. Watchdog timer test

3
drivers/pci/fsl_pci_init.c
View File

@ -91,6 +91,9 @@ int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
{
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
/* Reset hose to make sure its in a clean state */
memset(hose, 0, sizeof(struct pci_controller));
pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
return fsl_is_pci_agent(hose);

4
drivers/pci/pci.c
View File

@ -139,7 +139,7 @@ void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
*
*/
static struct pci_controller* hose_head = NULL;
static struct pci_controller* hose_head;
void pci_register_hose(struct pci_controller* hose)
{
@ -640,6 +640,8 @@ void pci_init(void)
}
#endif /* CONFIG_PCI_BOOTDELAY */
hose_head = NULL;
/* now call board specific pci_init()... */
pci_init_board();
}

6
include/configs/KUP4K.h
View File

@ -139,9 +139,9 @@
/* List of I2C addresses to be verified by POST */
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_PICIO_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
}
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
}
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */

6
include/configs/KUP4X.h
View File

@ -149,9 +149,9 @@
/* List of I2C addresses to be verified by POST */
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_PICIO_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
}
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
}
#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */

8
include/configs/TB5200.h
View File

@ -251,10 +251,10 @@
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
/* List of I2C addresses to be verified by POST */
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
CONFIG_SYS_I2C_SLAVE }
#undef CONFIG_SYS_POST_I2C_ADDRS
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
CONFIG_SYS_I2C_SLAVE}
/*
* Flash configuration

8
include/configs/TQM5200.h
View File

@ -370,10 +370,10 @@
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_HWMON_ADDR, \
CONFIG_SYS_I2C_SLAVE }
#undef CONFIG_SYS_POST_I2C_ADDRS
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_HWMON_ADDR, \
CONFIG_SYS_I2C_SLAVE}
#endif
/*

4
include/configs/cm5200.h
View File

@ -80,7 +80,9 @@
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
/* List of I2C addresses to be verified by POST */
#define I2C_ADDR_LIST { CONFIG_SYS_I2C_SLAVE, CONFIG_SYS_I2C_IO, CONFIG_SYS_I2C_EEPROM }
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
CONFIG_SYS_I2C_IO, \
CONFIG_SYS_I2C_EEPROM}
/* display image timestamps */
#define CONFIG_TIMESTAMP 1

2
include/configs/corenet_ds.h
View File

@ -213,7 +213,7 @@
#endif
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

50
include/configs/lwmon.h
View File

@ -349,32 +349,32 @@
/* List of I2C addresses to be verified by POST */
#ifdef CONFIG_USE_FRAM
#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
CONFIG_SYS_I2C_SYSMON_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
CONFIG_SYS_I2C_POWER_A_ADDR, \
CONFIG_SYS_I2C_POWER_B_ADDR, \
CONFIG_SYS_I2C_KEYBD_ADDR, \
CONFIG_SYS_I2C_PICIO_ADDR, \
CONFIG_SYS_I2C_EEPROM_ADDR, \
}
#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
CONFIG_SYS_I2C_SYSMON_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
CONFIG_SYS_I2C_POWER_A_ADDR, \
CONFIG_SYS_I2C_POWER_B_ADDR, \
CONFIG_SYS_I2C_KEYBD_ADDR, \
CONFIG_SYS_I2C_PICIO_ADDR, \
CONFIG_SYS_I2C_EEPROM_ADDR, \
}
#else /* Use EEPROM - which show up on 8 consequtive addresses */
#define I2C_ADDR_LIST { /* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
CONFIG_SYS_I2C_SYSMON_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
CONFIG_SYS_I2C_POWER_A_ADDR, \
CONFIG_SYS_I2C_POWER_B_ADDR, \
CONFIG_SYS_I2C_KEYBD_ADDR, \
CONFIG_SYS_I2C_PICIO_ADDR, \
CONFIG_SYS_I2C_EEPROM_ADDR+0, \
CONFIG_SYS_I2C_EEPROM_ADDR+1, \
CONFIG_SYS_I2C_EEPROM_ADDR+2, \
CONFIG_SYS_I2C_EEPROM_ADDR+3, \
CONFIG_SYS_I2C_EEPROM_ADDR+4, \
CONFIG_SYS_I2C_EEPROM_ADDR+5, \
CONFIG_SYS_I2C_EEPROM_ADDR+6, \
CONFIG_SYS_I2C_EEPROM_ADDR+7, \
}
#define CONFIG_SYS_POST_I2C_ADDRS {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
CONFIG_SYS_I2C_SYSMON_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR, \
CONFIG_SYS_I2C_POWER_A_ADDR, \
CONFIG_SYS_I2C_POWER_B_ADDR, \
CONFIG_SYS_I2C_KEYBD_ADDR, \
CONFIG_SYS_I2C_PICIO_ADDR, \
CONFIG_SYS_I2C_EEPROM_ADDR+0, \
CONFIG_SYS_I2C_EEPROM_ADDR+1, \
CONFIG_SYS_I2C_EEPROM_ADDR+2, \
CONFIG_SYS_I2C_EEPROM_ADDR+3, \
CONFIG_SYS_I2C_EEPROM_ADDR+4, \
CONFIG_SYS_I2C_EEPROM_ADDR+5, \
CONFIG_SYS_I2C_EEPROM_ADDR+6, \
CONFIG_SYS_I2C_EEPROM_ADDR+7, \
}
#endif /* CONFIG_USE_FRAM */
/*-----------------------------------------------------------------------

15
include/configs/lwmon5.h
View File

@ -306,14 +306,13 @@
#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
#define I2C_ADDR_LIST { \
CONFIG_SYS_I2C_RTC_ADDR, \
CONFIG_SYS_I2C_EEPROM_CPU_ADDR, \
CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
CONFIG_SYS_I2C_DSPIC_ADDR, \
CONFIG_SYS_I2C_DSPIC_2_ADDR, \
CONFIG_SYS_I2C_DSPIC_KEYB_ADDR, \
CONFIG_SYS_I2C_DSPIC_IO_ADDR }
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
CONFIG_SYS_I2C_DSPIC_ADDR, \
CONFIG_SYS_I2C_DSPIC_2_ADDR, \
CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
CONFIG_SYS_I2C_DSPIC_IO_ADDR }
/*
* Pass open firmware flat tree

8
include/configs/spieval.h
View File

@ -271,10 +271,10 @@
/* List of I2C addresses to be verified by POST */
#if defined (CONFIG_MINIFAP)
#undef I2C_ADDR_LIST
#define I2C_ADDR_LIST { CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_HWMON_ADDR, \
CONFIG_SYS_I2C_SLAVE }
#undef CONFIG_SYS_POST_I2C_ADDRS
#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_HWMON_ADDR, \
CONFIG_SYS_I2C_SLAVE}
#endif
/*

5
include/configs/XPEDITE1000.h → include/configs/xpedite1000.h
View File

@ -33,6 +33,7 @@
/* High Level Configuration Options */
#define CONFIG_XPEDITE1000 1
#define CONFIG_SYS_BOARD_NAME "XPedite1000"
#define CONFIG_SYS_FORM_PMC 1
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_440 1
#define CONFIG_440GX 1 /* 440 GX */
@ -341,8 +342,8 @@ extern void out32(unsigned int, unsigned long);
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
"osfile=/home/user/uImage-XPedite1000\0" \
"fdtfile=/home/user/xpedite1000.dtb\0" \
"osfile=/home/user/board.uImage\0" \
"fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \

37
include/configs/XPEDITE5170.h → include/configs/xpedite517x.h
View File

@ -22,7 +22,7 @@
*/
/*
* xpedite5170 board configuration file
* xpedite517x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@ -34,6 +34,7 @@
#define CONFIG_MPC8641 1 /* MPC8641 specific */
#define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
#define CONFIG_SYS_BOARD_NAME "XPedite5170"
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#define CONFIG_BAT_RW 1 /* Use common BAT rw code */
@ -107,6 +108,21 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\
CONFIG_SYS_POST_I2C)
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
CONFIG_SYS_I2C_DS4510_ADDR, \
CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_LM90_ADDR, \
CONFIG_SYS_I2C_PCA9553_ADDR, \
CONFIG_SYS_I2C_PCA953X_ADDR0, \
CONFIG_SYS_I2C_PCA953X_ADDR1, \
CONFIG_SYS_I2C_PCA953X_ADDR2, \
CONFIG_SYS_I2C_PCA953X_ADDR3, \
CONFIG_SYS_I2C_PEX8518_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR}
/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */
#define I2C_ADDR_IGNORE_LIST {0x50}
/*
* Memory map
@ -258,6 +274,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
#define CONFIG_DTT_DS1621
#define CONFIG_DTT_SENSORS { 0 }
#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
@ -281,6 +298,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62
/*
* PU = pulled high, PD = pulled low
@ -324,18 +342,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* PCIE1 - PEX8518 */
#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
/* PCIE2 - VPX P1 */
#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
@ -545,6 +563,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SNTP
@ -725,8 +744,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
"osfile=/home/user/uImage-XPedite5170\0" \
"fdtfile=/home/user/xpedite5170.dtb\0" \
"osfile=/home/user/board.uImage\0" \
"fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \

26
include/configs/XPEDITE5200.h → include/configs/xpedite520x.h
View File

@ -22,7 +22,7 @@
*/
/*
* xpedite5200 board configuration file
* xpedite520x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@ -36,6 +36,7 @@
#define CONFIG_MPC8548 1
#define CONFIG_XPEDITE5200 1
#define CONFIG_SYS_BOARD_NAME "XPedite5200"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#ifndef CONFIG_SYS_TEXT_BASE
@ -92,6 +93,13 @@
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
CONFIG_SYS_POST_I2C)
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_PCA953X_ADDR0, \
CONFIG_SYS_I2C_PCA953X_ADDR1, \
CONFIG_SYS_I2C_RTC_ADDR}
/*
* Memory map
@ -250,7 +258,7 @@
#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
#define CONFIG_SYS_PCA953X_FLASH_WP 0x20
#define CONFIG_SYS_PCA953X_NVM_WP 0x20
#define CONFIG_SYS_PCA953X_MONARCH 0x40
#define CONFIG_SYS_PCA953X_EREADY 0x80
@ -264,14 +272,17 @@
#define CONFIG_SYS_PCA953X_P14_IO6 0x40
#define CONFIG_SYS_PCA953X_P14_IO7 0x80
/* 12-bit ADC used to measure CPU diode */
#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
@ -339,6 +350,7 @@
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_REGINFO
@ -521,8 +533,8 @@
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
"osfile=/home/user/uImage-XPedite5200\0" \
"fdtfile=/home/user/xpedite5200.dtb\0" \
"osfile=/home/user/board.uImage\0" \
"fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \

35
include/configs/XPEDITE5370.h → include/configs/xpedite537x.h
View File

@ -22,7 +22,7 @@
*/
/*
* xpedite5370 board configuration file
* xpedite537x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@ -36,6 +36,7 @@
#define CONFIG_MPC8572 1
#define CONFIG_XPEDITE5370 1
#define CONFIG_SYS_BOARD_NAME "XPedite5370"
#define CONFIG_SYS_FORM_3U_VPX 1
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#ifndef CONFIG_SYS_TEXT_BASE
@ -110,6 +111,20 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
CONFIG_SYS_POST_I2C)
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
CONFIG_SYS_I2C_DS4510_ADDR, \
CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_LM90_ADDR, \
CONFIG_SYS_I2C_PCA953X_ADDR0, \
CONFIG_SYS_I2C_PCA953X_ADDR1, \
CONFIG_SYS_I2C_PCA953X_ADDR2, \
CONFIG_SYS_I2C_PCA953X_ADDR3, \
CONFIG_SYS_I2C_PEX8518_ADDR, \
CONFIG_SYS_I2C_RTC_ADDR}
/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
#define I2C_ADDR_IGNORE_LIST {0x50}
/*
* Memory map
@ -265,6 +280,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
#define CONFIG_DTT_DS1621
#define CONFIG_DTT_SENSORS { 0 }
#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
@ -334,18 +350,18 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* PCIE1 - VPX P1 */
#define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
/* PCIE2 - PEX8518 */
#define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
@ -396,6 +412,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
@ -578,8 +595,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
"osfile=/home/user/uImage-XPedite5370\0" \
"fdtfile=/home/user/xpedite5370.dtb\0" \
"osfile=/home/user/board.uImage\0" \
"fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \

607
include/configs/xpedite550x.h Normal file
View File

@ -0,0 +1,607 @@
/*
* Copyright 2010 Extreme Engineering Solutions, Inc.
* Copyright 2007-2008 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* xpedite550x board configuration file
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* High Level Configuration Options
*/
#define CONFIG_BOOKE 1 /* BOOKE */
#define CONFIG_E500 1 /* BOOKE e500 family */
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
#define CONFIG_P2020 1
#define CONFIG_XPEDITE550X 1
#define CONFIG_SYS_BOARD_NAME "XPedite5500"
#define CONFIG_SYS_FORM_PMC_XMC 1
#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
#define CONFIG_PCI 1 /* Enable PCI/PCIE */
#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
#define CONFIG_FSL_ELBC 1
/*
* Multicore config
*/
#define CONFIG_MP
#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
/*
* DDR config
*/
#define CONFIG_FSL_DDR3
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
#define CONFIG_DDR_SPD
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#define SPD_EEPROM_ADDRESS1 0x54
#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
#define CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_VERY_BIG_RAM
#ifndef __ASSEMBLY__
extern unsigned long get_board_sys_clk(unsigned long dummy);
extern unsigned long get_board_ddr_clk(unsigned long dummy);
#endif
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
/*
* These can be toggled for performance analysis, otherwise use default.
*/
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
#define CONFIG_ENABLE_36BIT_PHYS 1
/*
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*/
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
/*
* Diagnostics
*/
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x20000000
#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
CONFIG_SYS_POST_I2C)
#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
CONFIG_SYS_I2C_LM75_ADDR, \
CONFIG_SYS_I2C_LM90_ADDR, \
CONFIG_SYS_I2C_PCA953X_ADDR0, \
CONFIG_SYS_I2C_PCA953X_ADDR2, \
CONFIG_SYS_I2C_PCA953X_ADDR3, \
CONFIG_SYS_I2C_RTC_ADDR}
/*
* Memory map
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
* 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
* 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
* 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
* 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
* 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
* 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
* 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
* 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
*/
#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
/*
* NAND flash configuration
*/
#define CONFIG_SYS_NAND_BASE 0xef800000
#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
CONFIG_SYS_NAND_BASE2}
#define CONFIG_SYS_MAX_NAND_DEVICE 2
#define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
#define CONFIG_NAND_FSL_ELBC
/*
* NOR flash configuration
*/
#define CONFIG_SYS_FLASH_BASE 0xf8000000
#define CONFIG_SYS_FLASH_BASE2 0xf0000000
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
{0xf7f40000, 0xc0000} }
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
/*
* Chip select configuration
*/
/* NOR Flash 0 on CS0 */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
BR_PS_16 | \
BR_V)
#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
OR_GPCM_CSNT | \
OR_GPCM_XACS | \
OR_GPCM_ACS_DIV2 | \
OR_GPCM_SCY_8 | \
OR_GPCM_TRLX | \
OR_GPCM_EHTR | \
OR_GPCM_EAD)
/* NOR Flash 1 on CS1 */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
BR_PS_16 | \
BR_V)
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
/* NAND flash on CS2 */
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
(2<<BR_DECC_SHIFT) | \
BR_PS_8 | \
BR_MS_FCM | \
BR_V)
/* NAND flash on CS2 */
#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
OR_FCM_PGS | \
OR_FCM_CSCT | \
OR_FCM_CST | \
OR_FCM_CHT | \
OR_FCM_SCY_1 | \
OR_FCM_TRLX | \
OR_FCM_EHTR)
/* NAND flash on CS3 */
#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
(2<<BR_DECC_SHIFT) | \
BR_PS_8 | \
BR_MS_FCM | \
BR_V)
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
/*
* Use L1 as initial stack
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
#define CONFIG_SYS_INIT_RAM_END 0x00004000
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
/*
* Serial Port
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
#define CONFIG_BAUDRATE 115200
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
/*
* Use the HUSH parser
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* Pass open firmware flat tree
*/
#define CONFIG_OF_LIBFDT 1
#define CONFIG_OF_BOARD_SETUP 1
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
#define CONFIG_FDT_FIXUP_PCI_IRQ 1
/*
* I2C
*/
#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
#define CONFIG_HARD_I2C /* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE 0x7F
#define CONFIG_SYS_I2C_OFFSET 0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
#define CONFIG_I2C_MULTI_BUS
/* I2C DS7505 temperature sensor */
#define CONFIG_DTT_LM75
#define CONFIG_DTT_SENSORS { 0 }
#define CONFIG_SYS_I2C_LM75_ADDR 0x48
/* I2C ADT7461 temperature sensor */
#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
/* I2C EEPROM - AT24C128B */
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
/* I2C RTC */
#define CONFIG_RTC_M41T11 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
#define CONFIG_SYS_M41T11_BASE_YEAR 2000
/* GPIO */
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
/*
* GPIO pin definitions, PU = pulled high, PD = pulled low
*/
/* PCA9557 @ 0x18*/
#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
/* PCA9557 @ 0x1e*/
#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
/* PCA9557 @ 0x1f */
#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
/*
* General PCI
* Memory space is mapped 1-1, but I/O space must start from 0.
*/
/* controller 1 - PEX8112 or XMC, depending on build option */
#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
/*
* Networking options
*/
#define CONFIG_TSEC_ENET /* tsec ethernet support */
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
#define CONFIG_NET_MULTI 1
#define CONFIG_TSEC_TBI
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_ETHPRIME "eTSEC2"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define CONFIG_HAS_ETH0
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_PHY_ADDR 2
#define TSEC2_PHYIDX 0
#define CONFIG_HAS_ETH1
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_PHY_ADDR 3
#define TSEC3_PHYIDX 0
#define CONFIG_HAS_ETH2
/*
* USB
*/
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_DOS_PARTITION
/*
* Command configuration.
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PCI_ENUM
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
#define CONFIG_PANIC_HANG /* do not reset board on panic */
#define CONFIG_PREBOOT /* enable preboot variable */
#define CONFIG_FIT 1
#define CONFIG_FIT_VERBOSE 1
#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
/*
* For booting Linux, the board info and command line data
* have to be in the first 16 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
/*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
/*
* Environment Configuration
*/
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
#define CONFIG_ENV_SIZE 0x8000
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
/*
* Flash memory map:
* fff80000 - ffffffff Pri U-Boot (512 KB)
* fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
* fff00000 - fff3ffff Pri FDT (256KB)
* fef00000 - ffefffff Pri OS image (16MB)
* f8000000 - feefffff Pri OS Use/Filesystem (111MB)
*
* f7f80000 - f7ffffff Sec U-Boot (512 KB)
* f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
* f7f00000 - f7f3ffff Sec FDT (256KB)
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
"if test $? -eq 0; then " \
"protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
"protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
"cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
"if test $? -ne 0; then " \
"echo PROGRAM FAILED; " \
"else; " \
"echo PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_UBOOT2 \
"$download_cmd $loadaddr $ubootfile; " \
"if test $? -eq 0; then " \
"protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
"protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
"cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
"if test $? -ne 0; then " \
"echo PROGRAM FAILED; " \
"else; " \
"echo PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_BOOT_OS_NET \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"if test -n $fdtaddr; then " \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"bootm $osaddr - $fdtaddr; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi; " \
"else; " \
"bootm $osaddr; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_OS1 \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
"cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
"cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo OS PROGRAM FAILED; " \
"else; " \
"echo OS PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_OS2 \
"$download_cmd $osaddr $osfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
"cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
"cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo OS PROGRAM FAILED; " \
"else; " \
"echo OS PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo OS DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_FDT1 \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
"cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
"cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo FDT PROGRAM FAILED; " \
"else; " \
"echo FDT PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_PROG_FDT2 \
"$download_cmd $fdtaddr $fdtfile; " \
"if test $? -eq 0; then " \
"erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
"cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
"cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
"if test $? -ne 0; then " \
"echo FDT PROGRAM FAILED; " \
"else; " \
"echo FDT PROGRAM SUCCEEDED; " \
"fi; " \
"else; " \
"echo FDT DOWNLOAD FAILED; " \
"fi;"
#define CONFIG_EXTRA_ENV_SETTINGS \
"autoload=yes\0" \
"download_cmd=tftp\0" \
"console_args=console=ttyS0,115200\0" \
"root_args=root=/dev/nfs rw\0" \
"misc_args=ip=on\0" \
"set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
"bootfile=/home/user/file\0" \
"osfile=/home/user/board.uImage\0" \
"fdtfile=/home/user/board.dtb\0" \
"ubootfile=/home/user/u-boot.bin\0" \
"fdtaddr=c00000\0" \
"osaddr=0x1000000\0" \
"loadaddr=0x1000000\0" \
"prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
"prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
"prog_os1="CONFIG_PROG_OS1"\0" \
"prog_os2="CONFIG_PROG_OS2"\0" \
"prog_fdt1="CONFIG_PROG_FDT1"\0" \
"prog_fdt2="CONFIG_PROG_FDT2"\0" \
"bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
"bootcmd_flash1=run set_bootargs; " \
"bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
"bootcmd_flash2=run set_bootargs; " \
"bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
"bootcmd=run bootcmd_flash1\0"
#endif /* __CONFIG_H */

4
include/post.h
View File

@ -60,6 +60,10 @@
#include <asm/immap_85xx.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr))
#elif defined (CONFIG_MPC86xx)
#include <asm/immap_86xx.h>
#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + offsetof(ccsr_pic_t, tfrr))
#elif defined (CONFIG_4xx)
#define _POST_WORD_ADDR \
(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

99
post/drivers/i2c.c
View File

@ -21,70 +21,89 @@
* MA 02111-1307 USA
*/
#include <common.h>
/*
* I2C test
*
* For verifying the I2C bus, a full I2C bus scanning is performed.
*
* #ifdef I2C_ADDR_LIST
* The test is considered as passed if all the devices and
* only the devices in the list are found.
* #else [ ! I2C_ADDR_LIST ]
* #ifdef CONFIG_SYS_POST_I2C_ADDRS
* The test is considered as passed if all the devices and only the devices
* in the list are found.
* #ifdef CONFIG_SYS_POST_I2C_IGNORES
* Ignore devices listed in CONFIG_SYS_POST_I2C_IGNORES. These devices
* are optional or not vital to board functionality.
* #endif
* #else [ ! CONFIG_SYS_POST_I2C_ADDRS ]
* The test is considered as passed if any I2C device is found.
* #endif
*/
#include <common.h>
#include <post.h>
#include <i2c.h>
#if CONFIG_POST & CONFIG_SYS_POST_I2C
static int i2c_ignore_device(unsigned int chip)
{
#ifdef CONFIG_SYS_POST_I2C_IGNORES
const unsigned char i2c_ignore_list[] = CONFIG_SYS_POST_I2C_IGNORES;
int i;
for (i = 0; i < sizeof(i2c_ignore_list); i++)
if (i2c_ignore_list[i] == chip)
return 1;
#endif
return 0;
}
int i2c_post_test (int flags)
{
unsigned int i;
unsigned int good = 0;
#ifdef I2C_ADDR_LIST
unsigned int bad = 0;
#ifndef CONFIG_SYS_POST_I2C_ADDRS
/* Start at address 1, address 0 is the general call address */
for (i = 1; i < 128; i++)
if (i2c_ignore_device(i))
continue;
if (i2c_probe (i) == 0)
return 0;
/* No devices found */
return -1;
#else
unsigned int ret = 0;
int j;
unsigned char i2c_addr_list[] = I2C_ADDR_LIST;
unsigned char i2c_miss_list[] = I2C_ADDR_LIST;
#endif
const unsigned char i2c_addr_list[] = CONFIG_SYS_POST_I2C_ADDRS;
for (i = 0; i < 128; i++) {
if (i2c_probe (i) == 0) {
#ifndef I2C_ADDR_LIST
good++;
#else /* I2C_ADDR_LIST */
for (j=0; j<sizeof(i2c_addr_list); ++j) {
if (i == i2c_addr_list[j]) {
good++;
i2c_miss_list[j] = 0xFF;
break;
}
/* Start at address 1, address 0 is the general call address */
for (i = 1; i < 128; i++) {
if (i2c_ignore_device(i))
continue;
if (i2c_probe(i) != 0)
continue;
for (j = 0; j < sizeof(i2c_addr_list); ++j) {
if (i == i2c_addr_list[j]) {
i2c_addr_list[j] = 0xff;
break;
}
if (j == sizeof(i2c_addr_list)) {
bad++;
post_log ("I2C: addr %02X not expected\n",
i);
}
#endif /* I2C_ADDR_LIST */
}
if (j == sizeof(i2c_addr_list)) {
ret = -1;
post_log("I2C: addr %02x not expected\n", i);
}
}
#ifndef I2C_ADDR_LIST
return good > 0 ? 0 : -1;
#else /* I2C_ADDR_LIST */
if (good != sizeof(i2c_addr_list)) {
for (j=0; j<sizeof(i2c_miss_list); ++j) {
if (i2c_miss_list[j] != 0xFF) {
post_log ("I2C: addr %02X did not respond\n",
i2c_miss_list[j]);
}
}
for (i = 0; i < sizeof(i2c_addr_list); ++i) {
if (i2c_addr_list[i] == 0xff)
continue;
post_log("I2C: addr %02x did not respond\n", i2c_addr_list[i]);
ret = -1;
}
return ((good == sizeof(i2c_addr_list)) && (bad == 0)) ? 0 : -1;
return ret;
#endif
}