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net: sh_eth: Add support SH7734 Ethernet device
SH7734 has one channel ethernet device. This support 10/100/1000Base, and RMII/MII/GMII. And this has the same structure as SH7763. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
This commit is contained in:
Nobuhiro Iwamatsu
Joe Hershberger
parent
4ef8d53caa
commit
ee6ec5d4dd
@ -59,7 +59,7 @@ int sh_eth_send(struct eth_device *dev, void *packet, int len)
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}
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/* packet must be a 4 byte boundary */
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if ((int)packet & (4 - 1)) {
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if ((int)packet & 3) {
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printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
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ret = -EFAULT;
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goto err;
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@ -138,7 +138,7 @@ int sh_eth_recv(struct eth_device *dev)
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static int sh_eth_reset(struct sh_eth_dev *eth)
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{
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int port = eth->port;
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#if defined(CONFIG_CPU_SH7763)
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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int ret = 0, i;
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/* Start e-dmac transmitter and receiver */
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@ -208,7 +208,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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/* Point the controller to the tx descriptor list. Must use physical
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addresses */
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outl(ADDR_TO_PHY(port_info->tx_desc_base), TDLAR(port));
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#if defined(CONFIG_CPU_SH7763)
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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outl(ADDR_TO_PHY(port_info->tx_desc_base), TDFAR(port));
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outl(ADDR_TO_PHY(cur_tx_desc), TDFXR(port));
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outl(0x01, TDFFR(port));/* Last discriptor bit */
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@ -276,7 +276,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
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/* Point the controller to the rx descriptor list */
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outl(ADDR_TO_PHY(port_info->rx_desc_base), RDLAR(port));
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#if defined(CONFIG_CPU_SH7763)
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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outl(ADDR_TO_PHY(port_info->rx_desc_base), RDFAR(port));
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outl(ADDR_TO_PHY(cur_rx_desc), RDFXR(port));
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outl(RDFFR_RDLF, RDFFR(port));
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@ -346,7 +346,8 @@ static int sh_eth_phy_config(struct sh_eth_dev *eth)
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struct eth_device *dev = port_info->dev;
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struct phy_device *phydev;
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phydev = phy_connect(miiphy_get_dev_by_name(dev->name),
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phydev = phy_connect(
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miiphy_get_dev_by_name(dev->name),
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port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII);
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port_info->phydev = phydev;
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phy_config(phydev);
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@ -398,7 +399,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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outl(APR_AP, APR(port));
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outl(MPR_MP, MPR(port));
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#endif
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#if defined(CONFIG_CPU_SH7763)
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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outl(TPAUSER_TPAUSE, TPAUSER(port));
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#elif defined(CONFIG_CPU_SH7757)
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outl(TPAUSER_UNLIMITED, TPAUSER(port));
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@ -418,7 +419,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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/* Set the transfer speed */
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if (phy->speed == 100) {
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printf(SHETHER_NAME ": 100Base/");
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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outl(GECMR_100B, GECMR(port));
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#elif defined(CONFIG_CPU_SH7757)
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outl(1, RTRATE(port));
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@ -427,7 +428,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd)
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#endif
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} else if (phy->speed == 10) {
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printf(SHETHER_NAME ": 10Base/");
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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outl(GECMR_10B, GECMR(port));
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#elif defined(CONFIG_CPU_SH7757)
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outl(0, RTRATE(port));
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@ -188,13 +188,51 @@ struct sh_eth_dev {
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#define TPAUSER(port) (BASE_IO_ADDR + 0x0164)
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#define MAHR(port) (BASE_IO_ADDR + 0x01c0)
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#define MALR(port) (BASE_IO_ADDR + 0x01c8)
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#elif defined(CONFIG_CPU_SH7734)
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#define BASE_IO_ADDR 0xFEE00000
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#define EDSR(port) (BASE_IO_ADDR)
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#define TDLAR(port) (BASE_IO_ADDR + 0x0010)
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#define TDFAR(port) (BASE_IO_ADDR + 0x0014)
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#define TDFXR(port) (BASE_IO_ADDR + 0x0018)
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#define TDFFR(port) (BASE_IO_ADDR + 0x001c)
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#define RDLAR(port) (BASE_IO_ADDR + 0x0030)
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#define RDFAR(port) (BASE_IO_ADDR + 0x0034)
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#define RDFXR(port) (BASE_IO_ADDR + 0x0038)
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#define RDFFR(port) (BASE_IO_ADDR + 0x003c)
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#define EDMR(port) (BASE_IO_ADDR + 0x0400)
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#define EDTRR(port) (BASE_IO_ADDR + 0x0408)
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#define EDRRR(port) (BASE_IO_ADDR + 0x0410)
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#define EESR(port) (BASE_IO_ADDR + 0x0428)
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#define EESIPR(port) (BASE_IO_ADDR + 0x0430)
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#define TRSCER(port) (BASE_IO_ADDR + 0x0438)
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#define TFTR(port) (BASE_IO_ADDR + 0x0448)
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#define FDR(port) (BASE_IO_ADDR + 0x0450)
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#define RMCR(port) (BASE_IO_ADDR + 0x0458)
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#define RPADIR(port) (BASE_IO_ADDR + 0x0460)
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#define FCFTR(port) (BASE_IO_ADDR + 0x0468)
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#define ECMR(port) (BASE_IO_ADDR + 0x0500)
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#define RFLR(port) (BASE_IO_ADDR + 0x0508)
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#define ECSIPR(port) (BASE_IO_ADDR + 0x0518)
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#define PIR(port) (BASE_IO_ADDR + 0x0520)
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#define PIPR(port) (BASE_IO_ADDR + 0x052c)
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#define APR(port) (BASE_IO_ADDR + 0x0554)
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#define MPR(port) (BASE_IO_ADDR + 0x0558)
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#define TPAUSER(port) (BASE_IO_ADDR + 0x0564)
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#define GECMR(port) (BASE_IO_ADDR + 0x05b0)
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#define MAHR(port) (BASE_IO_ADDR + 0x05C0)
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#define MALR(port) (BASE_IO_ADDR + 0x05C8)
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#endif
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/*
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* Register's bits
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* Copy from Linux driver source code
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*/
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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/* EDSR */
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enum EDSR_BIT {
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EDSR_ENT = 0x01, EDSR_ENR = 0x02,
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@ -205,11 +243,11 @@ enum EDSR_BIT {
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/* EDMR */
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enum DMAC_M_BIT {
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EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
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#ifdef CONFIG_CPU_SH7763
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EDMR_SRST = 0x03,
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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EDMR_SRST = 0x03, /* Receive/Send reset */
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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#elif defined(CONFIG_CPU_SH7757) ||defined (CONFIG_CPU_SH7724)
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#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7724)
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EDMR_SRST = 0x01,
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EMDR_DESC_R = 0x30, /* Descriptor reserve size */
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EDMR_EL = 0x40, /* Litte endian */
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@ -223,7 +261,7 @@ enum DMAC_M_BIT {
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/* EDTRR */
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enum DMAC_T_BIT {
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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EDTRR_TRNS = 0x03,
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#else
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EDTRR_TRNS = 0x01,
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@ -262,7 +300,8 @@ enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
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/* EESR */
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enum EESR_BIT {
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#ifndef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
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EESR_TWB = 0x40000000,
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#else
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EESR_TWB = 0xC0000000,
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@ -272,14 +311,14 @@ enum EESR_BIT {
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#endif
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EESR_TABT = 0x04000000,
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EESR_RABT = 0x02000000, EESR_RFRMER = 0x01000000,
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#ifndef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
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EESR_ADE = 0x00800000,
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#endif
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EESR_ECI = 0x00400000,
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EESR_FTC = 0x00200000, EESR_TDE = 0x00100000,
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EESR_TFE = 0x00080000, EESR_FRC = 0x00040000,
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EESR_RDE = 0x00020000, EESR_RFE = 0x00010000,
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#ifndef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7724) && !defined(CONFIG_CPU_SH7757)
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EESR_CND = 0x00000800,
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#endif
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EESR_DLC = 0x00000400,
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@ -291,7 +330,7 @@ enum EESR_BIT {
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};
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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# define TX_CHECK (EESR_TC1 | EESR_FTC)
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# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
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| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
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@ -352,7 +391,7 @@ enum FCFTR_BIT {
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/* Transfer descriptor bit */
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enum TD_STS_BIT {
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7757) \
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|| defined(CONFIG_CPU_SH7724)
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|| defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7734)
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TD_TACT = 0x80000000,
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#else
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TD_TACT = 0x7fffffff,
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@ -368,7 +407,7 @@ enum TD_STS_BIT {
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enum RECV_RST_BIT { RMCR_RST = 0x01, };
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/* ECMR */
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enum FELIC_MODE_BIT {
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
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ECMR_RZPF = 0x00100000,
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#endif
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@ -383,7 +422,7 @@ enum FELIC_MODE_BIT {
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};
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
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ECMR_TXF | ECMR_MCT)
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#elif CONFIG_CPU_SH7757
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@ -396,14 +435,14 @@ enum FELIC_MODE_BIT {
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/* ECSR */
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enum ECSR_STATUS_BIT {
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#ifndef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7724) || defined(CONFIG_CPU_SH7757)
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ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
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#endif
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ECSR_LCHNG = 0x04,
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ECSR_MPD = 0x02, ECSR_ICD = 0x01,
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};
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
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#else
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# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
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@ -412,14 +451,20 @@ enum ECSR_STATUS_BIT {
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/* ECSIPR */
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enum ECSIPR_STATUS_MASK_BIT {
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#ifndef CONFIG_CPU_SH7763
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ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
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#endif
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#if defined(CONFIG_CPU_SH7724)
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ECSIPR_PSRTOIP = 0x10,
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ECSIPR_LCHNGIP = 0x04,
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ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
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ECSIPR_ICDIP = 0x01,
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#elif defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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ECSIPR_PSRTOIP = 0x10,
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ECSIPR_PHYIP = 0x08,
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ECSIPR_LCHNGIP = 0x04,
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ECSIPR_MPDIP = 0x02,
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ECSIPR_ICDIP = 0x01,
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#endif
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};
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
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#else
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# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
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@ -458,7 +503,7 @@ enum RPADIR_BIT {
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RPADIR_PADR = 0x0003f,
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};
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#ifdef CONFIG_CPU_SH7763
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#if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
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# define RPADIR_INIT (0x00)
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#else
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# define RPADIR_INIT (RPADIR_PADS1)
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