mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-24 12:44:23 +08:00
net: Divided code of NE2000 ethernet driver
There are more devices of the NE2000 base. A present code is difficult for us to support more devices. To support more NE2000 clone devices, separated the function. Signed-off-by: Yusuke Goda <goda.yusuke@renesas.com> Acked-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
goda.yusuke
Wolfgang Denk
parent
395bce4f59
commit
e710185aae
@ -82,25 +82,11 @@ Add SNMP
|
||||
|
||||
#ifdef CONFIG_DRIVER_NE2000
|
||||
|
||||
/* wor around udelay resetting OCR */
|
||||
static void my_udelay(long us) {
|
||||
long tmo;
|
||||
|
||||
tmo = get_timer (0) + us * CFG_HZ / 1000000; /* will this be much greater than 0 ? */
|
||||
while (get_timer (0) < tmo);
|
||||
}
|
||||
|
||||
#define mdelay(n) my_udelay((n)*1000)
|
||||
|
||||
#define mdelay(n) udelay((n)*1000)
|
||||
/* forward definition of function used for the uboot interface */
|
||||
void uboot_push_packet_len(int len);
|
||||
void uboot_push_tx_done(int key, int val);
|
||||
|
||||
/* timeout for tx/rx in s */
|
||||
#define TOUT 5
|
||||
|
||||
#define ETHER_ADDR_LEN 6
|
||||
|
||||
/*
|
||||
------------------------------------------------------------------------
|
||||
Debugging details
|
||||
@ -118,27 +104,26 @@ void uboot_push_tx_done(int key, int val);
|
||||
#if DEBUG & 1
|
||||
#define DEBUG_FUNCTION() do { printf("%s\n", __FUNCTION__); } while (0)
|
||||
#define DEBUG_LINE() do { printf("%d\n", __LINE__); } while (0)
|
||||
#define PRINTK(args...) printf(args)
|
||||
#else
|
||||
#define DEBUG_FUNCTION() do {} while(0)
|
||||
#define DEBUG_LINE() do {} while(0)
|
||||
#endif
|
||||
|
||||
#include "ne2000.h"
|
||||
|
||||
#if DEBUG & 1
|
||||
#define PRINTK(args...) printf(args)
|
||||
#else
|
||||
#define PRINTK(args...)
|
||||
#endif
|
||||
|
||||
/* NE2000 base header file */
|
||||
#include "ne2000_base.h"
|
||||
|
||||
/* Basic NE2000 chip support */
|
||||
#include "ne2000.h"
|
||||
|
||||
static dp83902a_priv_data_t nic; /* just one instance of the card supported */
|
||||
|
||||
static bool
|
||||
dp83902a_init(void)
|
||||
{
|
||||
dp83902a_priv_data_t *dp = &nic;
|
||||
cyg_uint8* base;
|
||||
int i;
|
||||
u8* base;
|
||||
|
||||
DEBUG_FUNCTION();
|
||||
|
||||
@ -147,6 +132,7 @@ dp83902a_init(void)
|
||||
|
||||
DEBUG_LINE();
|
||||
|
||||
#if defined(NE2000_BASIC_INIT)
|
||||
/* Prepare ESA */
|
||||
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */
|
||||
/* Use the address from the serial EEPROM */
|
||||
@ -163,6 +149,7 @@ dp83902a_init(void)
|
||||
dp->esa[4],
|
||||
dp->esa[5] );
|
||||
|
||||
#endif /* NE2000_BASIC_INIT */
|
||||
return true;
|
||||
}
|
||||
|
||||
@ -170,7 +157,7 @@ static void
|
||||
dp83902a_stop(void)
|
||||
{
|
||||
dp83902a_priv_data_t *dp = &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
u8 *base = dp->base;
|
||||
|
||||
DEBUG_FUNCTION();
|
||||
|
||||
@ -188,10 +175,10 @@ dp83902a_stop(void)
|
||||
the hardware ready to send/receive packets.
|
||||
*/
|
||||
static void
|
||||
dp83902a_start(unsigned char * enaddr)
|
||||
dp83902a_start(u8 * enaddr)
|
||||
{
|
||||
dp83902a_priv_data_t *dp = &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
u8 *base = dp->base;
|
||||
int i;
|
||||
|
||||
DEBUG_FUNCTION();
|
||||
@ -206,15 +193,20 @@ dp83902a_start(unsigned char * enaddr)
|
||||
dp->tx1 = dp->tx2 = 0;
|
||||
dp->tx_next = dp->tx_buf1;
|
||||
dp->tx_started = false;
|
||||
dp->running = true;
|
||||
DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */
|
||||
DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1); /* Receive ring boundary */
|
||||
DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */
|
||||
dp->rx_next = dp->rx_buf_start-1;
|
||||
dp->running = true;
|
||||
DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */
|
||||
DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */
|
||||
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */
|
||||
DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */
|
||||
dp->running = true;
|
||||
for (i = 0; i < ETHER_ADDR_LEN; i++) {
|
||||
/* FIXME */
|
||||
//*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + 0x1400)) = enaddr[i];
|
||||
DP_OUT(base, DP_P1_PAR0+i, enaddr[i]);
|
||||
}
|
||||
/* Enable and start device */
|
||||
@ -222,6 +214,7 @@ dp83902a_start(unsigned char * enaddr)
|
||||
DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */
|
||||
DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */
|
||||
dp->running = true;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
@ -234,7 +227,7 @@ static void
|
||||
dp83902a_start_xmit(int start_page, int len)
|
||||
{
|
||||
dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
u8 *base = dp->base;
|
||||
|
||||
DEBUG_FUNCTION();
|
||||
|
||||
@ -259,10 +252,10 @@ dp83902a_start_xmit(int start_page, int len)
|
||||
that there is free buffer space (dp->tx_next).
|
||||
*/
|
||||
static void
|
||||
dp83902a_send(unsigned char *data, int total_len, unsigned long key)
|
||||
dp83902a_send(u8 *data, int total_len, u32 key)
|
||||
{
|
||||
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
u8 *base = dp->base;
|
||||
int len, start_page, pkt_len, i, isr;
|
||||
#if DEBUG & 4
|
||||
int dx;
|
||||
@ -296,7 +289,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key)
|
||||
/* but the code is extended a bit to do what Hitachi's monitor */
|
||||
/* does (i.e., also read data). */
|
||||
|
||||
cyg_uint16 tmp;
|
||||
u16 tmp;
|
||||
int len = 1;
|
||||
|
||||
DP_OUT(base, DP_RSAL, 0x100-len);
|
||||
@ -322,7 +315,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key)
|
||||
|
||||
/* Put data into buffer */
|
||||
#if DEBUG & 4
|
||||
printf(" sg buf %08lx len %08x\n ", (unsigned long) data, len);
|
||||
printf(" sg buf %08lx len %08x\n ", (u32)data, len);
|
||||
dx = 0;
|
||||
#endif
|
||||
while (len > 0) {
|
||||
@ -330,6 +323,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key)
|
||||
printf(" %02x", *data);
|
||||
if (0 == (++dx % 16)) printf("\n ");
|
||||
#endif
|
||||
|
||||
DP_OUT_DATA(dp->data, *data++);
|
||||
len--;
|
||||
}
|
||||
@ -358,6 +352,7 @@ dp83902a_send(unsigned char *data, int total_len, unsigned long key)
|
||||
do {
|
||||
DP_IN(base, DP_ISR, isr);
|
||||
} while ((isr & DP_ISR_RDC) == 0);
|
||||
|
||||
/* Then disable DMA */
|
||||
DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START);
|
||||
|
||||
@ -383,9 +378,9 @@ static void
|
||||
dp83902a_RxEvent(void)
|
||||
{
|
||||
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
unsigned char rsr;
|
||||
unsigned char rcv_hdr[4];
|
||||
u8 *base = dp->base;
|
||||
u8 rsr;
|
||||
u8 rcv_hdr[4];
|
||||
int i, len, pkt, cur;
|
||||
|
||||
DEBUG_FUNCTION();
|
||||
@ -423,6 +418,7 @@ dp83902a_RxEvent(void)
|
||||
CYGACC_CALL_IF_DELAY_US(10);
|
||||
#endif
|
||||
|
||||
/* read header (get data size)*/
|
||||
for (i = 0; i < sizeof(rcv_hdr);) {
|
||||
DP_IN_DATA(dp->data, rcv_hdr[i++]);
|
||||
}
|
||||
@ -432,7 +428,10 @@ dp83902a_RxEvent(void)
|
||||
rcv_hdr[0], rcv_hdr[1], rcv_hdr[2], rcv_hdr[3]);
|
||||
#endif
|
||||
len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr);
|
||||
|
||||
/* data read */
|
||||
uboot_push_packet_len(len);
|
||||
|
||||
if (rcv_hdr[1] == dp->rx_buf_start)
|
||||
DP_OUT(base, DP_BNDRY, dp->rx_buf_end-1);
|
||||
else
|
||||
@ -448,12 +447,12 @@ dp83902a_RxEvent(void)
|
||||
efficient processing in the upper layers of the stack.
|
||||
*/
|
||||
static void
|
||||
dp83902a_recv(unsigned char *data, int len)
|
||||
dp83902a_recv(u8 *data, int len)
|
||||
{
|
||||
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
u8 *base = dp->base;
|
||||
int i, mlen;
|
||||
cyg_uint8 saved_char = 0;
|
||||
u8 saved_char = 0;
|
||||
bool saved;
|
||||
#if DEBUG & 4
|
||||
int dx;
|
||||
@ -482,7 +481,7 @@ dp83902a_recv(unsigned char *data, int len)
|
||||
if (data) {
|
||||
mlen = len;
|
||||
#if DEBUG & 4
|
||||
printf(" sg buf %08lx len %08x \n", (unsigned long) data, mlen);
|
||||
printf(" sg buf %08lx len %08x \n", (u32) data, mlen);
|
||||
dx = 0;
|
||||
#endif
|
||||
while (0 < mlen) {
|
||||
@ -495,7 +494,7 @@ dp83902a_recv(unsigned char *data, int len)
|
||||
}
|
||||
|
||||
{
|
||||
cyg_uint8 tmp;
|
||||
u8 tmp;
|
||||
DP_IN_DATA(dp->data, tmp);
|
||||
#if DEBUG & 4
|
||||
printf(" %02x", tmp);
|
||||
@ -516,9 +515,9 @@ static void
|
||||
dp83902a_TxEvent(void)
|
||||
{
|
||||
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
unsigned char tsr;
|
||||
unsigned long key;
|
||||
u8 *base = dp->base;
|
||||
u8 tsr;
|
||||
u32 key;
|
||||
|
||||
DEBUG_FUNCTION();
|
||||
|
||||
@ -551,8 +550,8 @@ static void
|
||||
dp83902a_ClearCounters(void)
|
||||
{
|
||||
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
cyg_uint8 cnt1, cnt2, cnt3;
|
||||
u8 *base = dp->base;
|
||||
u8 cnt1, cnt2, cnt3;
|
||||
|
||||
DP_IN(base, DP_FER, cnt1);
|
||||
DP_IN(base, DP_CER, cnt2);
|
||||
@ -566,8 +565,8 @@ static void
|
||||
dp83902a_Overflow(void)
|
||||
{
|
||||
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
cyg_uint8 isr;
|
||||
u8 *base = dp->base;
|
||||
u8 isr;
|
||||
|
||||
/* Issue a stop command and wait 1.6ms for it to complete. */
|
||||
DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA);
|
||||
@ -603,8 +602,8 @@ static void
|
||||
dp83902a_poll(void)
|
||||
{
|
||||
struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic;
|
||||
cyg_uint8 *base = dp->base;
|
||||
unsigned char isr;
|
||||
u8 *base = dp->base;
|
||||
u8 isr;
|
||||
|
||||
DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START);
|
||||
DP_IN(base, DP_ISR, isr);
|
||||
@ -642,13 +641,13 @@ dp83902a_poll(void)
|
||||
/* find prom (taken from pc_net_cs.c from Linux) */
|
||||
|
||||
#include "8390.h"
|
||||
|
||||
/*
|
||||
typedef struct hw_info_t {
|
||||
u_int offset;
|
||||
u_char a0, a1, a2;
|
||||
u_int flags;
|
||||
} hw_info_t;
|
||||
|
||||
*/
|
||||
#define DELAY_OUTPUT 0x01
|
||||
#define HAS_MISC_REG 0x02
|
||||
#define USE_BIG_BUF 0x04
|
||||
@ -731,102 +730,17 @@ static hw_info_t hw_info[] = {
|
||||
|
||||
static hw_info_t default_info = { 0, 0, 0, 0, 0 };
|
||||
|
||||
unsigned char dev_addr[6];
|
||||
u8 dev_addr[6];
|
||||
|
||||
#define PCNET_CMD 0x00
|
||||
#define PCNET_DATAPORT 0x10 /* NatSemi-defined port window offset. */
|
||||
#define PCNET_RESET 0x1f /* Issue a read to reset, a write to clear. */
|
||||
#define PCNET_MISC 0x18 /* For IBM CCAE and Socket EA cards */
|
||||
|
||||
unsigned long nic_base;
|
||||
|
||||
static void pcnet_reset_8390(void)
|
||||
{
|
||||
int i, r;
|
||||
|
||||
PRINTK("nic base is %lx\n", nic_base);
|
||||
|
||||
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
|
||||
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
|
||||
n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
|
||||
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
|
||||
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
|
||||
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
|
||||
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
|
||||
|
||||
n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
|
||||
break;
|
||||
PRINTK("got %x in reset\n", r);
|
||||
my_udelay(100);
|
||||
}
|
||||
n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
|
||||
|
||||
if (i == 100)
|
||||
printf("pcnet_reset_8390() did not complete.\n");
|
||||
} /* pcnet_reset_8390 */
|
||||
|
||||
static hw_info_t * get_prom(void ) {
|
||||
unsigned char prom[32];
|
||||
int i, j;
|
||||
struct {
|
||||
u_char value, offset;
|
||||
} program_seq[] = {
|
||||
{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
|
||||
{0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
|
||||
{0x00, EN0_RCNTLO}, /* Clear the count regs. */
|
||||
{0x00, EN0_RCNTHI},
|
||||
{0x00, EN0_IMR}, /* Mask completion irq. */
|
||||
{0xFF, EN0_ISR},
|
||||
{E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */
|
||||
{E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */
|
||||
{32, EN0_RCNTLO},
|
||||
{0x00, EN0_RCNTHI},
|
||||
{0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */
|
||||
{0x00, EN0_RSARHI},
|
||||
{E8390_RREAD+E8390_START, E8390_CMD},
|
||||
};
|
||||
|
||||
PRINTK("trying to get MAC via prom reading\n");
|
||||
|
||||
pcnet_reset_8390();
|
||||
|
||||
mdelay(10);
|
||||
|
||||
for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++)
|
||||
n2k_outb(program_seq[i].value, program_seq[i].offset);
|
||||
|
||||
PRINTK("PROM:");
|
||||
for (i = 0; i < 32; i++) {
|
||||
prom[i] = n2k_inb(PCNET_DATAPORT);
|
||||
PRINTK(" %02x", prom[i]);
|
||||
}
|
||||
PRINTK("\n");
|
||||
for (i = 0; i < NR_INFO; i++) {
|
||||
if ((prom[0] == hw_info[i].a0) &&
|
||||
(prom[2] == hw_info[i].a1) &&
|
||||
(prom[4] == hw_info[i].a2)) {
|
||||
PRINTK("matched board %d\n", i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
|
||||
for (j = 0; j < 6; j++)
|
||||
dev_addr[j] = prom[j<<1];
|
||||
PRINTK("on exit i is %d/%ld\n", i, NR_INFO);
|
||||
PRINTK("MAC address is %02x:%02x:%02x:%02x:%02x:%02x\n",
|
||||
dev_addr[0],dev_addr[1],dev_addr[2],dev_addr[3],dev_addr[4],dev_addr[5]);
|
||||
return (i < NR_INFO) ? hw_info+i : &default_info;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
u32 nic_base;
|
||||
|
||||
/* U-boot specific routines */
|
||||
|
||||
|
||||
static unsigned char *pbuf = NULL;
|
||||
static u8 *pbuf = NULL;
|
||||
|
||||
static int pkey = -1;
|
||||
static int initialized=0;
|
||||
@ -839,7 +753,7 @@ void uboot_push_packet_len(int len) {
|
||||
}
|
||||
dp83902a_recv(&pbuf[0], len);
|
||||
|
||||
/* Just pass it to the upper layer */
|
||||
/*Just pass it to the upper layer*/
|
||||
NetReceive(&pbuf[0], len);
|
||||
}
|
||||
|
||||
@ -864,7 +778,7 @@ int eth_init(bd_t *bd) {
|
||||
|
||||
#ifdef CONFIG_DRIVER_NE2000_CCR
|
||||
{
|
||||
volatile unsigned char *p = (volatile unsigned char *) CONFIG_DRIVER_NE2000_CCR;
|
||||
vu_char *p = (vu_char *) CONFIG_DRIVER_NE2000_CCR;
|
||||
|
||||
PRINTK("CCR before is %x\n", *p);
|
||||
*p = CONFIG_DRIVER_NE2000_VAL;
|
||||
@ -873,9 +787,9 @@ int eth_init(bd_t *bd) {
|
||||
#endif
|
||||
|
||||
nic_base = CONFIG_DRIVER_NE2000_BASE;
|
||||
nic.base = (cyg_uint8 *) CONFIG_DRIVER_NE2000_BASE;
|
||||
nic.base = (u8 *) CONFIG_DRIVER_NE2000_BASE;
|
||||
|
||||
r = get_prom();
|
||||
r = get_prom(dev_addr);
|
||||
if (!r)
|
||||
return -1;
|
||||
|
||||
@ -886,22 +800,23 @@ int eth_init(bd_t *bd) {
|
||||
PRINTK("Set environment from HW MAC addr = \"%s\"\n", ethaddr);
|
||||
setenv ("ethaddr", ethaddr);
|
||||
|
||||
|
||||
#define DP_DATA 0x10
|
||||
nic.data = nic.base + DP_DATA;
|
||||
nic.tx_buf1 = 0x40;
|
||||
nic.tx_buf2 = 0x48;
|
||||
nic.rx_buf_start = 0x50;
|
||||
nic.rx_buf_end = 0x80;
|
||||
nic.tx_buf1 = START_PG;
|
||||
nic.tx_buf2 = START_PG2;
|
||||
nic.rx_buf_start = RX_START;
|
||||
nic.rx_buf_end = RX_END;
|
||||
|
||||
if (dp83902a_init() == false)
|
||||
return -1;
|
||||
|
||||
dp83902a_start(dev_addr);
|
||||
initialized=1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void eth_halt() {
|
||||
|
||||
PRINTK("### eth_halt\n");
|
||||
if(initialized)
|
||||
dp83902a_stop();
|
||||
@ -920,7 +835,7 @@ int eth_send(volatile void *packet, int length) {
|
||||
|
||||
pkey = -1;
|
||||
|
||||
dp83902a_send((unsigned char *) packet, length, 666);
|
||||
dp83902a_send((u8 *) packet, length, 666);
|
||||
tmo = get_timer (0) + TOUT * CFG_HZ;
|
||||
while(1) {
|
||||
dp83902a_poll();
|
||||
|
||||
@ -71,209 +71,113 @@ are GPL, so this is, of course, GPL.
|
||||
*/
|
||||
|
||||
/*
|
||||
------------------------------------------------------------------------
|
||||
Macros for accessing DP registers
|
||||
These can be overridden by the platform header
|
||||
*/
|
||||
* NE2000 support header file.
|
||||
* Created by Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
|
||||
*/
|
||||
|
||||
#define DP_IN(_b_, _o_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)+(_o_)))
|
||||
#define DP_OUT(_b_, _o_, _d_) *( (volatile unsigned char *) ((_b_)+(_o_))) = (_d_)
|
||||
#ifndef __DRIVERS_NE2000_H__
|
||||
#define __DRIVERS_NE2000_H__
|
||||
|
||||
#define DP_IN_DATA(_b_, _d_) (_d_) = *( (volatile unsigned char *) ((_b_)))
|
||||
#define DP_OUT_DATA(_b_, _d_) *( (volatile unsigned char *) ((_b_))) = (_d_)
|
||||
/* Enable NE2000 basic init function */
|
||||
#define NE2000_BASIC_INIT
|
||||
|
||||
#define DP_DATA 0x10
|
||||
#define START_PG 0x50 /* First page of TX buffer */
|
||||
#define STOP_PG 0x80 /* Last page +1 of RX ring */
|
||||
|
||||
#define RX_START 0x50
|
||||
#define RX_END 0x80
|
||||
|
||||
#define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_char *) ((_b_)+(_o_)))
|
||||
#define DP_OUT(_b_, _o_, _d_) *( (vu_char *) ((_b_)+(_o_))) = (_d_)
|
||||
#define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_char *) ((_b_)))
|
||||
#define DP_OUT_DATA(_b_, _d_) *( (vu_char *) ((_b_))) = (_d_)
|
||||
|
||||
static void pcnet_reset_8390(void)
|
||||
{
|
||||
int i, r;
|
||||
|
||||
PRINTK("nic base is %lx\n", nic_base);
|
||||
|
||||
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
|
||||
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
|
||||
n2k_outb(E8390_NODMA+E8390_PAGE1+E8390_STOP, E8390_CMD);
|
||||
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
|
||||
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
|
||||
PRINTK("cmd (at %lx) is %x\n", nic_base+ E8390_CMD, n2k_inb(E8390_CMD));
|
||||
n2k_outb(E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD);
|
||||
|
||||
n2k_outb(n2k_inb(PCNET_RESET), PCNET_RESET);
|
||||
|
||||
for (i = 0; i < 100; i++) {
|
||||
if ((r = (n2k_inb(EN0_ISR) & ENISR_RESET)) != 0)
|
||||
break;
|
||||
PRINTK("got %x in reset\n", r);
|
||||
udelay(100);
|
||||
}
|
||||
n2k_outb(ENISR_RESET, EN0_ISR); /* Ack intr. */
|
||||
|
||||
if (i == 100)
|
||||
printf("pcnet_reset_8390() did not complete.\n");
|
||||
} /* pcnet_reset_8390 */
|
||||
|
||||
int get_prom(u8* mac_addr)
|
||||
{
|
||||
u8 prom[32];
|
||||
int i, j;
|
||||
struct {
|
||||
u_char value, offset;
|
||||
} program_seq[] = {
|
||||
{E8390_NODMA+E8390_PAGE0+E8390_STOP, E8390_CMD}, /* Select page 0*/
|
||||
{0x48, EN0_DCFG}, /* Set byte-wide (0x48) access. */
|
||||
{0x00, EN0_RCNTLO}, /* Clear the count regs. */
|
||||
{0x00, EN0_RCNTHI},
|
||||
{0x00, EN0_IMR}, /* Mask completion irq. */
|
||||
{0xFF, EN0_ISR},
|
||||
{E8390_RXOFF, EN0_RXCR}, /* 0x20 Set to monitor */
|
||||
{E8390_TXOFF, EN0_TXCR}, /* 0x02 and loopback mode. */
|
||||
{32, EN0_RCNTLO},
|
||||
{0x00, EN0_RCNTHI},
|
||||
{0x00, EN0_RSARLO}, /* DMA starting at 0x0000. */
|
||||
{0x00, EN0_RSARHI},
|
||||
{E8390_RREAD+E8390_START, E8390_CMD},
|
||||
};
|
||||
|
||||
PRINTK("trying to get MAC via prom reading\n");
|
||||
|
||||
pcnet_reset_8390();
|
||||
|
||||
mdelay(10);
|
||||
|
||||
for (i = 0; i < sizeof(program_seq)/sizeof(program_seq[0]); i++)
|
||||
n2k_outb(program_seq[i].value, program_seq[i].offset);
|
||||
|
||||
PRINTK("PROM:");
|
||||
for (i = 0; i < 32; i++) {
|
||||
prom[i] = n2k_inb(PCNET_DATAPORT);
|
||||
PRINTK(" %02x", prom[i]);
|
||||
}
|
||||
PRINTK("\n");
|
||||
for (i = 0; i < NR_INFO; i++) {
|
||||
if ((prom[0] == hw_info[i].a0) &&
|
||||
(prom[2] == hw_info[i].a1) &&
|
||||
(prom[4] == hw_info[i].a2)) {
|
||||
PRINTK("matched board %d\n", i);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if ((i < NR_INFO) || ((prom[28] == 0x57) && (prom[30] == 0x57))) {
|
||||
PRINTK("on exit i is %d/%ld\n", i, NR_INFO);
|
||||
PRINTK("MAC address is ");
|
||||
for (j = 0; j < 6; j++){
|
||||
mac_addr[j] = prom[j<<1];
|
||||
PRINTK("%02x:",mac_addr[i]);
|
||||
}
|
||||
PRINTK("\n");
|
||||
return (i < NR_INFO) ? i : 0;
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
/* here is all the data */
|
||||
|
||||
#define cyg_uint8 unsigned char
|
||||
#define cyg_uint16 unsigned short
|
||||
#define bool int
|
||||
|
||||
#define false 0
|
||||
#define true 1
|
||||
|
||||
#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
|
||||
#define CYGACC_CALL_IF_DELAY_US(X) my_udelay(X)
|
||||
|
||||
typedef struct dp83902a_priv_data {
|
||||
cyg_uint8* base;
|
||||
cyg_uint8* data;
|
||||
cyg_uint8* reset;
|
||||
int tx_next; /* First free Tx page */
|
||||
int tx_int; /* Expecting interrupt from this buffer */
|
||||
int rx_next; /* First free Rx page */
|
||||
int tx1, tx2; /* Page numbers for Tx buffers */
|
||||
unsigned long tx1_key, tx2_key; /* Used to ack when packet sent */
|
||||
int tx1_len, tx2_len;
|
||||
bool tx_started, running, hardwired_esa;
|
||||
cyg_uint8 esa[6];
|
||||
void* plf_priv;
|
||||
|
||||
/* Buffer allocation */
|
||||
int tx_buf1, tx_buf2;
|
||||
int rx_buf_start, rx_buf_end;
|
||||
} dp83902a_priv_data_t;
|
||||
|
||||
/*
|
||||
------------------------------------------------------------------------
|
||||
Some forward declarations
|
||||
*/
|
||||
static void dp83902a_poll(void);
|
||||
|
||||
/* ------------------------------------------------------------------------ */
|
||||
/* Register offsets */
|
||||
|
||||
#define DP_CR 0x00
|
||||
#define DP_CLDA0 0x01
|
||||
#define DP_PSTART 0x01 /* write */
|
||||
#define DP_CLDA1 0x02
|
||||
#define DP_PSTOP 0x02 /* write */
|
||||
#define DP_BNDRY 0x03
|
||||
#define DP_TSR 0x04
|
||||
#define DP_TPSR 0x04 /* write */
|
||||
#define DP_NCR 0x05
|
||||
#define DP_TBCL 0x05 /* write */
|
||||
#define DP_FIFO 0x06
|
||||
#define DP_TBCH 0x06 /* write */
|
||||
#define DP_ISR 0x07
|
||||
#define DP_CRDA0 0x08
|
||||
#define DP_RSAL 0x08 /* write */
|
||||
#define DP_CRDA1 0x09
|
||||
#define DP_RSAH 0x09 /* write */
|
||||
#define DP_RBCL 0x0a /* write */
|
||||
#define DP_RBCH 0x0b /* write */
|
||||
#define DP_RSR 0x0c
|
||||
#define DP_RCR 0x0c /* write */
|
||||
#define DP_FER 0x0d
|
||||
#define DP_TCR 0x0d /* write */
|
||||
#define DP_CER 0x0e
|
||||
#define DP_DCR 0x0e /* write */
|
||||
#define DP_MISSED 0x0f
|
||||
#define DP_IMR 0x0f /* write */
|
||||
#define DP_DATAPORT 0x10 /* "eprom" data port */
|
||||
|
||||
#define DP_P1_CR 0x00
|
||||
#define DP_P1_PAR0 0x01
|
||||
#define DP_P1_PAR1 0x02
|
||||
#define DP_P1_PAR2 0x03
|
||||
#define DP_P1_PAR3 0x04
|
||||
#define DP_P1_PAR4 0x05
|
||||
#define DP_P1_PAR5 0x06
|
||||
#define DP_P1_CURP 0x07
|
||||
#define DP_P1_MAR0 0x08
|
||||
#define DP_P1_MAR1 0x09
|
||||
#define DP_P1_MAR2 0x0a
|
||||
#define DP_P1_MAR3 0x0b
|
||||
#define DP_P1_MAR4 0x0c
|
||||
#define DP_P1_MAR5 0x0d
|
||||
#define DP_P1_MAR6 0x0e
|
||||
#define DP_P1_MAR7 0x0f
|
||||
|
||||
#define DP_P2_CR 0x00
|
||||
#define DP_P2_PSTART 0x01
|
||||
#define DP_P2_CLDA0 0x01 /* write */
|
||||
#define DP_P2_PSTOP 0x02
|
||||
#define DP_P2_CLDA1 0x02 /* write */
|
||||
#define DP_P2_RNPP 0x03
|
||||
#define DP_P2_TPSR 0x04
|
||||
#define DP_P2_LNPP 0x05
|
||||
#define DP_P2_ACH 0x06
|
||||
#define DP_P2_ACL 0x07
|
||||
#define DP_P2_RCR 0x0c
|
||||
#define DP_P2_TCR 0x0d
|
||||
#define DP_P2_DCR 0x0e
|
||||
#define DP_P2_IMR 0x0f
|
||||
|
||||
/* Command register - common to all pages */
|
||||
|
||||
#define DP_CR_STOP 0x01 /* Stop: software reset */
|
||||
#define DP_CR_START 0x02 /* Start: initialize device */
|
||||
#define DP_CR_TXPKT 0x04 /* Transmit packet */
|
||||
#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
|
||||
#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
|
||||
#define DP_CR_SEND 0x18 /* Send packet */
|
||||
#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
|
||||
#define DP_CR_PAGE0 0x00 /* Page select */
|
||||
#define DP_CR_PAGE1 0x40
|
||||
#define DP_CR_PAGE2 0x80
|
||||
#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
|
||||
|
||||
/* Data configuration register */
|
||||
|
||||
#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
|
||||
#define DP_DCR_BOS 0x02 /* 1=Little Endian */
|
||||
#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
|
||||
#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
|
||||
#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
|
||||
#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
|
||||
#define DP_DCR_FIFO_2 0x20
|
||||
#define DP_DCR_FIFO_4 0x40
|
||||
#define DP_DCR_FIFO_6 0x60
|
||||
|
||||
#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4)
|
||||
|
||||
/* Interrupt status register */
|
||||
|
||||
#define DP_ISR_RxP 0x01 /* Packet received */
|
||||
#define DP_ISR_TxP 0x02 /* Packet transmitted */
|
||||
#define DP_ISR_RxE 0x04 /* Receive error */
|
||||
#define DP_ISR_TxE 0x08 /* Transmit error */
|
||||
#define DP_ISR_OFLW 0x10 /* Receive overflow */
|
||||
#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
|
||||
#define DP_ISR_RDC 0x40 /* Remote DMA complete */
|
||||
#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
|
||||
|
||||
/* Interrupt mask register */
|
||||
|
||||
#define DP_IMR_RxP 0x01 /* Packet received */
|
||||
#define DP_IMR_TxP 0x02 /* Packet transmitted */
|
||||
#define DP_IMR_RxE 0x04 /* Receive error */
|
||||
#define DP_IMR_TxE 0x08 /* Transmit error */
|
||||
#define DP_IMR_OFLW 0x10 /* Receive overflow */
|
||||
#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
|
||||
#define DP_IMR_RDC 0x40 /* Remote DMA complete */
|
||||
|
||||
#define DP_IMR_All 0x3F /* Everything but remote DMA */
|
||||
|
||||
/* Receiver control register */
|
||||
|
||||
#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
|
||||
#define DP_RCR_AR 0x02 /* Accept runt packets */
|
||||
#define DP_RCR_AB 0x04 /* Accept broadcast packets */
|
||||
#define DP_RCR_AM 0x08 /* Accept multicast packets */
|
||||
#define DP_RCR_PROM 0x10 /* Promiscuous mode */
|
||||
#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
|
||||
|
||||
/* Receiver status register */
|
||||
|
||||
#define DP_RSR_RxP 0x01 /* Packet received */
|
||||
#define DP_RSR_CRC 0x02 /* CRC error */
|
||||
#define DP_RSR_FRAME 0x04 /* Framing error */
|
||||
#define DP_RSR_FO 0x08 /* FIFO overrun */
|
||||
#define DP_RSR_MISS 0x10 /* Missed packet */
|
||||
#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
|
||||
#define DP_RSR_DIS 0x40 /* Receiver disabled */
|
||||
#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
|
||||
|
||||
/* Transmitter control register */
|
||||
|
||||
#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
|
||||
#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
|
||||
#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
|
||||
#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
|
||||
#define DP_TCR_OUTLOOP 0x08 /* External loopback */
|
||||
#define DP_TCR_ATD 0x10 /* Auto transmit disable */
|
||||
#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
|
||||
|
||||
/* Transmit status register */
|
||||
|
||||
#define DP_TSR_TxP 0x01 /* Packet transmitted */
|
||||
#define DP_TSR_COL 0x04 /* Collision (at least one) */
|
||||
#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
|
||||
#define DP_TSR_CRS 0x10 /* Lost carrier */
|
||||
#define DP_TSR_FU 0x20 /* FIFO underrun */
|
||||
#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
|
||||
#define DP_TSR_OWC 0x80 /* Collision outside normal window */
|
||||
|
||||
#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
|
||||
#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */
|
||||
#endif /* __DRIVERS_NE2000_H__ */
|
||||
|
||||
282
drivers/net/ne2000_base.h
Normal file
282
drivers/net/ne2000_base.h
Normal file
@ -0,0 +1,282 @@
|
||||
/*
|
||||
Ported to U-Boot by Christian Pellegrin <chri@ascensit.com>
|
||||
|
||||
Based on sources from the Linux kernel (pcnet_cs.c, 8390.h) and
|
||||
eCOS(if_dp83902a.c, if_dp83902a.h). Both of these 2 wonderful world
|
||||
are GPL, so this is, of course, GPL.
|
||||
|
||||
|
||||
==========================================================================
|
||||
|
||||
dev/dp83902a.h
|
||||
|
||||
National Semiconductor DP83902a ethernet chip
|
||||
|
||||
==========================================================================
|
||||
####ECOSGPLCOPYRIGHTBEGIN####
|
||||
-------------------------------------------
|
||||
This file is part of eCos, the Embedded Configurable Operating System.
|
||||
Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
||||
|
||||
eCos is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free
|
||||
Software Foundation; either version 2 or (at your option) any later version.
|
||||
|
||||
eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License along
|
||||
with eCos; if not, write to the Free Software Foundation, Inc.,
|
||||
59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
||||
|
||||
As a special exception, if other files instantiate templates or use macros
|
||||
or inline functions from this file, or you compile this file and link it
|
||||
with other works to produce a work based on this file, this file does not
|
||||
by itself cause the resulting work to be covered by the GNU General Public
|
||||
License. However the source code for this file must still be made available
|
||||
in accordance with section (3) of the GNU General Public License.
|
||||
|
||||
This exception does not invalidate any other reasons why a work based on
|
||||
this file might be covered by the GNU General Public License.
|
||||
|
||||
Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
||||
at http://sources.redhat.com/ecos/ecos-license/
|
||||
-------------------------------------------
|
||||
####ECOSGPLCOPYRIGHTEND####
|
||||
####BSDCOPYRIGHTBEGIN####
|
||||
|
||||
-------------------------------------------
|
||||
|
||||
Portions of this software may have been derived from OpenBSD or other sources,
|
||||
and are covered by the appropriate copyright disclaimers included herein.
|
||||
|
||||
-------------------------------------------
|
||||
|
||||
####BSDCOPYRIGHTEND####
|
||||
==========================================================================
|
||||
#####DESCRIPTIONBEGIN####
|
||||
|
||||
Author(s): gthomas
|
||||
Contributors: gthomas, jskov
|
||||
Date: 2001-06-13
|
||||
Purpose:
|
||||
Description:
|
||||
|
||||
####DESCRIPTIONEND####
|
||||
|
||||
==========================================================================
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
------------------------------------------------------------------------
|
||||
Macros for accessing DP registers
|
||||
These can be overridden by the platform header
|
||||
*/
|
||||
|
||||
#define bool int
|
||||
|
||||
#define false 0
|
||||
#define true 1
|
||||
|
||||
/* timeout for tx/rx in s */
|
||||
#define TOUT 5
|
||||
/* Ether MAC address size */
|
||||
#define ETHER_ADDR_LEN 6
|
||||
|
||||
|
||||
#define CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA 1
|
||||
#define CYGACC_CALL_IF_DELAY_US(X) udelay(X)
|
||||
|
||||
/* H/W infomation struct */
|
||||
typedef struct hw_info_t {
|
||||
u32 offset;
|
||||
u8 a0, a1, a2;
|
||||
u32 flags;
|
||||
} hw_info_t;
|
||||
|
||||
typedef struct dp83902a_priv_data {
|
||||
u8* base;
|
||||
u8* data;
|
||||
u8* reset;
|
||||
int tx_next; /* First free Tx page */
|
||||
int tx_int; /* Expecting interrupt from this buffer */
|
||||
int rx_next; /* First free Rx page */
|
||||
int tx1, tx2; /* Page numbers for Tx buffers */
|
||||
u32 tx1_key, tx2_key; /* Used to ack when packet sent */
|
||||
int tx1_len, tx2_len;
|
||||
bool tx_started, running, hardwired_esa;
|
||||
u8 esa[6];
|
||||
void* plf_priv;
|
||||
|
||||
/* Buffer allocation */
|
||||
int tx_buf1, tx_buf2;
|
||||
int rx_buf_start, rx_buf_end;
|
||||
} dp83902a_priv_data_t;
|
||||
|
||||
/*
|
||||
------------------------------------------------------------------------
|
||||
Some forward declarations
|
||||
*/
|
||||
int get_prom( u8* mac_addr);
|
||||
static void dp83902a_poll(void);
|
||||
|
||||
/* ------------------------------------------------------------------------ */
|
||||
/* Register offsets */
|
||||
|
||||
#define DP_CR 0x00
|
||||
#define DP_CLDA0 0x01
|
||||
#define DP_PSTART 0x01 /* write */
|
||||
#define DP_CLDA1 0x02
|
||||
#define DP_PSTOP 0x02 /* write */
|
||||
#define DP_BNDRY 0x03
|
||||
#define DP_TSR 0x04
|
||||
#define DP_TPSR 0x04 /* write */
|
||||
#define DP_NCR 0x05
|
||||
#define DP_TBCL 0x05 /* write */
|
||||
#define DP_FIFO 0x06
|
||||
#define DP_TBCH 0x06 /* write */
|
||||
#define DP_ISR 0x07
|
||||
#define DP_CRDA0 0x08
|
||||
#define DP_RSAL 0x08 /* write */
|
||||
#define DP_CRDA1 0x09
|
||||
#define DP_RSAH 0x09 /* write */
|
||||
#define DP_RBCL 0x0a /* write */
|
||||
#define DP_RBCH 0x0b /* write */
|
||||
#define DP_RSR 0x0c
|
||||
#define DP_RCR 0x0c /* write */
|
||||
#define DP_FER 0x0d
|
||||
#define DP_TCR 0x0d /* write */
|
||||
#define DP_CER 0x0e
|
||||
#define DP_DCR 0x0e /* write */
|
||||
#define DP_MISSED 0x0f
|
||||
#define DP_IMR 0x0f /* write */
|
||||
#define DP_DATAPORT 0x10 /* "eprom" data port */
|
||||
|
||||
#define DP_P1_CR 0x00
|
||||
#define DP_P1_PAR0 0x01
|
||||
#define DP_P1_PAR1 0x02
|
||||
#define DP_P1_PAR2 0x03
|
||||
#define DP_P1_PAR3 0x04
|
||||
#define DP_P1_PAR4 0x05
|
||||
#define DP_P1_PAR5 0x06
|
||||
#define DP_P1_CURP 0x07
|
||||
#define DP_P1_MAR0 0x08
|
||||
#define DP_P1_MAR1 0x09
|
||||
#define DP_P1_MAR2 0x0a
|
||||
#define DP_P1_MAR3 0x0b
|
||||
#define DP_P1_MAR4 0x0c
|
||||
#define DP_P1_MAR5 0x0d
|
||||
#define DP_P1_MAR6 0x0e
|
||||
#define DP_P1_MAR7 0x0f
|
||||
|
||||
#define DP_P2_CR 0x00
|
||||
#define DP_P2_PSTART 0x01
|
||||
#define DP_P2_CLDA0 0x01 /* write */
|
||||
#define DP_P2_PSTOP 0x02
|
||||
#define DP_P2_CLDA1 0x02 /* write */
|
||||
#define DP_P2_RNPP 0x03
|
||||
#define DP_P2_TPSR 0x04
|
||||
#define DP_P2_LNPP 0x05
|
||||
#define DP_P2_ACH 0x06
|
||||
#define DP_P2_ACL 0x07
|
||||
#define DP_P2_RCR 0x0c
|
||||
#define DP_P2_TCR 0x0d
|
||||
#define DP_P2_DCR 0x0e
|
||||
#define DP_P2_IMR 0x0f
|
||||
|
||||
/* Command register - common to all pages */
|
||||
|
||||
#define DP_CR_STOP 0x01 /* Stop: software reset */
|
||||
#define DP_CR_START 0x02 /* Start: initialize device */
|
||||
#define DP_CR_TXPKT 0x04 /* Transmit packet */
|
||||
#define DP_CR_RDMA 0x08 /* Read DMA (recv data from device) */
|
||||
#define DP_CR_WDMA 0x10 /* Write DMA (send data to device) */
|
||||
#define DP_CR_SEND 0x18 /* Send packet */
|
||||
#define DP_CR_NODMA 0x20 /* Remote (or no) DMA */
|
||||
#define DP_CR_PAGE0 0x00 /* Page select */
|
||||
#define DP_CR_PAGE1 0x40
|
||||
#define DP_CR_PAGE2 0x80
|
||||
#define DP_CR_PAGEMSK 0x3F /* Used to mask out page bits */
|
||||
|
||||
/* Data configuration register */
|
||||
|
||||
#define DP_DCR_WTS 0x01 /* 1=16 bit word transfers */
|
||||
#define DP_DCR_BOS 0x02 /* 1=Little Endian */
|
||||
#define DP_DCR_LAS 0x04 /* 1=Single 32 bit DMA mode */
|
||||
#define DP_DCR_LS 0x08 /* 1=normal mode, 0=loopback */
|
||||
#define DP_DCR_ARM 0x10 /* 0=no send command (program I/O) */
|
||||
#define DP_DCR_FIFO_1 0x00 /* FIFO threshold */
|
||||
#define DP_DCR_FIFO_2 0x20
|
||||
#define DP_DCR_FIFO_4 0x40
|
||||
#define DP_DCR_FIFO_6 0x60
|
||||
|
||||
#define DP_DCR_INIT (DP_DCR_LS|DP_DCR_FIFO_4)
|
||||
|
||||
/* Interrupt status register */
|
||||
|
||||
#define DP_ISR_RxP 0x01 /* Packet received */
|
||||
#define DP_ISR_TxP 0x02 /* Packet transmitted */
|
||||
#define DP_ISR_RxE 0x04 /* Receive error */
|
||||
#define DP_ISR_TxE 0x08 /* Transmit error */
|
||||
#define DP_ISR_OFLW 0x10 /* Receive overflow */
|
||||
#define DP_ISR_CNT 0x20 /* Tally counters need emptying */
|
||||
#define DP_ISR_RDC 0x40 /* Remote DMA complete */
|
||||
#define DP_ISR_RESET 0x80 /* Device has reset (shutdown, error) */
|
||||
|
||||
/* Interrupt mask register */
|
||||
|
||||
#define DP_IMR_RxP 0x01 /* Packet received */
|
||||
#define DP_IMR_TxP 0x02 /* Packet transmitted */
|
||||
#define DP_IMR_RxE 0x04 /* Receive error */
|
||||
#define DP_IMR_TxE 0x08 /* Transmit error */
|
||||
#define DP_IMR_OFLW 0x10 /* Receive overflow */
|
||||
#define DP_IMR_CNT 0x20 /* Tall counters need emptying */
|
||||
#define DP_IMR_RDC 0x40 /* Remote DMA complete */
|
||||
|
||||
#define DP_IMR_All 0x3F /* Everything but remote DMA */
|
||||
|
||||
/* Receiver control register */
|
||||
|
||||
#define DP_RCR_SEP 0x01 /* Save bad(error) packets */
|
||||
#define DP_RCR_AR 0x02 /* Accept runt packets */
|
||||
#define DP_RCR_AB 0x04 /* Accept broadcast packets */
|
||||
#define DP_RCR_AM 0x08 /* Accept multicast packets */
|
||||
#define DP_RCR_PROM 0x10 /* Promiscuous mode */
|
||||
#define DP_RCR_MON 0x20 /* Monitor mode - 1=accept no packets */
|
||||
|
||||
/* Receiver status register */
|
||||
|
||||
#define DP_RSR_RxP 0x01 /* Packet received */
|
||||
#define DP_RSR_CRC 0x02 /* CRC error */
|
||||
#define DP_RSR_FRAME 0x04 /* Framing error */
|
||||
#define DP_RSR_FO 0x08 /* FIFO overrun */
|
||||
#define DP_RSR_MISS 0x10 /* Missed packet */
|
||||
#define DP_RSR_PHY 0x20 /* 0=pad match, 1=mad match */
|
||||
#define DP_RSR_DIS 0x40 /* Receiver disabled */
|
||||
#define DP_RSR_DFR 0x80 /* Receiver processing deferred */
|
||||
|
||||
/* Transmitter control register */
|
||||
|
||||
#define DP_TCR_NOCRC 0x01 /* 1=inhibit CRC */
|
||||
#define DP_TCR_NORMAL 0x00 /* Normal transmitter operation */
|
||||
#define DP_TCR_LOCAL 0x02 /* Internal NIC loopback */
|
||||
#define DP_TCR_INLOOP 0x04 /* Full internal loopback */
|
||||
#define DP_TCR_OUTLOOP 0x08 /* External loopback */
|
||||
#define DP_TCR_ATD 0x10 /* Auto transmit disable */
|
||||
#define DP_TCR_OFFSET 0x20 /* Collision offset adjust */
|
||||
|
||||
/* Transmit status register */
|
||||
|
||||
#define DP_TSR_TxP 0x01 /* Packet transmitted */
|
||||
#define DP_TSR_COL 0x04 /* Collision (at least one) */
|
||||
#define DP_TSR_ABT 0x08 /* Aborted because of too many collisions */
|
||||
#define DP_TSR_CRS 0x10 /* Lost carrier */
|
||||
#define DP_TSR_FU 0x20 /* FIFO underrun */
|
||||
#define DP_TSR_CDH 0x40 /* Collision Detect Heartbeat */
|
||||
#define DP_TSR_OWC 0x80 /* Collision outside normal window */
|
||||
|
||||
#define IEEE_8023_MAX_FRAME 1518 /* Largest possible ethernet frame */
|
||||
#define IEEE_8023_MIN_FRAME 64 /* Smallest possible ethernet frame */
|
||||
Loading…
Reference in New Issue
Block a user