mirror of
https://github.com/u-boot/u-boot.git
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rockchip: Add support for veyron-mickey (Chromebit)
This adds support for the Asus Chromebit, and RK3288-based device designed to plug directly into an HDMI monitor. The device tree file comes from Linux v4.8. Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass
parent
095e6c1f2d
commit
e70408c069
@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk3036-sdk.dtb \
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rk3288-firefly.dtb \
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rk3288-veyron-jerry.dtb \
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rk3288-veyron-mickey.dtb \
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rk3288-rock2-square.dtb \
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rk3288-evb.dtb \
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rk3288-fennec.dtb \
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277
arch/arm/dts/rk3288-veyron-mickey.dts
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277
arch/arm/dts/rk3288-veyron-mickey.dts
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@ -0,0 +1,277 @@
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/*
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* Google Veyron Mickey Rev 0 board device tree source
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*
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* Copyright 2015 Google, Inc
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "rk3288-veyron-chromebook.dtsi"
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/ {
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model = "Google Mickey";
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compatible = "google,veyron-mickey-rev8", "google,veyron-mickey-rev7",
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"google,veyron-mickey-rev6", "google,veyron-mickey-rev5",
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"google,veyron-mickey-rev4", "google,veyron-mickey-rev3",
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"google,veyron-mickey-rev2", "google,veyron-mickey-rev1",
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"google,veyron-mickey-rev0", "google,veyron-mickey",
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"google,veyron", "rockchip,rk3288";
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vcc_5v: vcc-5v {
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vin-supply = <&vcc33_sys>;
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};
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vcc33_io: vcc33_io {
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compatible = "regulator-fixed";
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regulator-name = "vcc33_io";
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regulator-always-on;
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regulator-boot-on;
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vin-supply = <&vcc33_sys>;
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};
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};
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&cpu_thermal {
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/delete-node/ trips;
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/delete-node/ cooling-maps;
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trips {
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cpu_alert_almost_warm: cpu_alert_almost_warm {
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temperature = <63000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_warm: cpu_alert_warm {
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temperature = <65000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_almost_hot: cpu_alert_almost_hot {
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temperature = <80000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_hot: cpu_alert_hot {
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temperature = <82000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_hotter: cpu_alert_hotter {
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temperature = <84000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert_very_hot: cpu_alert_very_hot {
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temperature = <85000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_crit: cpu_crit {
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temperature = <90000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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/*
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* After 1st level, throttle the CPU down to as low as 1.4 GHz
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* and don't let the GPU go faster than 400 MHz. Note that we
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* won't throttle the GPU lower than 400 MHz due to CPU
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* heat--we'll let the GPU do the rest itself.
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*/
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cpu_warm_limit_cpu {
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trip = <&cpu_alert_warm>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT 4>;
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};
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/*
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* Add some discrete steps to help throttling system deal
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* with the fact that there are two passive cooling devices:
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* the CPU and the GPU.
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*
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* - 1.2 GHz - 1.0 GHz (almost hot)
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* - 800 MHz (hot)
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* - 800 MHz - 696 MHz (hotter)
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* - 696 MHz - min (very hot)
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*
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* Note:
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* - 800 MHz appears to be a "sweet spot" for me. I can run
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* some pretty serious workload here and be happy.
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* - After 696 MHz we stop lowering voltage, so throttling
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* past there is less effective.
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*/
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cpu_almost_hot_limit_cpu {
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trip = <&cpu_alert_almost_hot>;
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cooling-device =
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<&cpu0 5 6>;
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};
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cpu_hot_limit_cpu {
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trip = <&cpu_alert_hot>;
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cooling-device =
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<&cpu0 7 7>;
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};
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cpu_hotter_limit_cpu {
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trip = <&cpu_alert_hotter>;
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cooling-device =
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<&cpu0 7 8>;
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};
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cpu_very_hot_limit_cpu {
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trip = <&cpu_alert_very_hot>;
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cooling-device =
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<&cpu0 8 THERMAL_NO_LIMIT>;
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};
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};
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};
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&dmc {
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rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
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0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
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0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
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0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
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0x8 0x1f4>;
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rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
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0x0 0xc3 0x6 0x2>;
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rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 1>;
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};
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&emmc {
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/delete-property/mmc-hs200-1_8v;
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};
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&i2c2 {
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status = "disabled";
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};
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&i2c4 {
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status = "disabled";
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};
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&i2s {
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status = "okay";
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clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out";
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clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>;
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};
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&rk808 {
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
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dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>,
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<&gpio7 15 GPIO_ACTIVE_HIGH>;
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/delete-property/ vcc6-supply;
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/delete-property/ vcc12-supply;
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vcc11-supply = <&vcc33_sys>;
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regulators {
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/* vcc33_io is sourced directly from vcc33_sys */
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/delete-node/ LDO_REG1;
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/delete-node/ LDO_REG7;
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/* This is not a pwren anymore, but the real power supply */
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vdd10_lcd: LDO_REG7 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-name = "vdd10_lcd";
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regulator-suspend-mem-disabled;
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};
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vcc18_lcd: LDO_REG8 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc18_lcd";
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regulator-suspend-mem-disabled;
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};
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};
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};
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&pinctrl {
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hdmi {
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power_hdmi_on: power-hdmi-on {
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rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
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};
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};
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pmic {
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dvs_1: dvs-1 {
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rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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dvs_2: dvs-2 {
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rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
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};
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};
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};
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&sdmmc {
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status = "disabled";
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};
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&sdio0 {
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status = "disabled";
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};
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&sdmmc {
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status = "disabled";
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};
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&spi0 {
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status = "disabled";
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};
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&usb_host0_ehci {
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status = "disabled";
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};
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&usb_host1 {
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status = "disabled";
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};
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&vcc50_hdmi {
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enable-active-high;
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gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&power_hdmi_on>;
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};
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@ -64,7 +64,8 @@ u32 spl_boot_device(void)
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}
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fallback:
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#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
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#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
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defined(CONFIG_TARGET_CHROMEBIT_MICKEY)
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return BOOT_DEVICE_SPI;
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#endif
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return BOOT_DEVICE_MMC1;
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@ -49,6 +49,15 @@ config TARGET_CHROMEBOOK_JERRY
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WiFi. It includes a Chrome OS EC (Cortex-M3) to provide access to
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the keyboard and battery functions.
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config TARGET_CHROMEBIT_MICKEY
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bool "Google/Rockchip Veyron-Mickey Chromebit"
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help
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Mickey is a small RK3288-based device with one USB 3.0 port, HDMI
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and WiFi. It has a separate power port and is designed to connect
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to the HDMI input of a monitor or TV. It has no internal battery.
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Typically a USB hub or wireless keyboard/touchpad is used to get
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keyboard and mouse access.
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config TARGET_ROCK2
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bool "Radxa Rock 2"
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help
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@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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endif
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if TARGET_CHROMEBIT_MICKEY
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config SYS_BOARD
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default "veyron"
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config SYS_VENDOR
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default "google"
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config SYS_CONFIG_NAME
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default "veyron"
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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endif
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@ -4,3 +4,10 @@ S: Maintained
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F: board/google/veyron/
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F: include/configs/veyron.h
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F: configs/chromebook_jerry_defconfig
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CHROMEBIT MICKEY BOARD
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M: Simon Glass <sjg@chromium.org>
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S: Maintained
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F: board/google/veyron/
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F: include/configs/veyron.h
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F: configs/chromebit_mickey_defconfig
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84
configs/chromebit_mickey_defconfig
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84
configs/chromebit_mickey_defconfig
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@ -0,0 +1,84 @@
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CONFIG_ARM=y
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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# CONFIG_SPL_MMC_SUPPORT is not set
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CONFIG_ROCKCHIP_RK3288=y
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CONFIG_TARGET_CHROMEBIT_MICKEY=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI_SUPPORT=y
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CONFIG_SPL_STACK_R_ADDR=0x80000
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CONFIG_DM_KEYBOARD=y
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CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-mickey"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMLS is not set
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_SPI=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_TIME=y
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_FS_GENERIC=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_REGMAP=y
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CONFIG_SPL_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_SPL_SYSCON=y
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# CONFIG_SPL_SIMPLE_BUS is not set
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CONFIG_CLK=y
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CONFIG_SPL_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_I2C_CROS_EC_TUNNEL=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_I2C_MUX=y
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CONFIG_CROS_EC_KEYB=y
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CONFIG_CMD_CROS_EC=y
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CONFIG_CROS_EC=y
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CONFIG_CROS_EC_SPI=y
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CONFIG_PWRSEQ=y
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CONFIG_ROCKCHIP_DWMMC=y
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CONFIG_PINCTRL=y
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CONFIG_SPL_PINCTRL=y
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# CONFIG_SPL_PINCTRL_FULL is not set
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CONFIG_ROCKCHIP_RK3288_PINCTRL=y
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CONFIG_DM_PMIC=y
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# CONFIG_SPL_PMIC_CHILDREN is not set
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CONFIG_PMIC_RK808=y
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CONFIG_DM_REGULATOR=y
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CONFIG_SPL_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_REGULATOR_RK808=y
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CONFIG_DM_PWM=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_RAM=y
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CONFIG_SPL_RAM=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_BASE=0xff690000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550=y
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CONFIG_ROCKCHIP_SERIAL=y
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CONFIG_ROCKCHIP_SPI=y
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CONFIG_SYSRESET=y
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CONFIG_DM_VIDEO=y
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CONFIG_DISPLAY=y
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CONFIG_VIDEO_ROCKCHIP=y
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CONFIG_USE_TINY_PRINTF=y
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CONFIG_CMD_DHRYSTONE=y
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CONFIG_ERRNO_STR=y
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CONFIG_SPL_OF_PLATDATA=y
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# CONFIG_SPL_OF_LIBFDT is not set
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