mirrors/u-boot
0
0
Fork 0
mirror of https://github.com/u-boot/u-boot.git synced 2024-11-24 20:54:24 +08:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

Browse Source
This commit is contained in:
Albert ARIBAUD 2013-02-02 19:29:59 +01:00
commit e5f5c4a977
68 changed files with 3418 additions and 973 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
.gitignore vendored
View File

@ -15,6 +15,7 @@
*.swp
*.patch
*.bin
*.cfgtmp
# Build tree
/build-*

5
MAINTAINERS
View File

@ -935,6 +935,7 @@ Marek Vasut <marek.vasut@gmail.com>
palmtc xscale/pxa
vpac270 xscale/pxa
zipitz2 xscale/pxa
mx23_olinuxino i.MX23
m28evk i.MX28
sc_sps_1 i.MX28
@ -946,6 +947,10 @@ Matt Waddel <matt.waddel@linaro.org>
ca9x4_ct_vxp ARM ARMV7 (Quad Core)
Otavio Salvador <otavio@ossystems.com.br>
mx23evk i.MX23
Prafulla Wadaskar <prafulla@marvell.com>
aspenite ARM926EJS (ARMADA100 88AP168 SoC)

9
Makefile
View File

@ -467,9 +467,8 @@ $(obj)u-boot.img: $(obj)u-boot.bin
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
$(obj)u-boot.imx: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(OBJTREE)/u-boot.imx : $(obj)u-boot.bin $(SUBDIR_TOOLS) depend
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
$(obj)u-boot.kwb: $(obj)u-boot.bin
$(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \
@ -508,6 +507,7 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img
$(obj)u-boot.ais
# Specify the target for use in elftosb call
ELFTOSB_TARGET-$(CONFIG_MX23) = imx23
ELFTOSB_TARGET-$(CONFIG_MX28) = imx28
$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
@ -843,7 +843,8 @@ clean:
@$(MAKE) -s -C doc/DocBook/ cleandocs
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \
-o -name '*.cfgtmp' \) -print \
| xargs rm -f
# Removes everything not needed for testing u-boot

2
arch/arm/cpu/arm926ejs/config.mk
View File

@ -34,6 +34,6 @@ PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(obj)u-boot.imx
ALL-y += $(OBJTREE)/u-boot.imx
endif

87
arch/arm/cpu/arm926ejs/mxs/clock.c
View File

@ -1,5 +1,5 @@
/*
* Freescale i.MX28 clock setup code
* Freescale i.MX23/i.MX28 clock setup code
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@ -32,16 +32,25 @@
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
/* The PLL frequency is always 480MHz, see section 10.2 in iMX28 datasheet. */
/*
* The PLL frequency is 480MHz and XTAL frequency is 24MHz
* iMX23: datasheet section 4.2
* iMX28: datasheet section 10.2
*/
#define PLL_FREQ_KHZ 480000
#define PLL_FREQ_COEF 18
/* The XTAL frequency is always 24MHz, see section 10.2 in iMX28 datasheet. */
#define XTAL_FREQ_KHZ 24000
#define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000)
#define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000)
static uint32_t mx28_get_pclk(void)
#if defined(CONFIG_MX23)
#define MXC_SSPCLK_MAX MXC_SSPCLK0
#elif defined(CONFIG_MX28)
#define MXC_SSPCLK_MAX MXC_SSPCLK3
#endif
static uint32_t mxs_get_pclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -73,7 +82,7 @@ static uint32_t mx28_get_pclk(void)
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
static uint32_t mx28_get_hclk(void)
static uint32_t mxs_get_hclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -88,10 +97,10 @@ static uint32_t mx28_get_hclk(void)
return 0;
div = clkctrl & CLKCTRL_HBUS_DIV_MASK;
return mx28_get_pclk() / div;
return mxs_get_pclk() / div;
}
static uint32_t mx28_get_emiclk(void)
static uint32_t mxs_get_emiclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -116,11 +125,17 @@ static uint32_t mx28_get_emiclk(void)
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
}
static uint32_t mx28_get_gpmiclk(void)
static uint32_t mxs_get_gpmiclk(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
#if defined(CONFIG_MX23)
uint8_t *reg =
&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
#elif defined(CONFIG_MX28)
uint8_t *reg =
&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
#endif
uint32_t clkctrl, clkseq, div;
uint8_t clkfrac, frac;
@ -134,7 +149,7 @@ static uint32_t mx28_get_gpmiclk(void)
}
/* REF Path */
clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]);
clkfrac = readb(reg);
frac = clkfrac & CLKCTRL_FRAC_FRAC_MASK;
div = clkctrl & CLKCTRL_GPMI_DIV_MASK;
return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div;
@ -143,7 +158,7 @@ static uint32_t mx28_get_gpmiclk(void)
/*
* Set IO clock frequency, in kHz
*/
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -176,7 +191,7 @@ void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq)
/*
* Get IO clock, returns IO clock in kHz
*/
static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
static uint32_t mxs_get_ioclk(enum mxs_ioclock io)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
@ -197,13 +212,13 @@ static uint32_t mx28_get_ioclk(enum mxs_ioclock io)
/*
* Configure SSP clock frequency, in kHz
*/
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clk, clkreg;
if (ssp > MXC_SSPCLK3)
if (ssp > MXC_SSPCLK_MAX)
return;
clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) +
@ -216,7 +231,7 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
if (xtal)
clk = XTAL_FREQ_KHZ;
else
clk = mx28_get_ioclk(ssp >> 1);
clk = mxs_get_ioclk(ssp >> 1);
if (freq > clk)
return;
@ -241,14 +256,14 @@ void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal)
/*
* Return SSP frequency, in kHz
*/
static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
uint32_t clkreg;
uint32_t clk, tmp;
if (ssp > MXC_SSPCLK3)
if (ssp > MXC_SSPCLK_MAX)
return 0;
tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq);
@ -263,7 +278,7 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
if (tmp == 0)
return 0;
clk = mx28_get_ioclk(ssp >> 1);
clk = mxs_get_ioclk(ssp >> 1);
return clk / tmp;
}
@ -271,14 +286,14 @@ static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp)
/*
* Set SSP/MMC bus frequency, in kHz)
*/
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq)
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq)
{
struct mxs_ssp_regs *ssp_regs;
const uint32_t sspclk = mx28_get_sspclk(bus);
const uint32_t sspclk = mxs_get_sspclk(bus);
uint32_t reg;
uint32_t divide, rate, tgtclk;
ssp_regs = (struct mxs_ssp_regs *)(MXS_SSP0_BASE + (bus * 0x2000));
ssp_regs = mxs_ssp_regs_by_bus(bus);
/*
* SSP bit rate = SSPCLK / (CLOCK_DIVIDE * (1 + CLOCK_RATE)),
@ -313,28 +328,30 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return mx28_get_pclk() * 1000000;
return mxs_get_pclk() * 1000000;
case MXC_GPMI_CLK:
return mx28_get_gpmiclk() * 1000000;
return mxs_get_gpmiclk() * 1000000;
case MXC_AHB_CLK:
case MXC_IPG_CLK:
return mx28_get_hclk() * 1000000;
return mxs_get_hclk() * 1000000;
case MXC_EMI_CLK:
return mx28_get_emiclk();
return mxs_get_emiclk();
case MXC_IO0_CLK:
return mx28_get_ioclk(MXC_IOCLK0);
return mxs_get_ioclk(MXC_IOCLK0);
case MXC_IO1_CLK:
return mx28_get_ioclk(MXC_IOCLK1);
case MXC_SSP0_CLK:
return mx28_get_sspclk(MXC_SSPCLK0);
case MXC_SSP1_CLK:
return mx28_get_sspclk(MXC_SSPCLK1);
case MXC_SSP2_CLK:
return mx28_get_sspclk(MXC_SSPCLK2);
case MXC_SSP3_CLK:
return mx28_get_sspclk(MXC_SSPCLK3);
return mxs_get_ioclk(MXC_IOCLK1);
case MXC_XTAL_CLK:
return XTAL_FREQ_KHZ * 1000;
case MXC_SSP0_CLK:
return mxs_get_sspclk(MXC_SSPCLK0);
#ifdef CONFIG_MX28
case MXC_SSP1_CLK:
return mxs_get_sspclk(MXC_SSPCLK1);
case MXC_SSP2_CLK:
return mxs_get_sspclk(MXC_SSPCLK2);
case MXC_SSP3_CLK:
return mxs_get_sspclk(MXC_SSPCLK3);
#endif
}
return 0;

25
arch/arm/cpu/arm926ejs/mxs/mxs.c
View File

@ -1,5 +1,5 @@
/*
* Freescale i.MX28 common code
* Freescale i.MX23/i.MX28 common code
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@ -35,6 +35,7 @@
#include <asm/arch/iomux.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
@ -196,6 +197,8 @@ static const char *get_cpu_type(void)
(struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
case HW_DIGCTL_CHIPID_MX23:
return "23";
case HW_DIGCTL_CHIPID_MX28:
return "28";
default:
@ -210,6 +213,21 @@ static const char *get_cpu_rev(void)
uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
case HW_DIGCTL_CHIPID_MX23:
switch (rev) {
case 0x0:
return "1.0";
case 0x1:
return "1.1";
case 0x2:
return "1.2";
case 0x3:
return "1.3";
case 0x4:
return "1.4";
default:
return "??";
}
case HW_DIGCTL_CHIPID_MX28:
switch (rev) {
case 0x1:
@ -276,7 +294,7 @@ int cpu_eth_init(bd_t *bis)
}
#endif
static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
__weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
{
mac[0] = 0x00;
mac[1] = 0x04; /* Use FSL vendor MAC address by default */
@ -285,9 +303,6 @@ static void __mx28_adjust_mac(int dev_id, unsigned char *mac)
mac[5] += 1;
}
void mx28_adjust_mac(int dev_id, unsigned char *mac)
__attribute__((weak, alias("__mx28_adjust_mac")));
#ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
#define MXS_OCOTP_MAX_TIMEOUT 1000000

25
arch/arm/cpu/arm926ejs/mxs/spl_boot.c
View File

@ -51,12 +51,21 @@ void early_delay(int delay)
#define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
static const iomux_cfg_t iomux_boot[] = {
#if defined(CONFIG_MX23)
MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
#elif defined(CONFIG_MX28)
MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
MX28_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
#endif
};
static uint8_t mxs_get_bootmode_index(void)
@ -68,6 +77,21 @@ static uint8_t mxs_get_bootmode_index(void)
/* Setup IOMUX of bootmode pads to GPIO */
mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
#if defined(CONFIG_MX23)
/* Setup bootmode pins as GPIO input */
gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
gpio_direction_input(MX23_PAD_LCD_D02__GPIO_1_2);
gpio_direction_input(MX23_PAD_LCD_D03__GPIO_1_3);
gpio_direction_input(MX23_PAD_LCD_D05__GPIO_1_5);
/* Read bootmode pads */
bootmode |= (gpio_get_value(MX23_PAD_LCD_D00__GPIO_1_0) ? 1 : 0) << 0;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D01__GPIO_1_1) ? 1 : 0) << 1;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
#elif defined(CONFIG_MX28)
/* Setup bootmode pins as GPIO input */
gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
@ -83,6 +107,7 @@ static uint8_t mxs_get_bootmode_index(void)
bootmode |= (gpio_get_value(MX28_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
bootmode |= (gpio_get_value(MX28_PAD_LCD_D04__GPIO_1_4) ? 1 : 0) << 4;
bootmode |= (gpio_get_value(MX28_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
#endif
for (i = 0; i < ARRAY_SIZE(mxs_boot_modes); i++) {
masked = bootmode & mxs_boot_modes[i].boot_mask;

118
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
View File

@ -27,6 +27,7 @@
#include <config.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <linux/compiler.h>
#include "mxs_init.h"
@ -83,16 +84,30 @@ static uint32_t dram_vals[] = {
0x06120612, 0x04320432, 0x04320432, 0x00040004,
0x00040004, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00010001
/*
* i.MX23 DDR at 133MHz
*/
#elif defined(CONFIG_MX23)
0x01010001, 0x00010100, 0x01000101, 0x00000001,
0x00000101, 0x00000000, 0x00010000, 0x01000001,
0x00000000, 0x00000001, 0x07000200, 0x00070202,
0x02020000, 0x04040a01, 0x00000201, 0x02040000,
0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313,
0x02061521, 0x0000000a, 0x00080008, 0x00200020,
0x00200020, 0x00200020, 0x000003f7, 0x00000000,
0x00000000, 0x00000020, 0x00000020, 0x00c80000,
0x000a23cd, 0x000000c8, 0x00006665, 0x00000000,
0x00000101, 0x00040001, 0x00000000, 0x00000000,
0x00010000
#else
#error Unsupported memory initialization
#endif
};
void __mxs_adjust_memory_params(uint32_t *dram_vals)
__weak void mxs_adjust_memory_params(uint32_t *dram_vals)
{
}
void mxs_adjust_memory_params(uint32_t *dram_vals)
__attribute__((weak, alias("__mxs_adjust_memory_params")));
static void initialize_dram_values(void)
{
@ -102,19 +117,30 @@ static void initialize_dram_values(void)
for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
#ifdef CONFIG_MX23
writel((1 << 24), MXS_DRAM_BASE + (4 * 8));
#endif
}
static void mxs_mem_init_clock(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
#if defined(CONFIG_MX23)
/* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
const unsigned char divider = 33;
#elif defined(CONFIG_MX28)
/* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
const unsigned char divider = 21;
#endif
/* Gate EMI clock */
writeb(CLKCTRL_FRAC_CLKGATE,
&clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_EMI]);
/* Set fractional divider for ref_emi to 480 * 18 / 21 = 411MHz */
writeb(CLKCTRL_FRAC_CLKGATE | (21 & CLKCTRL_FRAC_FRAC_MASK),
/* Set fractional divider for ref_emi */
writeb(CLKCTRL_FRAC_CLKGATE | (divider & CLKCTRL_FRAC_FRAC_MASK),
&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]);
/* Ungate EMI clock */
@ -197,10 +223,60 @@ uint32_t mxs_mem_get_size(void)
return sz;
}
void mxs_mem_init(void)
#ifdef CONFIG_MX23
static void mx23_mem_setup_vddmem(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
POWER_VDDMEMCTRL_ENABLE_ILIMIT |
POWER_VDDMEMCTRL_ENABLE_LINREG |
POWER_VDDMEMCTRL_PULLDOWN_ACTIVE,
&power_regs->hw_power_vddmemctrl);
early_delay(10000);
writel((0x12 << POWER_VDDMEMCTRL_TRG_OFFSET) |
POWER_VDDMEMCTRL_ENABLE_LINREG,
&power_regs->hw_power_vddmemctrl);
}
static void mx23_mem_init(void)
{
mx23_mem_setup_vddmem();
/*
* Configure the DRAM registers
*/
/* Clear START and SREFRESH bit from DRAM_CTL8 */
clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8));
initialize_dram_values();
/* Set START bit in DRAM_CTL16 */
setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
early_delay(20000);
/* Adjust EMI port priority. */
clrsetbits_le32(0x80020000, 0x1f << 16, 0x8);
early_delay(20000);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 19);
setbits_le32(MXS_DRAM_BASE + 0x40, 1 << 11);
/* Wait for bit 10 (DRAM init complete) in DRAM_CTL18 */
while (!(readl(MXS_DRAM_BASE + 0x48) & (1 << 10)))
;
}
#endif
#ifdef CONFIG_MX28
static void mx28_mem_init(void)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mxs_pinctrl_regs *pinctrl_regs =
(struct mxs_pinctrl_regs *)MXS_PINCTRL_BASE;
@ -208,16 +284,6 @@ void mxs_mem_init(void)
writel(PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2,
&pinctrl_regs->hw_pinctrl_emi_ds_ctrl_set);
/* Power up PLL0 */
writel(CLKCTRL_PLL0CTRL0_POWER,
&clkctrl_regs->hw_clkctrl_pll0ctrl0_set);
early_delay(11000);
mxs_mem_init_clock();
mxs_mem_setup_vdda();
/*
* Configure the DRAM registers
*/
@ -236,6 +302,22 @@ void mxs_mem_init(void)
/* Wait for bit 20 (DRAM init complete) in DRAM_CTL58 */
while (!(readl(MXS_DRAM_BASE + 0xe8) & (1 << 20)))
;
}
#endif
void mxs_mem_init(void)
{
early_delay(11000);
mxs_mem_init_clock();
mxs_mem_setup_vdda();
#if defined(CONFIG_MX23)
mx23_mem_init();
#elif defined(CONFIG_MX28)
mx28_mem_init();
#endif
early_delay(10000);

12
arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
View File

@ -881,11 +881,23 @@ static void mxs_setup_batt_detect(void)
early_delay(10);
}
static void mxs_ungate_power(void)
{
#ifdef CONFIG_MX23
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
#endif
}
void mxs_power_init(void)
{
struct mxs_power_regs *power_regs =
(struct mxs_power_regs *)MXS_POWER_BASE;
mxs_ungate_power();
mxs_power_clock2xtal();
mxs_power_clear_auto_restart();
mxs_power_set_linreg();

18
arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd Normal file
View File

@ -0,0 +1,18 @@
options {
driveTag = 0x00;
flags = 0x01;
}
sources {
u_boot_spl="spl/u-boot-spl.bin";
u_boot="u-boot.bin";
}
section (0) {
load u_boot_spl > 0x0000;
load ivt (entry = 0x0014) > 0x8000;
call 0x8000;
load u_boot > 0x40000100;
call 0x40000100;
}

2
arch/arm/cpu/armv7/config.mk
View File

@ -40,5 +40,5 @@ PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(obj)u-boot.imx
ALL-y += $(OBJTREE)/u-boot.imx
endif

13
arch/arm/imx-common/Makefile
View File

@ -42,6 +42,19 @@ all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
$(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp: $(OBJTREE)/%.cfgtmp : $(SRCTREE)/%
mkdir -p $(dir $@)
$(CC) -E -x c $< $(CPPFLAGS) -o $@
$(OBJTREE)/u-boot.imx: $(OBJTREE)/u-boot.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE) -d $< $@
$(OBJTREE)/SPL: $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/$(patsubst "%",%,$(CONFIG_IMX_CONFIG)).cfgtmp
$(OBJTREE)/tools/mkimage -n $(filter-out %.bin,$^) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
#########################################################################
# defines $(obj).depend target

14
arch/arm/include/asm/arch-mxs/clock.h
View File

@ -1,5 +1,5 @@
/*
* Freescale i.MX28 Clock
* Freescale i.MX23/i.MX28 Clock
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@ -31,11 +31,13 @@ enum mxc_clock {
MXC_GPMI_CLK,
MXC_IO0_CLK,
MXC_IO1_CLK,
MXC_XTAL_CLK,
MXC_SSP0_CLK,
#ifdef CONFIG_MX28
MXC_SSP1_CLK,
MXC_SSP2_CLK,
MXC_SSP3_CLK,
MXC_XTAL_CLK,
#endif
};
enum mxs_ioclock {
@ -45,16 +47,18 @@ enum mxs_ioclock {
enum mxs_sspclock {
MXC_SSPCLK0 = 0,
#ifdef CONFIG_MX28
MXC_SSPCLK1,
MXC_SSPCLK2,
MXC_SSPCLK3,
#endif
};
uint32_t mxc_get_clock(enum mxc_clock clk);
void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mx28_set_ssp_busclock(unsigned int bus, uint32_t freq);
void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq);
void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal);
void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq);
/* Compatibility with the FEC Ethernet driver */
#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK)

7
arch/arm/include/asm/arch-mxs/imx-regs.h
View File

@ -1,5 +1,5 @@
/*
* Freescale i.MX28 Registers
* Freescale i.MX23/i.MX28 Registers
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@ -37,6 +37,11 @@
#include <asm/arch/regs-ssp.h>
#include <asm/arch/regs-timrot.h>
#ifdef CONFIG_MX23
#include <asm/arch/regs-clkctrl-mx23.h>
#include <asm/arch/regs-power-mx23.h>
#endif
#ifdef CONFIG_MX28
#include <asm/arch/regs-clkctrl-mx28.h>
#include <asm/arch/regs-power-mx28.h>

355
arch/arm/include/asm/arch-mxs/iomux-mx23.h Normal file
View File

@ -0,0 +1,355 @@
/*
* Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
* Copyright (C) 2010 Freescale Semiconductor, Inc.
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#ifndef __MACH_IOMUX_MX23_H__
#define __MACH_IOMUX_MX23_H__
#include <asm/arch/iomux.h>
/*
* The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
* See also iomux.h
*
* BANK PIN MUX
*/
/* MUXSEL_0 */
#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0)
#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0)
#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0)
#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0)
#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0)
#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0)
#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0)
#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0)
#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
/* MUXSEL_1 */
#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1)
#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1)
#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1)
#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1)
#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1)
/* MUXSEL_2 */
#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2)
#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2)
#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2)
#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2)
#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2)
#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2)
#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2)
#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2)
#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2)
/* MUXSEL_GPIO */
#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO)
#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO)
#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO)
#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO)
#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO)
#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO)
#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO)
#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO)
#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
#endif /* __MACH_IOMUX_MX23_H__ */

121
arch/arm/include/asm/arch-mxs/regs-apbh.h
View File

@ -29,6 +29,87 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
mxs_reg_32(hw_apbh_ctrl2)
mxs_reg_32(hw_apbh_channel_ctrl)
union {
struct {
mxs_reg_32(hw_apbh_ch_curcmdar)
mxs_reg_32(hw_apbh_ch_nxtcmdar)
mxs_reg_32(hw_apbh_ch_cmd)
mxs_reg_32(hw_apbh_ch_bar)
mxs_reg_32(hw_apbh_ch_sema)
mxs_reg_32(hw_apbh_ch_debug1)
mxs_reg_32(hw_apbh_ch_debug2)
} ch[8];
struct {
mxs_reg_32(hw_apbh_ch0_curcmdar)
mxs_reg_32(hw_apbh_ch0_nxtcmdar)
mxs_reg_32(hw_apbh_ch0_cmd)
mxs_reg_32(hw_apbh_ch0_bar)
mxs_reg_32(hw_apbh_ch0_sema)
mxs_reg_32(hw_apbh_ch0_debug1)
mxs_reg_32(hw_apbh_ch0_debug2)
mxs_reg_32(hw_apbh_ch1_curcmdar)
mxs_reg_32(hw_apbh_ch1_nxtcmdar)
mxs_reg_32(hw_apbh_ch1_cmd)
mxs_reg_32(hw_apbh_ch1_bar)
mxs_reg_32(hw_apbh_ch1_sema)
mxs_reg_32(hw_apbh_ch1_debug1)
mxs_reg_32(hw_apbh_ch1_debug2)
mxs_reg_32(hw_apbh_ch2_curcmdar)
mxs_reg_32(hw_apbh_ch2_nxtcmdar)
mxs_reg_32(hw_apbh_ch2_cmd)
mxs_reg_32(hw_apbh_ch2_bar)
mxs_reg_32(hw_apbh_ch2_sema)
mxs_reg_32(hw_apbh_ch2_debug1)
mxs_reg_32(hw_apbh_ch2_debug2)
mxs_reg_32(hw_apbh_ch3_curcmdar)
mxs_reg_32(hw_apbh_ch3_nxtcmdar)
mxs_reg_32(hw_apbh_ch3_cmd)
mxs_reg_32(hw_apbh_ch3_bar)
mxs_reg_32(hw_apbh_ch3_sema)
mxs_reg_32(hw_apbh_ch3_debug1)
mxs_reg_32(hw_apbh_ch3_debug2)
mxs_reg_32(hw_apbh_ch4_curcmdar)
mxs_reg_32(hw_apbh_ch4_nxtcmdar)
mxs_reg_32(hw_apbh_ch4_cmd)
mxs_reg_32(hw_apbh_ch4_bar)
mxs_reg_32(hw_apbh_ch4_sema)
mxs_reg_32(hw_apbh_ch4_debug1)
mxs_reg_32(hw_apbh_ch4_debug2)
mxs_reg_32(hw_apbh_ch5_curcmdar)
mxs_reg_32(hw_apbh_ch5_nxtcmdar)
mxs_reg_32(hw_apbh_ch5_cmd)
mxs_reg_32(hw_apbh_ch5_bar)
mxs_reg_32(hw_apbh_ch5_sema)
mxs_reg_32(hw_apbh_ch5_debug1)
mxs_reg_32(hw_apbh_ch5_debug2)
mxs_reg_32(hw_apbh_ch6_curcmdar)
mxs_reg_32(hw_apbh_ch6_nxtcmdar)
mxs_reg_32(hw_apbh_ch6_cmd)
mxs_reg_32(hw_apbh_ch6_bar)
mxs_reg_32(hw_apbh_ch6_sema)
mxs_reg_32(hw_apbh_ch6_debug1)
mxs_reg_32(hw_apbh_ch6_debug2)
mxs_reg_32(hw_apbh_ch7_curcmdar)
mxs_reg_32(hw_apbh_ch7_nxtcmdar)
mxs_reg_32(hw_apbh_ch7_cmd)
mxs_reg_32(hw_apbh_ch7_bar)
mxs_reg_32(hw_apbh_ch7_sema)
mxs_reg_32(hw_apbh_ch7_debug1)
mxs_reg_32(hw_apbh_ch7_debug2)
};
};
mxs_reg_32(hw_apbh_version)
};
#elif defined(CONFIG_MX28)
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
@ -169,10 +250,26 @@ struct mxs_apbh_regs {
};
#endif
#endif
#define APBH_CTRL0_SFTRST (1 << 31)
#define APBH_CTRL0_CLKGATE (1 << 30)
#define APBH_CTRL0_AHB_BURST8_EN (1 << 29)
#define APBH_CTRL0_APB_BURST_EN (1 << 28)
#if defined(CONFIG_MX23)
#define APBH_CTRL0_RSVD0_MASK (0xf << 24)
#define APBH_CTRL0_RSVD0_OFFSET 24
#define APBH_CTRL0_RESET_CHANNEL_MASK (0xff << 16)
#define APBH_CTRL0_RESET_CHANNEL_OFFSET 16
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xff << 8)
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 8
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP0 0x02
#define APBH_CTRL0_CLKGATE_CHANNEL_SSP1 0x04
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x10
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x20
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND2 0x40
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND3 0x80
#elif defined(CONFIG_MX28)
#define APBH_CTRL0_RSVD0_MASK (0xfff << 16)
#define APBH_CTRL0_RSVD0_OFFSET 16
#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xffff
@ -191,6 +288,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
#endif
#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN (1 << 31)
#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN (1 << 30)
@ -260,6 +358,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL2_CH1_ERROR_IRQ (1 << 1)
#define APBH_CTRL2_CH0_ERROR_IRQ (1 << 0)
#if defined(CONFIG_MX28)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xffff << 16)
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0 (0x0001 << 16)
@ -292,7 +391,26 @@ struct mxs_apbh_regs {
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_NAND7 0x0800
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_HSADC 0x1000
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
#if defined(CONFIG_MX23)
#define APBH_DEVSEL_CH7_MASK (0xf << 28)
#define APBH_DEVSEL_CH7_OFFSET 28
#define APBH_DEVSEL_CH6_MASK (0xf << 24)
#define APBH_DEVSEL_CH6_OFFSET 24
#define APBH_DEVSEL_CH5_MASK (0xf << 20)
#define APBH_DEVSEL_CH5_OFFSET 20
#define APBH_DEVSEL_CH4_MASK (0xf << 16)
#define APBH_DEVSEL_CH4_OFFSET 16
#define APBH_DEVSEL_CH3_MASK (0xf << 12)
#define APBH_DEVSEL_CH3_OFFSET 12
#define APBH_DEVSEL_CH2_MASK (0xf << 8)
#define APBH_DEVSEL_CH2_OFFSET 8
#define APBH_DEVSEL_CH1_MASK (0xf << 4)
#define APBH_DEVSEL_CH1_OFFSET 4
#define APBH_DEVSEL_CH0_MASK (0xf << 0)
#define APBH_DEVSEL_CH0_OFFSET 0
#elif defined(CONFIG_MX28)
#define APBH_DEVSEL_CH15_MASK (0x3 << 30)
#define APBH_DEVSEL_CH15_OFFSET 30
#define APBH_DEVSEL_CH14_MASK (0x3 << 28)
@ -325,7 +443,9 @@ struct mxs_apbh_regs {
#define APBH_DEVSEL_CH1_OFFSET 2
#define APBH_DEVSEL_CH0_MASK (0x3 << 0)
#define APBH_DEVSEL_CH0_OFFSET 0
#endif
#if defined(CONFIG_MX28)
#define APBH_DMA_BURST_SIZE_CH15_MASK (0x3 << 30)
#define APBH_DMA_BURST_SIZE_CH15_OFFSET 30
#define APBH_DMA_BURST_SIZE_CH14_MASK (0x3 << 28)
@ -377,6 +497,7 @@ struct mxs_apbh_regs {
#define APBH_DMA_BURST_SIZE_CH0_BURST8 0x2
#define APBH_DEBUG_GPMI_ONE_FIFO (1 << 0)
#endif
#define APBH_CHn_CURCMDAR_CMD_ADDR_MASK 0xffffffff
#define APBH_CHn_CURCMDAR_CMD_ADDR_OFFSET 0

56
arch/arm/include/asm/arch-mxs/regs-base.h
View File

@ -1,5 +1,5 @@
/*
* Freescale i.MX28 Peripheral Base Addresses
* Freescale i.MX23/i.MX28 Peripheral Base Addresses
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
@ -25,12 +25,55 @@
*
*/
#ifndef __MX28_REGS_BASE_H__
#define __MX28_REGS_BASE_H__
#ifndef __MXS_REGS_BASE_H__
#define __MXS_REGS_BASE_H__
/*
* Register base address
* Register base addresses for i.MX23
*/
#if defined(CONFIG_MX23)
#define MXS_ICOLL_BASE 0x80000000
#define MXS_APBH_BASE 0x80004000
#define MXS_ECC8_BASE 0x80008000
#define MXS_BCH_BASE 0x8000A000
#define MXS_GPMI_BASE 0x8000C000
#define MXS_SSP0_BASE 0x80010000
#define MXS_SSP1_BASE 0x80034000
#define MXS_ETM_BASE 0x80014000
#define MXS_PINCTRL_BASE 0x80018000
#define MXS_DIGCTL_BASE 0x8001C000
#define MXS_EMI_BASE 0x80020000
#define MXS_APBX_BASE 0x80024000
#define MXS_DCP_BASE 0x80028000
#define MXS_PXP_BASE 0x8002A000
#define MXS_OCOTP_BASE 0x8002C000
#define MXS_AXI_BASE 0x8002E000
#define MXS_LCDIF_BASE 0x80030000
#define MXS_SSP1_BASE 0x80034000
#define MXS_TVENC_BASE 0x80038000
#define MXS_CLKCTRL_BASE 0x80040000
#define MXS_SAIF0_BASE 0x80042000
#define MXS_POWER_BASE 0x80044000
#define MXS_SAIF1_BASE 0x80046000
#define MXS_AUDIOOUT_BASE 0x80048000
#define MXS_AUDIOIN_BASE 0x8004C000
#define MXS_LRADC_BASE 0x80050000
#define MXS_SPDIF_BASE 0x80054000
#define MXS_I2C0_BASE 0x80058000
#define MXS_RTC_BASE 0x8005C000
#define MXS_PWM_BASE 0x80064000
#define MXS_TIMROT_BASE 0x80068000
#define MXS_UARTAPP0_BASE 0x8006C000
#define MXS_UARTAPP1_BASE 0x8006E000
#define MXS_UARTDBG_BASE 0x80070000
#define MXS_USBPHY0_BASE 0x8007C000
#define MXS_USBCTRL0_BASE 0x80080000
#define MXS_DRAM_BASE 0x800E0000
/*
* Register base addresses for i.MX28
*/
#elif defined(CONFIG_MX28)
#define MXS_ICOL_BASE 0x80000000
#define MXS_HSADC_BASE 0x80002000
#define MXS_APBH_BASE 0x80004000
@ -84,5 +127,8 @@
#define MXS_DRAM_BASE 0x800E0000
#define MXS_ENET0_BASE 0x800F0000
#define MXS_ENET1_BASE 0x800F4000
#else
#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28
#endif
#endif /* __MX28_REGS_BASE_H__ */
#endif /* __MXS_REGS_BASE_H__ */

221
arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h Normal file
View File

@ -0,0 +1,221 @@
/*
* Freescale i.MX23 CLKCTRL Register Definitions
*
* Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* Based on code from LTIB:
* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX23_REGS_CLKCTRL_H__
#define __MX23_REGS_CLKCTRL_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_clkctrl_regs {
mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */
uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */
uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */
mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */
mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */
mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */
mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */
mxs_reg_32(hw_clkctrl_pix) /* 0x60 */
mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */
mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */
mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */
mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */
uint32_t reserved1[4];
mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */
mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */
mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */
mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */
mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */
mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */
mxs_reg_32(hw_clkctrl_reset) /* 0x120 */
mxs_reg_32(hw_clkctrl_status) /* 0x130 */
mxs_reg_32(hw_clkctrl_version) /* 0x140 */
};
#endif
#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28
#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28)
#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28)
#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24
#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24)
#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20
#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20)
#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20)
#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18)
#define CLKCTRL_PLL0CTRL0_POWER (1 << 16)
#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31)
#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30)
#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff
#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0
#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29)
#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28)
#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26)
#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16)
#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16
#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12)
#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10)
#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f
#define CLKCTRL_CPU_DIV_CPU_OFFSET 0
#define CLKCTRL_HBUS_BUSY (1 << 29)
#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28)
#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27)
#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26)
#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25)
#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24)
#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23)
#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22)
#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21)
#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20)
#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16
#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16)
#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16)
#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5)
#define CLKCTRL_HBUS_DIV_MASK 0x1f
#define CLKCTRL_HBUS_DIV_OFFSET 0
#define CLKCTRL_XBUS_BUSY (1 << 31)
#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10)
#define CLKCTRL_XBUS_DIV_MASK 0x3ff
#define CLKCTRL_XBUS_DIV_OFFSET 0
#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31)
#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30)
#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29)
#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28)
#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27)
#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26)
#define CLKCTRL_XTAL_DIV_UART_MASK 0x3
#define CLKCTRL_XTAL_DIV_UART_OFFSET 0
#define CLKCTRL_PIX_CLKGATE (1 << 31)
#define CLKCTRL_PIX_BUSY (1 << 29)
#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12)
#define CLKCTRL_PIX_DIV_MASK 0xfff
#define CLKCTRL_PIX_DIV_OFFSET 0
#define CLKCTRL_SSP_CLKGATE (1 << 31)
#define CLKCTRL_SSP_BUSY (1 << 29)
#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9)
#define CLKCTRL_SSP_DIV_MASK 0x1ff
#define CLKCTRL_SSP_DIV_OFFSET 0
#define CLKCTRL_GPMI_CLKGATE (1 << 31)
#define CLKCTRL_GPMI_BUSY (1 << 29)
#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10)
#define CLKCTRL_GPMI_DIV_MASK 0x3ff
#define CLKCTRL_GPMI_DIV_OFFSET 0
#define CLKCTRL_SPDIF_CLKGATE (1 << 31)
#define CLKCTRL_EMI_CLKGATE (1 << 31)
#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30)
#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29)
#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28)
#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27)
#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26)
#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17)
#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16)
#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8)
#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8
#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f
#define CLKCTRL_EMI_DIV_EMI_OFFSET 0
#define CLKCTRL_IR_CLKGATE (1 << 31)
#define CLKCTRL_IR_AUTO_DIV (1 << 29)
#define CLKCTRL_IR_IR_BUSY (1 << 28)
#define CLKCTRL_IR_IROV_BUSY (1 << 27)
#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16)
#define CLKCTRL_IR_IROV_DIV_OFFSET 16
#define CLKCTRL_IR_IR_DIV_MASK 0x3ff
#define CLKCTRL_IR_IR_DIV_OFFSET 0
#define CLKCTRL_SAIF0_CLKGATE (1 << 31)
#define CLKCTRL_SAIF0_BUSY (1 << 29)
#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16)
#define CLKCTRL_SAIF0_DIV_MASK 0xffff
#define CLKCTRL_SAIF0_DIV_OFFSET 0
#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31)
#define CLKCTRL_TV_CLK_TV_GATE (1 << 30)
#define CLKCTRL_ETM_CLKGATE (1 << 31)
#define CLKCTRL_ETM_BUSY (1 << 29)
#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6)
#define CLKCTRL_ETM_DIV_MASK 0x3f
#define CLKCTRL_ETM_DIV_OFFSET 0
#define CLKCTRL_FRAC_CLKGATE (1 << 7)
#define CLKCTRL_FRAC_STABLE (1 << 6)
#define CLKCTRL_FRAC_FRAC_MASK 0x3f
#define CLKCTRL_FRAC_FRAC_OFFSET 0
#define CLKCTRL_FRAC0_CPU 0
#define CLKCTRL_FRAC0_EMI 1
#define CLKCTRL_FRAC0_PIX 2
#define CLKCTRL_FRAC0_IO0 3
#define CLKCTRL_FRAC1_VID 3
#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8)
#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7)
#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6)
#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5)
#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4)
#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3)
#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1)
#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0)
#define CLKCTRL_RESET_CHIP (1 << 1)
#define CLKCTRL_RESET_DIG (1 << 0)
#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30)
#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30
#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24)
#define CLKCTRL_VERSION_MAJOR_OFFSET 24
#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16)
#define CLKCTRL_VERSION_MINOR_OFFSET 16
#define CLKCTRL_VERSION_STEP_MASK 0xffff
#define CLKCTRL_VERSION_STEP_OFFSET 0
#endif /* __MX23_REGS_CLKCTRL_H__ */

1
arch/arm/include/asm/arch-mxs/regs-digctl.h
View File

@ -154,6 +154,7 @@ struct mxs_digctl_regs {
/* Product code identification */
#define HW_DIGCTL_CHIPID_MASK (0xffff << 16)
#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16)
#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16)
#endif /* __MX28_REGS_DIGCTL_H__ */

358
arch/arm/include/asm/arch-mxs/regs-power-mx23.h Normal file
View File

@ -0,0 +1,358 @@
/*
* Freescale i.MX23 Power Controller Register Definitions
*
* Copyright (C) 2012 Marek Vasut <marex@denx.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX23_REGS_POWER_H__
#define __MX23_REGS_POWER_H__
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
struct mxs_power_regs {
mxs_reg_32(hw_power_ctrl)
mxs_reg_32(hw_power_5vctrl)
mxs_reg_32(hw_power_minpwr)
mxs_reg_32(hw_power_charge)
uint32_t hw_power_vdddctrl;
uint32_t reserved_vddd[3];
uint32_t hw_power_vddactrl;
uint32_t reserved_vdda[3];
uint32_t hw_power_vddioctrl;
uint32_t reserved_vddio[3];
uint32_t hw_power_vddmemctrl;
uint32_t reserved_vddmem[3];
uint32_t hw_power_dcdc4p2;
uint32_t reserved_dcdc4p2[3];
uint32_t hw_power_misc;
uint32_t reserved_misc[3];
uint32_t hw_power_dclimits;
uint32_t reserved_dclimits[3];
mxs_reg_32(hw_power_loopctrl)
uint32_t hw_power_sts;
uint32_t reserved_sts[3];
mxs_reg_32(hw_power_speed)
uint32_t hw_power_battmonitor;
uint32_t reserved_battmonitor[3];
uint32_t reserved1[4];
mxs_reg_32(hw_power_reset)
uint32_t reserved2[4];
mxs_reg_32(hw_power_special)
mxs_reg_32(hw_power_version)
};
#endif
#define POWER_CTRL_CLKGATE (1 << 30)
#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27)
#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24)
#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23)
#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22)
#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21)
#define POWER_CTRL_PSWITCH_IRQ (1 << 20)
#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19)
#define POWER_CTRL_POLARITY_PSWITCH (1 << 18)
#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17)
#define POWER_CTRL_POLARITY_DC_OK (1 << 16)
#define POWER_CTRL_DC_OK_IRQ (1 << 15)
#define POWER_CTRL_ENIRQ_DC_OK (1 << 14)
#define POWER_CTRL_BATT_BO_IRQ (1 << 13)
#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12)
#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11)
#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10)
#define POWER_CTRL_VDDA_BO_IRQ (1 << 9)
#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8)
#define POWER_CTRL_VDDD_BO_IRQ (1 << 7)
#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6)
#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5)
#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4)
#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3)
#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2)
#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1)
#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0)
#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28)
#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28)
#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28)
#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24)
#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24
#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20)
#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20
#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12)
#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12
#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8
#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8)
#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8)
#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7)
#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6)
#define POWER_5VCTRL_DCDC_XFER (1 << 5)
#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4)
#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3)
#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2)
#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1)
#define POWER_5VCTRL_ENABLE_DCDC (1 << 0)
#define POWER_MINPWR_LOWPWR_4P2 (1 << 14)
#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13)
#define POWER_MINPWR_PWD_BO (1 << 12)
#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11)
#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10)
#define POWER_MINPWR_ENABLE_OSC (1 << 9)
#define POWER_MINPWR_SELECT_OSC (1 << 8)
#define POWER_MINPWR_VBG_OFF (1 << 7)
#define POWER_MINPWR_DOUBLE_FETS (1 << 6)
#define POWER_MINPWR_HALFFETS (1 << 5)
#define POWER_MINPWR_LESSANA_I (1 << 4)
#define POWER_MINPWR_PWD_XTAL24 (1 << 3)
#define POWER_MINPWR_DC_STOPCLK (1 << 2)
#define POWER_MINPWR_EN_DC_PFM (1 << 1)
#define POWER_MINPWR_DC_HALFCLK (1 << 0)
#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24)
#define POWER_CHARGE_ADJ_VOLT_OFFSET 24
#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24)
#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24)
#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24)
#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24)
#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24)
#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24)
#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24)
#define POWER_CHARGE_ENABLE_LOAD (1 << 22)
#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21)
#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20)
#define POWER_CHARGE_CHRG_STS_OFF (1 << 19)
#define POWER_CHARGE_USE_EXTERN_R (1 << 17)
#define POWER_CHARGE_PWD_BATTCHRG (1 << 16)
#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8)
#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8
#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8)
#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8)
#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8)
#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8)
#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f
#define POWER_CHARGE_BATTCHRG_I_OFFSET 0
#define POWER_CHARGE_BATTCHRG_I_10MA 0x01
#define POWER_CHARGE_BATTCHRG_I_20MA 0x02
#define POWER_CHARGE_BATTCHRG_I_50MA 0x04
#define POWER_CHARGE_BATTCHRG_I_100MA 0x08
#define POWER_CHARGE_BATTCHRG_I_200MA 0x10
#define POWER_CHARGE_BATTCHRG_I_400MA 0x20
#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28)
#define POWER_VDDDCTRL_ADJTN_OFFSET 28
#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23)
#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22)
#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21)
#define POWER_VDDDCTRL_DISABLE_FET (1 << 20)
#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16
#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16)
#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16)
#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDDCTRL_TRG_MASK 0x1f
#define POWER_VDDDCTRL_TRG_OFFSET 0
#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19)
#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18)
#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17)
#define POWER_VDDACTRL_DISABLE_FET (1 << 16)
#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12
#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDACTRL_TRG_MASK 0x1f
#define POWER_VDDACTRL_TRG_OFFSET 0
#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20)
#define POWER_VDDIOCTRL_ADJTN_OFFSET 20
#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18)
#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17)
#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16)
#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12
#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12)
#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12)
#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8)
#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8
#define POWER_VDDIOCTRL_TRG_MASK 0x1f
#define POWER_VDDIOCTRL_TRG_OFFSET 0
#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10)
#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9)
#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8)
#define POWER_VDDMEMCTRL_TRG_MASK 0x1f
#define POWER_VDDMEMCTRL_TRG_OFFSET 0
#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28
#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28)
#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28)
#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24)
#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24
#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23)
#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22)
#define POWER_DCDC4P2_HYST_DIR (1 << 21)
#define POWER_DCDC4P2_HYST_THRESH (1 << 20)
#define POWER_DCDC4P2_TRG_MASK (0x7 << 16)
#define POWER_DCDC4P2_TRG_OFFSET 16
#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16)
#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16)
#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16)
#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16)
#define POWER_DCDC4P2_TRG_BATT (0x4 << 16)
#define POWER_DCDC4P2_BO_MASK (0x1f << 8)
#define POWER_DCDC4P2_BO_OFFSET 8
#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f
#define POWER_DCDC4P2_CMPTRIP_OFFSET 0
#define POWER_MISC_FREQSEL_MASK (0x7 << 4)
#define POWER_MISC_FREQSEL_OFFSET 4
#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4)
#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4)
#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4)
#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4)
#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4)
#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4)
#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4)
#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3)
#define POWER_MISC_DELAY_TIMING (1 << 2)
#define POWER_MISC_TEST (1 << 1)
#define POWER_MISC_SEL_PLLCLK (1 << 0)
#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8)
#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8
#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f
#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0
#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20)
#define POWER_LOOPCTRL_HYST_SIGN (1 << 19)
#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18)
#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17)
#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16)
#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15)
#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14)
#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12
#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12)
#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12)
#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8)
#define POWER_LOOPCTRL_DC_FF_OFFSET 8
#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4)
#define POWER_LOOPCTRL_DC_R_OFFSET 4
#define POWER_LOOPCTRL_DC_C_MASK 0x3
#define POWER_LOOPCTRL_DC_C_OFFSET 0
#define POWER_LOOPCTRL_DC_C_MAX 0x0
#define POWER_LOOPCTRL_DC_C_2X 0x1
#define POWER_LOOPCTRL_DC_C_4X 0x2
#define POWER_LOOPCTRL_DC_C_MIN 0x3
#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24)
#define POWER_STS_PWRUP_SOURCE_OFFSET 24
#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24)
#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24)
#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24)
#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24)
#define POWER_STS_PSWITCH_MASK (0x3 << 20)
#define POWER_STS_PSWITCH_OFFSET 20
#define POWER_STS_AVALID0_STATUS (1 << 17)
#define POWER_STS_BVALID0_STATUS (1 << 16)
#define POWER_STS_VBUSVALID0_STATUS (1 << 15)
#define POWER_STS_SESSEND0_STATUS (1 << 14)
#define POWER_STS_BATT_BO (1 << 13)
#define POWER_STS_VDD5V_FAULT (1 << 12)
#define POWER_STS_CHRGSTS (1 << 11)
#define POWER_STS_DCDC_4P2_BO (1 << 10)
#define POWER_STS_DC_OK (1 << 9)
#define POWER_STS_VDDIO_BO (1 << 8)
#define POWER_STS_VDDA_BO (1 << 7)
#define POWER_STS_VDDD_BO (1 << 6)
#define POWER_STS_VDD5V_GT_VDDIO (1 << 5)
#define POWER_STS_VDD5V_DROOP (1 << 4)
#define POWER_STS_AVALID0 (1 << 3)
#define POWER_STS_BVALID0 (1 << 2)
#define POWER_STS_VBUSVALID0 (1 << 1)
#define POWER_STS_SESSEND0 (1 << 0)
#define POWER_SPEED_STATUS_MASK (0xff << 16)
#define POWER_SPEED_STATUS_OFFSET 16
#define POWER_SPEED_CTRL_MASK 0x3
#define POWER_SPEED_CTRL_OFFSET 0
#define POWER_SPEED_CTRL_SS_OFF 0x0
#define POWER_SPEED_CTRL_SS_ON 0x1
#define POWER_SPEED_CTRL_SS_ENABLE 0x3
#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16)
#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16
#define POWER_BATTMONITOR_EN_BATADJ (1 << 10)
#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9)
#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8)
#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f
#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0
#define POWER_RESET_UNLOCK_MASK (0xffff << 16)
#define POWER_RESET_UNLOCK_OFFSET 16
#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16)
#define POWER_RESET_PWD_OFF (1 << 1)
#define POWER_RESET_PWD (1 << 0)
#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3)
#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2)
#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1)
#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0)
#define POWER_SPECIAL_TEST_MASK 0xffffffff
#define POWER_SPECIAL_TEST_OFFSET 0
#define POWER_VERSION_MAJOR_MASK (0xff << 24)
#define POWER_VERSION_MAJOR_OFFSET 24
#define POWER_VERSION_MINOR_MASK (0xff << 16)
#define POWER_VERSION_MINOR_OFFSET 16
#define POWER_VERSION_STEP_MASK 0xffff
#define POWER_VERSION_STEP_OFFSET 0
#endif /* __MX23_REGS_POWER_H__ */

54
arch/arm/include/asm/arch-mxs/regs-ssp.h
View File

@ -28,6 +28,28 @@
#include <asm/arch/regs-common.h>
#ifndef __ASSEMBLY__
#if defined(CONFIG_MX23)
struct mxs_ssp_regs {
mxs_reg_32(hw_ssp_ctrl0)
mxs_reg_32(hw_ssp_cmd0)
mxs_reg_32(hw_ssp_cmd1)
mxs_reg_32(hw_ssp_compref)
mxs_reg_32(hw_ssp_compmask)
mxs_reg_32(hw_ssp_timing)
mxs_reg_32(hw_ssp_ctrl1)
mxs_reg_32(hw_ssp_data)
mxs_reg_32(hw_ssp_sdresp0)
mxs_reg_32(hw_ssp_sdresp1)
mxs_reg_32(hw_ssp_sdresp2)
mxs_reg_32(hw_ssp_sdresp3)
mxs_reg_32(hw_ssp_status)
uint32_t reserved1[12];
mxs_reg_32(hw_ssp_debug)
mxs_reg_32(hw_ssp_version)
};
#elif defined(CONFIG_MX28)
struct mxs_ssp_regs {
mxs_reg_32(hw_ssp_ctrl0)
mxs_reg_32(hw_ssp_cmd0)
@ -52,6 +74,25 @@ struct mxs_ssp_regs {
};
#endif
static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
{
switch (port) {
case 0:
return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
case 1:
return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
#ifdef CONFIG_MX28
case 2:
return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
case 3:
return (struct mxs_ssp_regs *)MXS_SSP3_BASE;
#endif
default:
return NULL;
}
}
#endif
#define SSP_CTRL0_SFTRST (1 << 31)
#define SSP_CTRL0_CLKGATE (1 << 30)
#define SSP_CTRL0_RUN (1 << 29)
@ -72,6 +113,11 @@ struct mxs_ssp_regs {
#define SSP_CTRL0_GET_RESP (1 << 17)
#define SSP_CTRL0_ENABLE (1 << 16)
#ifdef CONFIG_MX23
#define SSP_CTRL0_XFER_COUNT_OFFSET 0
#define SSP_CTRL0_XFER_COUNT_MASK 0xffff
#endif
#define SSP_CMD0_SOFT_TERMINATE (1 << 26)
#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24)
@ -79,6 +125,12 @@ struct mxs_ssp_regs {
#define SSP_CMD0_SLOW_CLKING_EN (1 << 22)
#define SSP_CMD0_CONT_CLKING_EN (1 << 21)
#define SSP_CMD0_APPEND_8CYC (1 << 20)
#if defined(CONFIG_MX23)
#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16)
#define SSP_CMD0_BLOCK_SIZE_OFFSET 16
#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8)
#define SSP_CMD0_BLOCK_COUNT_OFFSET 8
#endif
#define SSP_CMD0_CMD_MASK 0xff
#define SSP_CMD0_CMD_OFFSET 0
#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00
@ -152,6 +204,7 @@ struct mxs_ssp_regs {
#define SSP_CMD1_CMD_ARG_MASK 0xffffffff
#define SSP_CMD1_CMD_ARG_OFFSET 0
#if defined(CONFIG_MX28)
#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff
#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0
@ -159,6 +212,7 @@ struct mxs_ssp_regs {
#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4
#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf
#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0
#endif
#define SSP_COMPREF_REFERENCE_MASK 0xffffffff
#define SSP_COMPREF_REFERENCE_OFFSET 0

20
arch/arm/include/asm/arch-mxs/sys_proto.h
View File

@ -31,10 +31,16 @@ int mxs_wait_mask_clr(struct mxs_register_32 *reg,
uint32_t mask,
unsigned int timeout);
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int));
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_MX23)
#include <asm/arch/iomux-mx23.h>
#elif defined(CONFIG_MX28)
#include <asm/arch/iomux-mx28.h>
#endif
void mxs_common_spl_init(const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size);
#endif
@ -46,6 +52,17 @@ struct mxs_pair {
};
static const struct mxs_pair mxs_boot_modes[] = {
#if defined(CONFIG_MX23)
{ 0x00, 0x0f, "USB" },
{ 0x01, 0x1f, "I2C, master" },
{ 0x02, 0x1f, "SSP SPI #1, master, NOR" },
{ 0x03, 0x1f, "SSP SPI #2, master, NOR" },
{ 0x04, 0x1f, "NAND" },
{ 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
{ 0x09, 0x1f, "SSP SD/MMC #0" },
{ 0x0a, 0x1f, "SSP SD/MMC #1" },
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
#elif defined(CONFIG_MX28)
{ 0x00, 0x0f, "USB #0" },
{ 0x01, 0x1f, "I2C #0, master, 3V3" },
{ 0x11, 0x1f, "I2C #0, master, 1V8" },
@ -62,6 +79,7 @@ static const struct mxs_pair mxs_boot_modes[] = {
{ 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" },
{ 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" },
{ 0x00, 0x00, "Reserved/Unknown/Wrong" },
#endif
};
struct mxs_spl_data {

8
board/bluegiga/apx4devkit/apx4devkit.c
View File

@ -43,12 +43,12 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000);
mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000);
mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
return 0;
}
@ -69,7 +69,7 @@ int board_init(void)
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bis)
{
return mxsmmc_initialize(bis, 0, NULL);
return mxsmmc_initialize(bis, 0, NULL, NULL);
}
#endif

10
board/denx/m28evk/m28evk.c
View File

@ -43,14 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000);
mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000);
mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
/* SSP2 clock at 160MHz */
mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
#ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
@ -93,7 +93,7 @@ int board_mmc_init(bd_t *bis)
/* Turn on the power to the card. */
gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
return mxsmmc_initialize(bis, 0, m28_mmc_wp);
return mxsmmc_initialize(bis, 0, m28_mmc_wp, NULL);
}
#endif

120
board/esg/ima3-mx53/imximage.cfg
View File

@ -1,50 +1,52 @@
#
# (C) Copyright 2012
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
/*
* (C) Copyright 2012
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM nor
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
# IOMUX for RAM only
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* IOMUX for RAM only */
DATA 4 0x53fa8554 0x300020
DATA 4 0x53fa8560 0x300020
DATA 4 0x53fa8594 0x300020
@ -72,37 +74,47 @@ DATA 4 0x53fa86fc 0x0
DATA 4 0x53fa86f4 0x0
DATA 4 0x53fa8714 0x0
DATA 4 0x53fa8724 0x4000000
#
# DDR RAM
/* DDR RAM */
DATA 4 0x63fd9088 0x40404040
DATA 4 0x63fd9090 0x40404040
DATA 4 0x63fd907C 0x01420143
DATA 4 0x63fd9080 0x01450146
DATA 4 0x63fd9018 0x00111740
DATA 4 0x63fd9000 0x84190000
# esdcfgX
/* esdcfgX */
DATA 4 0x63fd900C 0x9f5152e3
DATA 4 0x63fd9010 0xb68e8a63
DATA 4 0x63fd9014 0x01ff00db
# Read/Write command delay
/* Read/Write command delay */
DATA 4 0x63fd902c 0x000026d2
# Out of reset delays
/* Out of reset delays */
DATA 4 0x63fd9030 0x00ff0e21
# ESDCTL ODT timing control
/* ESDCTL ODT timing control */
DATA 4 0x63fd9008 0x12273030
# ESDCTL power down control
/* ESDCTL power down control */
DATA 4 0x63fd9004 0x0002002d
# Set registers in DDR memory chips
/* Set registers in DDR memory chips */
DATA 4 0x63fd901c 0x00008032
DATA 4 0x63fd901c 0x00008033
DATA 4 0x63fd901c 0x00028031
DATA 4 0x63fd901c 0x052080b0
DATA 4 0x63fd901c 0x04008040
# ESDCTL refresh control
/* ESDCTL refresh control */
DATA 4 0x63fd9020 0x00005800
# PHY ZQ HW control
/* PHY ZQ HW control */
DATA 4 0x63fd9040 0x05380003
# PHY ODT control
/* PHY ODT control */
DATA 4 0x63fd9058 0x00022222
# start DDR3
/* start DDR3 */
DATA 4 0x63fd901c 0x00000000

88
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
View File

@ -1,47 +1,51 @@
# Copyright (C) 2011 Freescale Semiconductor, Inc.
# Jason Liu <r64343@freescale.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@ -154,7 +158,7 @@ DATA 4 0x021b48b8 0x00000800
DATA 4 0x021b001c 0x00000000
DATA 4 0x021b0404 0x00011006
# set the default clock gate to save power
/* set the default clock gate to save power */
DATA 4 0x020c4068 0x00C03F3F
DATA 4 0x020c406c 0x0030FC03
DATA 4 0x020c4070 0x0FFFC000
@ -163,8 +167,8 @@ DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
# enable AXI cache for VDOA/VPU/IPU
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F

47
board/freescale/mx23evk/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
ifndef CONFIG_SPL_BUILD
COBJS := mx23evk.o
else
COBJS := spl_boot.o
endif
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

83
board/freescale/mx23evk/mx23evk.c Normal file
View File

@ -0,0 +1,83 @@
/*
* Freescale MX23EVK board
*
* (C) Copyright 2013 O.S. Systems Software LTDA.
*
* Author: Otavio Salvador <otavio@ossystems.com.br>
*
* Based on m28evk.c:
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/gpio.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx23.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Functions
*/
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mxs_set_ioclk(MXC_IOCLK0, 480000);
/* SSP0 clock at 96MHz */
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
return 0;
}
int dram_init(void)
{
return mxs_dram_init();
}
int board_init(void)
{
/* Adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
#ifdef CONFIG_CMD_MMC
static int mx23evk_mmc_wp(int id)
{
if (id != 0) {
printf("MXS MMC: Invalid card selected (card id = %d)\n", id);
return 1;
}
return gpio_get_value(MX23_PAD_PWM4__GPIO_1_30);
}
int board_mmc_init(bd_t *bis)
{
/* Configure WP as input */
gpio_direction_input(MX23_PAD_PWM4__GPIO_1_30);
/* Configure MMC0 Power Enable */
gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
return mxsmmc_initialize(bis, 0, mx23evk_mmc_wp, NULL);
}
#endif

104
board/freescale/mx23evk/spl_boot.c Normal file
View File

@ -0,0 +1,104 @@
/*
* Freescale MX23EVK Boot setup
*
* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
* on behalf of DENX Software Engineering GmbH
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx23.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#define MUX_CONFIG_SSP1 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP)
const iomux_cfg_t iomux_setup[] = {
/* DUART */
MX23_PAD_PWM0__DUART_RX,
MX23_PAD_PWM1__DUART_TX,
/* EMI */
MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
/* MMC 0 */
MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP1,
MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP1,
MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP1,
MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP1,
MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP1,
MX23_PAD_SSP1_DETECT__SSP1_DETECT | MUX_CONFIG_SSP1,
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
MX23_PAD_SSP1_SCK__SSP1_SCK |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* Write Protect Pin */
MX23_PAD_PWM4__GPIO_1_30 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
/* Slot Power Enable */
MX23_PAD_PWM3__GPIO_1_29 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
};
void board_init_ll(void)
{
mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
}

77
board/freescale/mx25pdk/imximage.cfg
View File

@ -1,46 +1,49 @@
#
# (C) Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
# EIM config-CS5 init -- CPLD
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* EIM config-CS5 init -- CPLD */
DATA 4 0xB8002050 0x0000D843
DATA 4 0xB8002054 0x22252521
DATA 4 0xB8002058 0x22220A00
# DDR2 init
/* DDR2 init */
DATA 4 0xB8001004 0x0076E83A
DATA 4 0xB8001010 0x00000204
DATA 4 0xB8001000 0x92210000
@ -67,7 +70,7 @@ DATA 4 0x43FAC454 0x00001000
DATA 4 0x53F80008 0x20034000
# Enable the clocks
/* Enable the clocks */
DATA 4 0x53f8000c 0x1fffffff
DATA 4 0x53f80010 0xffffffff
DATA 4 0x53f80014 0xfdfff

10
board/freescale/mx28evk/mx28evk.c
View File

@ -43,14 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000);
mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000);
mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
/* SSP2 clock at 160MHz */
mx28_set_sspclk(MXC_SSPCLK2, 160000, 0);
mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
#ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_SSP2_SS1__USB1_OVERCURRENT);
@ -94,7 +94,7 @@ int board_mmc_init(bd_t *bis)
/* Configure MMC0 Power Enable */
gpio_direction_output(MX28_PAD_PWM3__GPIO_3_28, 0);
return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp);
return mxsmmc_initialize(bis, 0, mx28evk_mmc_wp, NULL);
}
#endif

114
board/freescale/mx51evk/imximage.cfg
View File

@ -1,46 +1,50 @@
#
# (C Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* (C Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
# Setting IOMUXC
/* Setting IOMUXC */
DATA 4 0x73FA88a0 0x200
DATA 4 0x73FA850c 0x20c5
DATA 4 0x73FA8510 0x20c5
@ -65,22 +69,24 @@ DATA 4 0x73FA88a4 0x6
DATA 4 0x73FA88ac 0x6
DATA 4 0x73FA88b8 0x6
# Setting DDR for micron
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
# CAS=3 BL=4
# ESDCTL_ESDCTL0
/*
* Setting DDR for micron
* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
* CAS=3 BL=4
*/
/* ESDCTL_ESDCTL0 */
DATA 4 0x83FD9000 0x82a20000
# ESDCTL_ESDCTL1
/* ESDCTL_ESDCTL1 */
DATA 4 0x83FD9008 0x82a20000
# ESDCTL_ESDMISC
/* ESDCTL_ESDMISC */
DATA 4 0x83FD9010 0x000ad0d0
# ESDCTL_ESDCFG0
/* ESDCTL_ESDCFG0 */
DATA 4 0x83FD9004 0x333574aa
# ESDCTL_ESDCFG1
/* ESDCTL_ESDCFG1 */
DATA 4 0x83FD900C 0x333574aa
# Init DRAM on CS0
# ESDCTL_ESDSCR
/* Init DRAM on CS0 */
/* ESDCTL_ESDSCR */
DATA 4 0x83FD9014 0x04008008
DATA 4 0x83FD9014 0x0000801a
DATA 4 0x83FD9014 0x0000801b
@ -94,7 +100,7 @@ DATA 4 0x83FD9014 0x03808019
DATA 4 0x83FD9014 0x00408019
DATA 4 0x83FD9014 0x00008000
# Init DRAM on CS1
/* Init DRAM on CS1 */
DATA 4 0x83FD9014 0x0400800c
DATA 4 0x83FD9014 0x0000801e
DATA 4 0x83FD9014 0x0000801f
@ -108,12 +114,12 @@ DATA 4 0x83FD9014 0x0380801d
DATA 4 0x83FD9014 0x0040801d
DATA 4 0x83FD9014 0x00008004
# Write to CTL0
/* Write to CTL0 */
DATA 4 0x83FD9000 0xb2a20000
# Write to CTL1
/* Write to CTL1 */
DATA 4 0x83FD9008 0xb2a20000
# ESDMISC
/* ESDMISC */
DATA 4 0x83FD9010 0x000ad6d0
#ESDCTL_ESDCDLYGD
/* ESDCTL_ESDCDLYGD */
DATA 4 0x83FD9034 0x90000000
DATA 4 0x83FD9014 0x00000000

83
board/freescale/mx53ard/imximage_dd3.cfg
View File

@ -1,48 +1,51 @@
#
# (C) Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000

86
board/freescale/mx53evk/imximage.cfg
View File

@ -1,50 +1,52 @@
#
# (C Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
/*
* (C Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
# Setting IOMUXC
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Setting IOMUXC */
DATA 4 0x53fa8554 0x00200000
DATA 4 0x53fa8560 0x00200000
DATA 4 0x53fa8594 0x00200000

83
board/freescale/mx53loco/imximage.cfg
View File

@ -1,48 +1,51 @@
# Copyright (C) 2011 Freescale Semiconductor, Inc.
# Jason Liu <r64343@freescale.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000

83
board/freescale/mx53smd/imximage.cfg
View File

@ -1,48 +1,51 @@
#
# (C) Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x53fa8554 0x00300000
DATA 4 0x53fa8558 0x00300040
DATA 4 0x53fa8560 0x00300000

86
board/freescale/mx6qarm2/imximage.cfg
View File

@ -1,47 +1,51 @@
# Copyright (C) 2011 Freescale Semiconductor, Inc.
# Jason Liu <r64343@freescale.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc.
* Jason Liu <r64343@freescale.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e05a8 0x00000030
DATA 4 0x020e05b0 0x00000030
DATA 4 0x020e0524 0x00000030
@ -166,8 +170,8 @@ DATA 4 0x020c4078 0x00FFF300
DATA 4 0x020c407c 0x0F0000C3
DATA 4 0x020c4080 0x000003FF
# enable AXI cache for VDOA/VPU/IPU
/* enable AXI cache for VDOA/VPU/IPU */
DATA 4 0x020e0010 0xF00000CF
# set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
DATA 4 0x020e0018 0x007F007F
DATA 4 0x020e001c 0x007F007F

82
board/freescale/mx6qsabreauto/imximage.cfg
View File

@ -1,46 +1,50 @@
# Copyright (C) 2012 Freescale Semiconductor, Inc.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# image version
/*
* Copyright (C) 2012 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/* image version */
IMAGE_VERSION 2
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM sd
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
DATA 4 0x020e05a8 0x00000028
DATA 4 0x020e05b0 0x00000028
DATA 4 0x020e0524 0x00000028
@ -126,7 +130,7 @@ DATA 4 0x021b0020 0x00005800
DATA 4 0x021b0818 0x00000007
DATA 4 0x021b4818 0x00000007
# Calibration values based on ARD and 528MHz
/* Calibration values based on ARD and 528MHz */
DATA 4 0x021b083c 0x434B0358
DATA 4 0x021b0840 0x033D033C
DATA 4 0x021b483c 0x03520362

24
board/freescale/mx6qsabrelite/mx6qsabrelite.c
View File

@ -33,6 +33,7 @@
#include <asm/imx-common/boot_mode.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <malloc.h>
#include <micrel.h>
#include <miiphy.h>
#include <netdev.h>
@ -338,14 +339,31 @@ int board_phy_config(struct phy_device *phydev)
int board_eth_init(bd_t *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
setup_iomux_enet();
ret = cpu_eth_init(bis);
if (ret)
#ifdef CONFIG_FEC_MXC
bus = fec_get_miibus(base, -1);
if (!bus)
return 0;
/* scan phy 4,5,6,7 */
phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
free(bus);
return 0;
}
printf("using phy at %d\n", phydev->addr);
ret = fec_probe(bis, -1, base, bus, phydev);
if (ret) {
printf("FEC MXC: %s:failed\n", __func__);
free(phydev);
free(bus);
}
#endif
return 0;
}

132
board/genesi/mx51_efikamx/imximage_mx.cfg
View File

@ -1,52 +1,58 @@
#
# Copyright (C) 2009 Pegatron Corporation
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
# Copyright (C) 2009-2012 Genesi USA, Inc.
#
# BASED ON: imx51evk
#
# (C) Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
/*
* Copyright (C) 2009 Pegatron Corporation
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
* Copyright (C) 2009-2012 Genesi USA, Inc.
*
* BASED ON: imx51evk
*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
# Essential GPIO settings to be done as early as possible
# PCBIDn pad settings are all the defaults except #2 which needs HVE off
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/*
* Essential GPIO settings to be done as early as possible
* PCBIDn pad settings are all the defaults except #2 which needs HVE off
*/
DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16
DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17
DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11
@ -55,7 +61,7 @@ DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13
DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14
DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
# DDR bus IOMUX PAD settings
/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa850c 0x20c5 # SDODT1
DATA 4 0x73fa8510 0x20c5 # SDODT0
DATA 4 0x73fa84ac 0xc5 # SDWE
@ -72,22 +78,24 @@ DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1
DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2
DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
# Setting DDR for micron
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
# CAS=3 BL=4
# ESDCTL_ESDCTL0
/*
* Setting DDR for micron
* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
* CAS=3 BL=4
*/
/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
# ESDCTL_ESDCTL1
/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
# ESDCTL_ESDMISC
/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
# ESDCTL_ESDCFG0
/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x3f3574aa
# ESDCTL_ESDCFG1
/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x3f3574aa
# Init DRAM on CS0
# ESDCTL_ESDSCR
/* Init DRAM on CS0 */
/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
@ -101,7 +109,7 @@ DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000
# Init DRAM on CS1
/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
@ -115,12 +123,12 @@ DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0040801d
DATA 4 0x83fd9014 0x00008004
# Write to CTL0
/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
# Write to CTL1
/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
# ESDMISC
/* ESDMISC */
DATA 4 0x83fd9010 0x000ad6d0
#ESDCTL_ESDCDLYGD
/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000

126
board/genesi/mx51_efikamx/imximage_sb.cfg
View File

@ -1,51 +1,55 @@
#
# Copyright (C) 2009 Pegatron Corporation
# Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
# Copyright (C) 2009-2012 Genesi USA, Inc.
#
# BASED ON: imx51evk
#
# (C) Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
/*
* Copyright (C) 2009 Pegatron Corporation
* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
* Copyright (C) 2009-2012 Genesi USA, Inc.
*
* BASED ON: imx51evk
*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
# Boot Device : one of
# spi, sd (the board has no nand neither onenand)
/*
* Boot Device : one of
* spi, sd (the board has no nand neither onenand)
*/
BOOT_FROM spi
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
# DDR bus IOMUX PAD settings
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
DATA 4 0x73fa850c 0x20c5 # SDODT1
DATA 4 0x73fa8510 0x20c5 # SDODT0
@ -62,22 +66,24 @@ DATA 4 0x73fa84b4 0xe5 # SDCKE1
DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
# Setting DDR for micron
# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
# CAS=3 BL=4
# ESDCTL_ESDCTL0
/*
* Setting DDR for micron
* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
* CAS=3 BL=4
*/
/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
# ESDCTL_ESDCTL1
/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
# ESDCTL_ESDMISC
/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
# ESDCTL_ESDCFG0
/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x333574aa
# ESDCTL_ESDCFG1
/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x333574aa
# Init DRAM on CS0
# ESDCTL_ESDSCR
/* Init DRAM on CS0 */
/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
@ -91,7 +97,7 @@ DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000
# Init DRAM on CS1
/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
@ -105,12 +111,12 @@ DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0042801d
DATA 4 0x83fd9014 0x00008004
# Write to CTL0
/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
# Write to CTL1
/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
# ESDMISC
/* ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
#ESDCTL_ESDCDLYGD
/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000

47
board/olimex/mx23_olinuxino/Makefile Normal file
View File

@ -0,0 +1,47 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
ifndef CONFIG_SPL_BUILD
COBJS := mx23_olinuxino.o
else
COBJS := spl_boot.o
endif
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

71
board/olimex/mx23_olinuxino/mx23_olinuxino.c Normal file
View File

@ -0,0 +1,71 @@
/*
* Olimex MX23 Olinuxino board
*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx23.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Functions
*/
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mxs_set_ioclk(MXC_IOCLK0, 480000);
/* SSP0 clock at 96MHz */
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
return 0;
}
int dram_init(void)
{
return mxs_dram_init();
}
#ifdef CONFIG_CMD_MMC
static int mx23_olx_mmc_cd(int id)
{
return 1; /* Card always present */
}
int board_mmc_init(bd_t *bis)
{
return mxsmmc_initialize(bis, 0, NULL, mx23_olx_mmc_cd);
}
#endif
int board_init(void)
{
/* Adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}

99
board/olimex/mx23_olinuxino/spl_boot.c Normal file
View File

@ -0,0 +1,99 @@
/*
* Olimex MX23 Olinuxino Boot setup
*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx23.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_16MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
const iomux_cfg_t iomux_setup[] = {
/* DUART */
MX23_PAD_PWM0__DUART_RX,
MX23_PAD_PWM1__DUART_TX,
/* EMI */
MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
/* MMC 0 */
MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
};
void board_init_ll(void)
{
mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup));
}

10
board/schulercontrol/sc_sps_1/sc_sps_1.c
View File

@ -43,14 +43,14 @@ DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK0, 480000);
mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */
mx28_set_ioclk(MXC_IOCLK1, 480000);
mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP0 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK0, 96000, 0);
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
/* SSP2 clock at 96MHz */
mx28_set_sspclk(MXC_SSPCLK2, 96000, 0);
mxs_set_sspclk(MXC_SSPCLK2, 96000, 0);
#ifdef CONFIG_CMD_USB
mxs_iomux_setup_pad(MX28_PAD_AUART1_CTS__USB0_OVERCURRENT);
@ -78,7 +78,7 @@ int dram_init(void)
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bis)
{
return mxsmmc_initialize(bis, 0, NULL);
return mxsmmc_initialize(bis, 0, NULL, NULL);
}
#endif

291
board/ttcontrol/vision2/imximage_hynix.cfg
View File

@ -1,209 +1,228 @@
#
# (C) Copyright 2009
# Stefano Babic DENX Software Engineering sbabic@denx.de.
#
# (C) Copyright 2010
# Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not write to the Free Software
# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
# MA 02110-1301 USA
#
# Refer docs/README.imxmage for more details about how-to configure
# and create imximage boot image
#
# The syntax is taken as close as possible with the kwbimage
# Boot Device : one of
# spi, nand, onenand, sd
/*
* (C) Copyright 2009
* Stefano Babic DENX Software Engineering sbabic@denx.de.
*
* (C) Copyright 2010
* Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not write to the Free Software
* Foundation Inc. 51 Franklin Street Fifth Floor Boston,
* MA 02110-1301 USA
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
/*
* Boot Device : one of
* spi, nand, onenand, sd
*/
BOOT_FROM spi
# Device Configuration Data (DCD)
#
# Each entry must have the format:
# Addr-type Address Value
#
# where:
# Addr-type register length (1,2 or 4 bytes)
# Address absolute address of the register
# value value to be stored in the register
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
#######################
### Disable WDOG ###
#######################
/*
* #######################
* ### Disable WDOG ###
* #######################
*/
DATA 2 0x73f98000 0x30
#######################
### SET DDR Clk ###
#######################
# CCM: CBMCR - ddr_clk_sel: axi_b (133MHz)
/*
* #######################
* ### SET DDR Clk ###
* #######################
*/
/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
DATA 4 0x73FD4018 0x000024C0
# DOUBLE SPI CLK (13MHz->26 MHz Clock)
/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
DATA 4 0x73FD4038 0x2010241
#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8600 0x00000107
#IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8604 0x00000107
#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8608 0x00000187
#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa860c 0x00000187
#IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST
/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
DATA 4 0x73fa8614 0x00000107
#IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2)
/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
DATA 4 0x73fa86a8 0x00000187
#######################
### Settings IOMUXC ###
#######################
# DDR IOMUX configuration
# Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
# IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
/*
* #######################
* ### Settings IOMUXC ###
* #######################
*/
/*
* DDR IOMUX configuration
* Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
*/
DATA 4 0x73fa84b8 0x000000e7
# PVTC MAX (at GPC, PGR reg)
#DATA 4 0x73FD8004 0x1fc00000
/* PVTC MAX (at GPC, PGR reg) */
/* DATA 4 0x73FD8004 0x1fc00000 */
#DQM0 DS high slew rate slow
/* DQM0 DS high slew rate slow */
DATA 4 0x73fa84d4 0x000000e4
#DQM1 DS high slew rate slow
/* DQM1 DS high slew rate slow */
DATA 4 0x73fa84d8 0x000000e4
#DQM2 DS high slew rate slow
/* DQM2 DS high slew rate slow */
DATA 4 0x73fa84dc 0x000000e4
#DQM3 DS high slew rate slow
/* DQM3 DS high slew rate slow */
DATA 4 0x73fa84e0 0x000000e4
#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
DATA 4 0x73fa84bc 0x000000c4
#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
DATA 4 0x73fa84c0 0x000000c4
#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
DATA 4 0x73fa84c4 0x000000c4
#IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow
/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
DATA 4 0x73fa84c8 0x000000c4
#DRAM_DATA B0
/* DRAM_DATA B0 */
DATA 4 0x73fa88a4 0x00000004
#DRAM_DATA B1
/* DRAM_DATA B1 */
DATA 4 0x73fa88ac 0x00000004
#DRAM_DATA B2
/* DRAM_DATA B2 */
DATA 4 0x73fa88b8 0x00000004
#DRAM_DATA B3
/* DRAM_DATA B3 */
DATA 4 0x73fa882c 0x00000004
#DRAM_DATA B0 slew rate
/* DRAM_DATA B0 slew rate */
DATA 4 0x73fa8878 0x00000000
#DRAM_DATA B1 slew rate
/* DRAM_DATA B1 slew rate */
DATA 4 0x73fa8880 0x00000000
#DRAM_DATA B2 slew rate
/* DRAM_DATA B2 slew rate */
DATA 4 0x73fa888c 0x00000000
#DRAM_DATA B3 slew rate
/* DRAM_DATA B3 slew rate */
DATA 4 0x73fa889c 0x00000000
#######################
### Configure SDRAM ###
#######################
/*
* #######################
* ### Configure SDRAM ###
* #######################
*/
# Configure CS0
#######################
/* Configure CS0 */
/* ####################### */
# ESDCTL0: Enable controller
/* ESDCTL0: Enable controller */
DATA 4 0x83fd9000 0x83220000
# Init DRAM on CS0
# ESDSCR: Precharge command
/* Init DRAM on CS0 /
/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x04008008
# ESDSCR: Refresh command
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
# ESDSCR: Refresh command
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008010
# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x00338018
# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801a
# ESDSCR
/* ESDSCR */
DATA 4 0x83fd9014 0x00008000
# ESDSCR: EMR with full Drive strength
#DATA 4 0x83fd9014 0x0000801a
/* ESDSCR: EMR with full Drive strength */
/* DATA 4 0x83fd9014 0x0000801a */
# ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8
/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9000 0xC3220000
# ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
#DATA 4 0x83fd9004 0xC33574AA
#micron mDDR
# ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
#DATA 4 0x83FD9004 0x101564a8
#hynix mDDR
# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
/*
* ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
* DATA 4 0x83fd9004 0xC33574AA
*/
/*
* micron mDDR
* ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
* DATA 4 0x83FD9004 0x101564a8
*/
/*
* hynix mDDR
* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
*/
DATA 4 0x83FD9004 0x704564a8
# ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2
/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
DATA 4 0x83fd9010 0x000a1700
# Configure CS1
#######################
/* Configure CS1 */
/* ####################### */
# ESDCTL1: Enable controller
/* ESDCTL1: Enable controller */
DATA 4 0x83fd9008 0x83220000
# Init DRAM on CS1
# ESDSCR: Precharge command
/* Init DRAM on CS1 */
/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x0400800c
# ESDSCR: Refresh command
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
# ESDSCR: Refresh command
/* ESDSCR: Refresh command */
DATA 4 0x83fd9014 0x00008014
# ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8)
/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
DATA 4 0x83fd9014 0x0033801c
# ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51)
/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
DATA 4 0x83fd9014 0x0020801e
# ESDSCR
/* ESDSCR */
DATA 4 0x83fd9014 0x00008004
# ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8
/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
DATA 4 0x83fd9008 0xC3220000
# ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
# tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
#DATA 4 0x83fd900c 0xC33574AA
#micron mDDR
# ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
#DATA 4 0x83FD900C 0x101564a8
#hynix mDDR
# ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
# tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
/*
* ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
* DATA 4 0x83fd900c 0xC33574AA
*/
/*
* micron mDDR
* ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
* DATA 4 0x83FD900C 0x101564a8
*/
/*
* hynix mDDR
* ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
* tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
*/
DATA 4 0x83FD900C 0x704564a8
# ESDSCR (mDRAM configuration finished)
/* ESDSCR (mDRAM configuration finished) */
DATA 4 0x83FD9014 0x00000004
# ESDSCR - clear "configuration request" bit
/* ESDSCR - clear "configuration request" bit */
DATA 4 0x83fd9014 0x00000000

2
board/woodburn/imximage.cfg
View File

@ -1,4 +1,4 @@
BOOT_FROM sd
# DDR2 init
/* DDR2 init */
DATA 4 0xB8001010 0x00000304

3
board/woodburn/woodburn.c
View File

@ -241,9 +241,10 @@ int board_mmc_init(bd_t *bis)
mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1);
gpio_direction_input(GPIO_MMC_CD);
/* MMC Write Protection on GPIO1_8 */
mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5);
mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1);
gpio_direction_output(GPIO_MMC_WP, 0);
gpio_direction_input(GPIO_MMC_WP);
esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);

2
boards.cfg
View File

@ -191,7 +191,9 @@ tx25 arm arm926ejs tx25 karo
zmx25 arm arm926ejs zmx25 syteco mx25
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
mx23_olinuxino arm arm926ejs mx23_olinuxino olimex mxs mx23_olinuxino
apx4devkit arm arm926ejs apx4devkit bluegiga mxs apx4devkit
mx23evk arm arm926ejs mx23evk freescale mxs mx23evk
m28evk arm arm926ejs m28evk denx mxs m28evk
mx28evk arm arm926ejs mx28evk freescale mxs mx28evk
sc_sps_1 arm arm926ejs sc_sps_1 schulercontrol mxs

27
doc/README.fec_mxc Normal file
View File

@ -0,0 +1,27 @@
U-boot config options used in fec_mxc.c
CONFIG_FEC_MXC
Selects fec_mxc.c to be compiled into u-boot.
CONFIG_MII
Must be defined if CONFIG_FEC_MXC is defined.
CONFIG_FEC_XCV_TYPE
Defaults to MII100 for 100 Base-tx.
RGMII selects 1000 Base-tx reduced pin count interface.
RMII selects 100 Base-tx reduced pin count interface.
CONFIG_FEC_MXC_SWAP_PACKET
Forced on iff MX28.
Swaps the bytes order of all words(4 byte units) in the packet.
This should not be specified by a board file. It is cpu specific.
CONFIG_PHYLIB
fec_mxc supports PHYLIB and should be used for new boards.
CONFIG_FEC_MXC_NO_ANEG
Relevant only if PHYLIB not used. Skips auto-negotiation restart.
CONFIG_FEC_MXC_PHYADDR
Optional, selects the exact phy address that should be connected
and function fecmxc_initialize will try to initialize it.

10
drivers/dma/apbh_dma.c
View File

@ -223,13 +223,19 @@ static int mxs_dma_reset(int channel)
struct mxs_apbh_regs *apbh_regs =
(struct mxs_apbh_regs *)MXS_APBH_BASE;
int ret;
#if defined(CONFIG_MX23)
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
#elif defined(CONFIG_MX28)
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
#endif
ret = mxs_dma_validate_chan(channel);
if (ret)
return ret;
writel(1 << (channel + APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET),
&apbh_regs->hw_apbh_channel_ctrl_set);
writel(1 << (channel + offset), setreg);
return 0;
}

102
drivers/mmc/mxsmmc.c
View File

@ -47,16 +47,31 @@
struct mxsmmc_priv {
int id;
struct mxs_ssp_regs *regs;
uint32_t clkseq_bypass;
uint32_t *clkctrl_ssp;
uint32_t buswidth;
int (*mmc_is_wp)(int);
int (*mmc_cd)(int);
struct mxs_dma_desc *desc;
};
#if defined(CONFIG_MX23)
static const unsigned int mxsmmc_id_offset = 1;
#elif defined(CONFIG_MX28)
static const unsigned int mxsmmc_id_offset = 0;
#endif
#define MXSMMC_MAX_TIMEOUT 10000
#define MXSMMC_SMALL_TRANSFER 512
static int mxsmmc_cd(struct mxsmmc_priv *priv)
{
struct mxs_ssp_regs *ssp_regs = priv->regs;
if (priv->mmc_cd)
return priv->mmc_cd(priv->id);
return !(readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT);
}
static int mxsmmc_send_cmd_pio(struct mxsmmc_priv *priv, struct mmc_data *data)
{
struct mxs_ssp_regs *ssp_regs = priv->regs;
@ -122,7 +137,7 @@ static int mxsmmc_send_cmd_dma(struct mxsmmc_priv *priv, struct mmc_data *data)
priv->desc->cmd.data |= MXS_DMA_DESC_IRQ | MXS_DMA_DESC_DEC_SEM |
(data_count << MXS_DMA_DESC_BYTES_OFFSET);
dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id;
dmach = MXS_DMA_CHANNEL_AHB_APBH_SSP0 + priv->id + mxsmmc_id_offset;
mxs_dma_desc_append(dmach, priv->desc);
if (mxs_dma_go(dmach)) {
bounce_buffer_stop(&bbstate);
@ -168,7 +183,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
}
/* See if card is present */
if (readl(&ssp_regs->hw_ssp_status) & SSP_STATUS_CARD_DETECT) {
if (!mxsmmc_cd(priv)) {
printf("MMC%d: No card detected!\n", mmc->block_dev.dev);
return NO_CARD_ERR;
}
@ -213,14 +228,25 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
}
ctrl0 |= SSP_CTRL0_DATA_XFER;
reg = data->blocksize * data->blocks;
#if defined(CONFIG_MX23)
ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK,
((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
((ffs(data->blocksize) - 1) <<
SSP_CMD0_BLOCK_SIZE_OFFSET));
#elif defined(CONFIG_MX28)
writel(reg, &ssp_regs->hw_ssp_xfer_size);
reg = ((data->blocks - 1) <<
SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) |
((ffs(data->blocksize) - 1) <<
SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET);
writel(reg, &ssp_regs->hw_ssp_block_size);
reg = data->blocksize * data->blocks;
writel(reg, &ssp_regs->hw_ssp_xfer_size);
#endif
}
/* Kick off the command */
@ -306,7 +332,7 @@ static void mxsmmc_set_ios(struct mmc *mmc)
/* Set the clock speed */
if (mmc->clock)
mx28_set_ssp_busclock(priv->id, mmc->clock / 1000);
mxs_set_ssp_busclock(priv->id, mmc->clock / 1000);
switch (mmc->bus_width) {
case 1:
@ -336,14 +362,20 @@ static int mxsmmc_init(struct mmc *mmc)
/* Reset SSP */
mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg);
/* 8 bits word length in MMC mode */
clrsetbits_le32(&ssp_regs->hw_ssp_ctrl1,
SSP_CTRL1_SSP_MODE_MASK | SSP_CTRL1_WORD_LENGTH_MASK |
SSP_CTRL1_DMA_ENABLE,
SSP_CTRL1_SSP_MODE_SD_MMC | SSP_CTRL1_WORD_LENGTH_EIGHT_BITS);
/* Reconfigure the SSP block for MMC operation */
writel(SSP_CTRL1_SSP_MODE_SD_MMC |
SSP_CTRL1_WORD_LENGTH_EIGHT_BITS |
SSP_CTRL1_DMA_ENABLE |
SSP_CTRL1_POLARITY |
SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
SSP_CTRL1_DATA_CRC_IRQ_EN |
SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
SSP_CTRL1_RESP_ERR_IRQ_EN,
&ssp_regs->hw_ssp_ctrl1_set);
/* Set initial bit clock 400 KHz */
mx28_set_ssp_busclock(priv->id, 400);
mxs_set_ssp_busclock(priv->id, 400);
/* Send initial 74 clock cycles (185 us @ 400 KHz)*/
writel(SSP_CMD0_CONT_CLKING_EN, &ssp_regs->hw_ssp_cmd0_set);
@ -353,13 +385,21 @@ static int mxsmmc_init(struct mmc *mmc)
return 0;
}
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int))
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct mmc *mmc = NULL;
struct mxsmmc_priv *priv = NULL;
int ret;
#if defined(CONFIG_MX23)
const unsigned int mxsmmc_max_id = 2;
const unsigned int mxsmmc_clk_id = 0;
#elif defined(CONFIG_MX28)
const unsigned int mxsmmc_max_id = 4;
const unsigned int mxsmmc_clk_id = id;
#endif
if (id >= mxsmmc_max_id)
return -ENODEV;
mmc = malloc(sizeof(struct mmc));
if (!mmc)
@ -378,34 +418,14 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
return -ENOMEM;
}
ret = mxs_dma_init_channel(id);
ret = mxs_dma_init_channel(id + mxsmmc_id_offset);
if (ret)
return ret;
priv->mmc_is_wp = wp;
priv->mmc_cd = cd;
priv->id = id;
switch (id) {
case 0:
priv->regs = (struct mxs_ssp_regs *)MXS_SSP0_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP0;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp0;
break;
case 1:
priv->regs = (struct mxs_ssp_regs *)MXS_SSP1_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP1;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp1;
break;
case 2:
priv->regs = (struct mxs_ssp_regs *)MXS_SSP2_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP2;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp2;
break;
case 3:
priv->regs = (struct mxs_ssp_regs *)MXS_SSP3_BASE;
priv->clkseq_bypass = CLKCTRL_CLKSEQ_BYPASS_SSP3;
priv->clkctrl_ssp = &clkctrl_regs->hw_clkctrl_ssp3;
break;
}
priv->regs = mxs_ssp_regs_by_bus(id);
sprintf(mmc->name, "MXS MMC");
mmc->send_cmd = mxsmmc_send_cmd;
@ -426,7 +446,7 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int))
* CLOCK_RATE could be any integer from 0 to 255.
*/
mmc->f_min = 400000;
mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + id) * 1000 / 2;
mmc->f_max = mxc_get_clock(MXC_SSP0_CLK + mxsmmc_clk_id) * 1000 / 2;
mmc->b_max = 0x20;
mmc_register(mmc);

168
drivers/net/fec_mxc.c
View File

@ -135,15 +135,15 @@ static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr,
return val;
}
static void fec_mii_setspeed(struct fec_priv *fec)
static void fec_mii_setspeed(struct ethernet_regs *eth)
{
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
*/
writel((((imx_get_fecclk() / 1000000) + 2) / 5) << 1,
&fec->eth->mii_speed);
debug("%s: mii_speed %08x\n", __func__, readl(&fec->eth->mii_speed));
&eth->mii_speed);
debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
}
static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr,
@ -392,21 +392,6 @@ static int fec_set_hwaddr(struct eth_device *dev)
return 0;
}
static void fec_eth_phy_config(struct eth_device *dev)
{
#ifdef CONFIG_PHYLIB
struct fec_priv *fec = (struct fec_priv *)dev->priv;
struct phy_device *phydev;
phydev = phy_connect(fec->bus, fec->phy_id, dev,
PHY_INTERFACE_MODE_RGMII);
if (phydev) {
fec->phydev = phydev;
phy_config(phydev);
}
#endif
}
/*
* Do initial configuration of the FEC registers
*/
@ -511,9 +496,7 @@ static int fec_open(struct eth_device *edev)
#endif
#ifdef CONFIG_PHYLIB
if (!fec->phydev)
fec_eth_phy_config(edev);
if (fec->phydev) {
{
/* Start up the PHY */
int ret = phy_startup(fec->phydev);
@ -523,8 +506,6 @@ static int fec_open(struct eth_device *edev)
return ret;
}
speed = fec->phydev->speed;
} else {
speed = _100BASET;
}
#else
miiphy_wait_aneg(edev);
@ -611,7 +592,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
fec_reg_setup(fec);
if (fec->xcv_type != SEVENWIRE)
fec_mii_setspeed(fec);
fec_mii_setspeed(fec->bus->priv);
/*
* Set Opcode/Pause Duration Register
@ -915,11 +896,21 @@ static int fec_recv(struct eth_device *dev)
return len;
}
static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
static void fec_set_dev_name(char *dest, int dev_id)
{
sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id);
}
#ifdef CONFIG_PHYLIB
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, struct phy_device *phydev)
#else
static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, int phy_id)
#endif
{
struct eth_device *edev;
struct fec_priv *fec;
struct mii_dev *bus;
unsigned char ethaddr[6];
uint32_t start;
int ret = 0;
@ -966,53 +957,25 @@ static int fec_probe(bd_t *bd, int dev_id, int phy_id, uint32_t base_addr)
}
fec_reg_setup(fec);
fec_mii_setspeed(fec);
if (dev_id == -1) {
sprintf(edev->name, "FEC");
fec->dev_id = 0;
} else {
sprintf(edev->name, "FEC%i", dev_id);
fec->dev_id = dev_id;
}
fec->phy_id = phy_id;
bus = mdio_alloc();
if (!bus) {
printf("mdio_alloc failed\n");
ret = -ENOMEM;
goto err3;
}
bus->read = fec_phy_read;
bus->write = fec_phy_write;
sprintf(bus->name, edev->name);
#ifdef CONFIG_MX28
/*
* The i.MX28 has two ethernet interfaces, but they are not equal.
* Only the first one can access the MDIO bus.
*/
bus->priv = (struct ethernet_regs *)MXS_ENET0_BASE;
#else
bus->priv = fec->eth;
#endif
ret = mdio_register(bus);
if (ret) {
printf("mdio_register failed\n");
free(bus);
ret = -ENOMEM;
goto err3;
}
fec_set_dev_name(edev->name, dev_id);
fec->dev_id = (dev_id == -1) ? 0 : dev_id;
fec->bus = bus;
fec_mii_setspeed(bus->priv);
#ifdef CONFIG_PHYLIB
fec->phydev = phydev;
phy_connect_dev(phydev, edev);
/* Configure phy */
phy_config(phydev);
#else
fec->phy_id = phy_id;
#endif
eth_register(edev);
if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) {
debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr);
memcpy(edev->enetaddr, ethaddr, 6);
}
/* Configure phy */
fec_eth_phy_config(edev);
return ret;
err3:
free(fec);
err2:
@ -1021,28 +984,81 @@ err1:
return ret;
}
#ifndef CONFIG_FEC_MXC_MULTI
int fecmxc_initialize(bd_t *bd)
struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id)
{
int lout = 1;
struct ethernet_regs *eth = (struct ethernet_regs *)base_addr;
struct mii_dev *bus;
int ret;
debug("eth_init: fec_probe(bd)\n");
lout = fec_probe(bd, -1, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
bus = mdio_alloc();
if (!bus) {
printf("mdio_alloc failed\n");
return NULL;
}
bus->read = fec_phy_read;
bus->write = fec_phy_write;
bus->priv = eth;
fec_set_dev_name(bus->name, dev_id);
return lout;
ret = mdio_register(bus);
if (ret) {
printf("mdio_register failed\n");
free(bus);
return NULL;
}
fec_mii_setspeed(eth);
return bus;
}
#endif
int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
{
int lout = 1;
uint32_t base_mii;
struct mii_dev *bus = NULL;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev = NULL;
#endif
int ret;
#ifdef CONFIG_MX28
/*
* The i.MX28 has two ethernet interfaces, but they are not equal.
* Only the first one can access the MDIO bus.
*/
base_mii = MXS_ENET0_BASE;
#else
base_mii = addr;
#endif
debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr);
lout = fec_probe(bd, dev_id, phy_id, addr);
return lout;
bus = fec_get_miibus(base_mii, dev_id);
if (!bus)
return -ENOMEM;
#ifdef CONFIG_PHYLIB
phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
free(bus);
return -ENOMEM;
}
ret = fec_probe(bd, dev_id, addr, bus, phydev);
#else
ret = fec_probe(bd, dev_id, addr, bus, phy_id);
#endif
if (ret) {
#ifdef CONFIG_PHYLIB
free(phydev);
#endif
free(bus);
}
return ret;
}
#ifdef CONFIG_FEC_MXC_PHYADDR
int fecmxc_initialize(bd_t *bd)
{
return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR,
IMX_FEC_BASE);
}
#endif
#ifndef CONFIG_PHYLIB
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int))
{

2
drivers/net/fec_mxc.h
View File

@ -271,11 +271,11 @@ struct fec_priv {
bd_t *bd;
uint8_t *tdb_ptr;
int dev_id;
int phy_id;
struct mii_dev *bus;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
#else
int phy_id;
int (*mii_postcall)(int);
#endif
};

128
drivers/net/phy/phy.c
View File

@ -31,6 +31,7 @@
#include <miiphy.h>
#include <phy.h>
#include <errno.h>
#include <linux/err.h>
/* Generic PHY support and helper functions */
@ -574,6 +575,61 @@ static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
return 0;
}
static struct phy_device *create_phy_by_mask(struct mii_dev *bus,
unsigned phy_mask, int devad, phy_interface_t interface)
{
u32 phy_id = 0xffffffff;
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
int r = get_phy_id(bus, addr, devad, &phy_id);
if (r < 0)
return ERR_PTR(r);
/* If the PHY ID is mostly f's, we didn't find anything */
if ((phy_id & 0x1fffffff) != 0x1fffffff)
return phy_device_create(bus, addr, phy_id, interface);
phy_mask &= ~(1 << addr);
}
return NULL;
}
static struct phy_device *search_for_existing_phy(struct mii_dev *bus,
unsigned phy_mask, phy_interface_t interface)
{
/* If we have one, return the existing device, with new interface */
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
if (bus->phymap[addr]) {
bus->phymap[addr]->interface = interface;
return bus->phymap[addr];
}
phy_mask &= ~(1 << addr);
}
return NULL;
}
static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus,
unsigned phy_mask, phy_interface_t interface)
{
int i;
struct phy_device *phydev;
phydev = search_for_existing_phy(bus, phy_mask, interface);
if (phydev)
return phydev;
/* Try Standard (ie Clause 22) access */
/* Otherwise we have to try Clause 45 */
for (i = 0; i < 5; i++) {
phydev = create_phy_by_mask(bus, phy_mask,
i ? i : MDIO_DEVAD_NONE, interface);
if (IS_ERR(phydev))
return NULL;
if (phydev)
return phydev;
}
printf("Phy not found\n");
return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface);
}
/**
* get_phy_device - reads the specified PHY device and returns its @phy_device struct
* @bus: the target MII bus
@ -585,38 +641,7 @@ static int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
static struct phy_device *get_phy_device(struct mii_dev *bus, int addr,
phy_interface_t interface)
{
u32 phy_id = 0x1fffffff;
int i;
int r;
/* If we have one, return the existing device, with new interface */
if (bus->phymap[addr]) {
bus->phymap[addr]->interface = interface;
return bus->phymap[addr];
}
/* Try Standard (ie Clause 22) access */
r = get_phy_id(bus, addr, MDIO_DEVAD_NONE, &phy_id);
if (r)
return NULL;
/* If the PHY ID is mostly f's, we didn't find anything */
if ((phy_id & 0x1fffffff) != 0x1fffffff)
return phy_device_create(bus, addr, phy_id, interface);
/* Otherwise we have to try Clause 45 */
for (i = 1; i < 5; i++) {
r = get_phy_id(bus, addr, i, &phy_id);
if (r)
return NULL;
/* If the phy_id is mostly Fs, there is no device there */
if ((phy_id & 0x1fffffff) != 0x1fffffff)
break;
}
return phy_device_create(bus, addr, phy_id, interface);
return get_phy_device_by_mask(bus, 1 << addr, interface);
}
int phy_reset(struct phy_device *phydev)
@ -689,38 +714,41 @@ int miiphy_reset(const char *devname, unsigned char addr)
return phy_reset(phydev);
}
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface)
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
phy_interface_t interface)
{
struct phy_device *phydev;
/* Reset the bus */
if (bus->reset)
bus->reset(bus);
/* Wait 15ms to make sure the PHY has come out of hard reset */
udelay(15000);
return get_phy_device_by_mask(bus, phy_mask, interface);
}
phydev = get_phy_device(bus, addr, interface);
if (!phydev) {
printf("Could not get PHY for %s:%d\n", bus->name, addr);
return NULL;
}
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev)
{
/* Soft Reset the PHY */
phy_reset(phydev);
if (phydev->dev)
if (phydev->dev) {
printf("%s:%d is connected to %s. Reconnecting to %s\n",
bus->name, addr, phydev->dev->name, dev->name);
phydev->bus->name, phydev->addr,
phydev->dev->name, dev->name);
}
phydev->dev = dev;
debug("%s connected to %s\n", dev->name, phydev->drv->name);
}
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev, phy_interface_t interface)
{
struct phy_device *phydev;
phydev = phy_find_by_mask(bus, 1 << addr, interface);
if (phydev)
phy_connect_dev(phydev, dev);
else
printf("Could not get PHY for %s: addr %d\n", bus->name, addr);
return phydev;
}

7
drivers/spi/mxs_spi.c
View File

@ -80,7 +80,6 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct mxs_spi_slave *mxs_slave;
uint32_t addr;
struct mxs_ssp_regs *ssp_regs;
int reg;
@ -96,13 +95,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
if (mxs_dma_init_channel(bus))
goto err_init;
addr = MXS_SSP0_BASE + (bus * MXS_SPI_PORT_OFFSET);
mxs_slave->slave.bus = bus;
mxs_slave->slave.cs = cs;
mxs_slave->max_khz = max_hz / 1000;
mxs_slave->mode = mode;
mxs_slave->regs = (struct mxs_ssp_regs *)addr;
mxs_slave->regs = mxs_ssp_regs_by_bus(bus);
ssp_regs = mxs_slave->regs;
reg = readl(&ssp_regs->hw_ssp_ctrl0);
@ -140,7 +137,7 @@ int spi_claim_bus(struct spi_slave *slave)
writel(0, &ssp_regs->hw_ssp_cmd0);
mx28_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
mxs_set_ssp_busclock(slave->bus, mxs_slave->max_khz);
return 0;
}

3
include/configs/m28evk.h
View File

@ -191,7 +191,6 @@
#ifdef CONFIG_CMD_NET
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_MULTI
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
#endif
@ -274,7 +273,7 @@
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_BOOTARGS "console=ttyAM0,115200n8 "
#define CONFIG_BOOTARGS "console=ttyAMA0,115200n8 "
#define CONFIG_BOOTCOMMAND "run bootcmd_net"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR

210
include/configs/mx23_olinuxino.h Normal file
View File

@ -0,0 +1,210 @@
/*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __MX23_OLINUXINO_CONFIG_H__
#define __MX23_OLINUXINO_CONFIG_H__
/*
* SoC configurations
*/
#define CONFIG_MX23 /* i.MX23 SoC */
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_MACH_TYPE 4105
#include <asm/arch/regs-base.h>
#define CONFIG_SYS_NO_FLASH
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
/*
* SPL
*/
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/*
* U-Boot Commands
*/
#include <config_cmd_default.h>
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MMC
/*
* Memory configurations
*/
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
/*
* U-Boot general configurations
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
/*
* Serial Driver
*/
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
/*
* MMC Driver
*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_GENERIC_MMC
#define CONFIG_MXS_MMC
#endif
/*
* APBH DMA
*/
#define CONFIG_APBH_DMA
/*
* Boot Linux
*/
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 3
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT
/*
* Environment
*/
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/*
* Extra Environments
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_sd_firmware_filename=u-boot.sd\0" \
"update_sd_firmware=" /* Update the SD firmware partition */ \
"if mmc rescan ; then " \
"if tftp ${update_sd_firmware_filename} ; then " \
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
"setexpr fw_sz ${fw_sz} + 1 ; " \
"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
"fi ; " \
"fi\0" \
"script=boot.scr\0" \
"uimage=uImage\0" \
"console=ttyAMA0\0" \
"fdt_file=imx23-olinuxino.dtb\0" \
"fdt_addr=0x41000000\0" \
"boot_fdt=try\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootm; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootm; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else " \
"echo ERR: Fail to boot from MMC; " \
"fi; " \
"fi; " \
"else exit; fi"
#endif /* __MX23_OLINUXINO_CONFIG_H__ */

202
include/configs/mx23evk.h Normal file
View File

@ -0,0 +1,202 @@
/*
* Freescale i.MX23 EVK board config
*
* Copyright (C) 2013 Otavio Salvador <otavio@ossystems.com.br>
* on behalf of O.S. Systems Software LTDA.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#ifndef __MX23EVK_CONFIG_H__
#define __MX23EVK_CONFIG_H__
/* SoC configurations */
#define CONFIG_MX23 /* i.MX23 SoC */
#include <asm/arch/regs-base.h>
#define CONFIG_MXS_GPIO /* GPIO control */
#define CONFIG_SYS_HZ 1000 /* Ticks per second */
#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_ARCH_MISC_INIT
/* SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs"
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds"
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
/* U-Boot Commands */
#include <config_cmd_default.h>
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_MMC
#define CONFIG_CMD_BOOTZ
/* Memory configurations */
#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
#define CONFIG_STACKSIZE (128 * 1024) /* 128 KB stack */
#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */
#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */
#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Point initial SP in SRAM so SPL can use it too. */
#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000
#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024)
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/*
* We need to sacrifice first 4 bytes of RAM here to avoid triggering some
* strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot
* binary. In case there was more of this mess, 0x100 bytes are skipped.
*/
#define CONFIG_SYS_TEXT_BASE 0x40000100
#define CONFIG_ENV_OVERWRITE
/* U-Boot general configurations */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O buffer size */
#define CONFIG_SYS_PBSIZE \
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
/* Print buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
#define CONFIG_AUTO_COMPLETE /* Command auto complete */
#define CONFIG_CMDLINE_EDITING /* Command history etc */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/* Serial Driver */
#define CONFIG_PL011_SERIAL
#define CONFIG_PL011_CLOCK 24000000
#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE }
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* DMA */
#define CONFIG_APBH_DMA
/* MMC Driver */
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_BOUNCE_BUFFER
#define CONFIG_MXS_MMC
#endif
/* Boot Linux */
#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTDELAY 1
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_OF_LIBFDT
/* Environment */
#define CONFIG_ENV_IS_IN_MMC
#ifdef CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_OFFSET (256 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
#define CONFIG_SYS_MMC_ENV_DEV 0
#endif
/* Extra Environments */
#define CONFIG_EXTRA_ENV_SETTINGS \
"update_sd_firmware_filename=u-boot.sd\0" \
"update_sd_firmware=" /* Update the SD firmware partition */ \
"if mmc rescan ; then " \
"if tftp ${update_sd_firmware_filename} ; then " \
"setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \
"setexpr fw_sz ${fw_sz} + 1 ; " \
"mmc write ${loadaddr} 0x800 ${fw_sz} ; " \
"fi ; " \
"fi\0" \
"script=boot.scr\0" \
"uimage=uImage\0" \
"console=ttyAMA0\0" \
"fdt_file=imx23-evk.dtb\0" \
"fdt_addr=0x41000000\0" \
"boot_fdt=try\0" \
"mmcdev=0\0" \
"mmcpart=2\0" \
"mmcroot=/dev/mmcblk0p3 rw rootwait\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \
"loadbootscript=" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"bootscript=echo Running bootscript from mmc ...; " \
"source\0" \
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
"mmcboot=echo Booting from mmc ...; " \
"run mmcargs; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if run loadfdt; then " \
"bootm ${loadaddr} - ${fdt_addr}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootm; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootm; " \
"fi;\0"
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loaduimage; then " \
"run mmcboot; " \
"else " \
"echo ERR: Fail to boot from MMC; " \
"fi; " \
"fi; " \
"else exit; fi"
#endif /* __MX23EVK_CONFIG_H__ */

1
include/configs/mx28evk.h
View File

@ -163,7 +163,6 @@
#define CONFIG_NET_MULTI
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_MULTI
#define CONFIG_MII
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_MX28_FEC_MAC_IN_OCOTP

2
include/configs/mx6qsabre_common.h
View File

@ -91,7 +91,7 @@
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
"mmcpart=1\0" \
"mmcpart=" __stringify(CONFIG_SYS_MMC_ENV_PART) "\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"mmcargs=setenv bootargs console=${console},${baudrate} " \
"root=${mmcroot}\0" \

12
include/configs/mx6qsabreauto.h
View File

@ -19,11 +19,23 @@
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
/* USB Configs */
#define CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_MX6
#define CONFIG_USB_STORAGE
#define CONFIG_USB_HOST_ETHER
#define CONFIG_USB_ETHER_ASIX
#define CONFIG_MXC_USB_PORT 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#include "mx6qsabre_common.h"
#define CONFIG_SYS_FSL_USDHC_NUM 2
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_SYS_MMC_ENV_PART 1 /* Boot partition 1 */
#endif
#endif /* __MX6QSABREAUTO_CONFIG_H */

1
include/configs/sc_sps_1.h
View File

@ -158,7 +158,6 @@
#ifdef CONFIG_CMD_NET
#define CONFIG_ETHPRIME "FEC0"
#define CONFIG_FEC_MXC
#define CONFIG_FEC_MXC_MULTI
#define CONFIG_MII
#define CONFIG_DISCOVER_PHY
#define CONFIG_FEC_XCV_TYPE RMII

7
include/netdev.h
View File

@ -215,9 +215,16 @@ struct mv88e61xx_config {
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
#endif /* CONFIG_MV88E61XX_SWITCH */
struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id);
#ifdef CONFIG_PHYLIB
struct phy_device;
int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr,
struct mii_dev *bus, struct phy_device *phydev);
#else
/*
* Allow FEC to fine-tune MII configuration on boards which require this.
*/
int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int));
#endif
#endif /* _NETDEV_H_ */

3
include/phy.h
View File

@ -199,6 +199,9 @@ static inline int is_10g_interface(phy_interface_t interface)
int phy_init(void);
int phy_reset(struct phy_device *phydev);
struct phy_device *phy_find_by_mask(struct mii_dev *bus, unsigned phy_mask,
phy_interface_t interface);
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev);
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface);

7
spl/Makefile
View File

@ -141,11 +141,8 @@ $(OBJTREE)/MLO.byteswap: $(obj)u-boot-spl.bin
$(OBJTREE)/tools/mkimage -T omapimage -n byteswap \
-a $(CONFIG_SPL_TEXT_BASE) -d $< $@
ifneq ($(CONFIG_IMX_CONFIG),)
$(OBJTREE)/SPL: $(obj)u-boot-spl.bin
$(OBJTREE)/tools/mkimage -n $(SRCTREE)/$(CONFIG_IMX_CONFIG) -T imximage \
-e $(CONFIG_SPL_TEXT_BASE) -d $< $@
endif
$(OBJTREE)/SPL : $(obj)u-boot-spl.bin depend
$(MAKE) -C $(SRCTREE)/arch/arm/imx-common $@
ALL-y += $(obj)u-boot-spl.bin

2
tools/Makefile
View File

@ -69,6 +69,7 @@ BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
BIN_FILES-y += mkenvimage$(SFX)
BIN_FILES-y += mkimage$(SFX)
BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
@ -98,6 +99,7 @@ NOPED_OBJ_FILES-y += omapimage.o
NOPED_OBJ_FILES-y += mkenvimage.o
NOPED_OBJ_FILES-y += mkimage.o
OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
OBJ_FILES-$(CONFIG_MX23) += mxsboot.o
OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
NOPED_OBJ_FILES-y += os_support.o

2
tools/imximage.c
View File

@ -551,7 +551,7 @@ int imximage_check_params(struct mkimage_params *params)
* imximage parameters
*/
static struct image_type_params imximage_params = {
.name = "Freescale i.MX 5x Boot Image support",
.name = "Freescale i.MX Boot Image support",
.header_size = sizeof(struct imx_header),
.hdr = (void *)&imximage_header,
.check_image_type = imximage_check_image_types,