mirror of
https://github.com/u-boot/u-boot.git
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avr32: delete non generic board's atstk100{3, 4, 6}
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Andreas Bießmann
parent
c62d2f8fc5
commit
e5354b8a9e
@ -17,15 +17,6 @@ config TARGET_ATNGW100MKII
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config TARGET_ATSTK1002
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bool "Support atstk1002"
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config TARGET_ATSTK1003
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bool "Support atstk1003"
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config TARGET_ATSTK1004
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bool "Support atstk1004"
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config TARGET_ATSTK1006
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bool "Support atstk1006"
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config TARGET_GRASSHOPPER
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bool "Support grasshopper"
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@ -13,51 +13,3 @@ config SYS_CONFIG_NAME
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default "atstk1002"
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endif
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if TARGET_ATSTK1003
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config SYS_BOARD
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default "atstk1000"
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config SYS_VENDOR
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default "atmel"
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config SYS_SOC
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default "at32ap700x"
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config SYS_CONFIG_NAME
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default "atstk1003"
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endif
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if TARGET_ATSTK1004
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config SYS_BOARD
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default "atstk1000"
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config SYS_VENDOR
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default "atmel"
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config SYS_SOC
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default "at32ap700x"
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config SYS_CONFIG_NAME
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default "atstk1004"
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endif
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if TARGET_ATSTK1006
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config SYS_BOARD
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default "atstk1000"
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config SYS_VENDOR
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default "atmel"
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config SYS_SOC
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default "at32ap700x"
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config SYS_CONFIG_NAME
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default "atstk1006"
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endif
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@ -4,9 +4,3 @@ S: Orphan (since 2014-06)
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F: board/atmel/atstk1000/
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F: include/configs/atstk1002.h
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F: configs/atstk1002_defconfig
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F: include/configs/atstk1003.h
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F: configs/atstk1003_defconfig
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F: include/configs/atstk1004.h
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F: configs/atstk1004_defconfig
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F: include/configs/atstk1006.h
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F: configs/atstk1006_defconfig
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@ -30,32 +30,12 @@ struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
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};
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static const struct sdram_config sdram_config = {
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#if defined(CONFIG_ATSTK1006)
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/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
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.data_bits = SDRAM_DATA_32BIT,
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.row_bits = 13,
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.col_bits = 9,
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.bank_bits = 2,
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.cas = 2,
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.twr = 2,
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.trc = 7,
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.trp = 2,
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.trcd = 2,
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.tras = 4,
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.txsr = 7,
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/* 7.81 us */
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.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
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#else
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/* MT48LC2M32B2P-5 (8 MB) on motherboard */
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#ifdef CONFIG_ATSTK1004
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.data_bits = SDRAM_DATA_16BIT,
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#else
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.data_bits = SDRAM_DATA_32BIT,
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#endif
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#ifdef CONFIG_ATSTK1000_16MB_SDRAM
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/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
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.row_bits = 12,
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#else
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/* MT48LC2M32B2P-5 (8 MB) on motherboard */
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.row_bits = 11,
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#endif
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.col_bits = 8,
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@ -69,7 +49,6 @@ static const struct sdram_config sdram_config = {
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.txsr = 5,
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/* 15.6 us */
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.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
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#endif
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};
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int board_early_init_f(void)
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@ -1,6 +0,0 @@
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CONFIG_AVR32=y
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CONFIG_TARGET_ATSTK1003=y
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CONFIG_AUTOBOOT_KEYED=y
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CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
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CONFIG_AUTOBOOT_DELAY_STR="d"
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CONFIG_AUTOBOOT_STOP_STR=" "
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@ -1,6 +0,0 @@
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CONFIG_AVR32=y
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CONFIG_TARGET_ATSTK1004=y
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CONFIG_AUTOBOOT_KEYED=y
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CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
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CONFIG_AUTOBOOT_DELAY_STR="d"
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CONFIG_AUTOBOOT_STOP_STR=" "
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@ -1,7 +0,0 @@
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CONFIG_AVR32=y
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CONFIG_CMD_NET=y
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CONFIG_TARGET_ATSTK1006=y
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CONFIG_AUTOBOOT_KEYED=y
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CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
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CONFIG_AUTOBOOT_DELAY_STR="d"
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CONFIG_AUTOBOOT_STOP_STR=" "
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@ -1,150 +0,0 @@
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/*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Configuration settings for the ATSTK1003 CPU daughterboard
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/hardware.h>
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7001
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#define CONFIG_ATSTK1003
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#define CONFIG_ATSTK1000
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
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* PLL frequency.
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* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
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*/
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#define CONFIG_PLL
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#define CONFIG_SYS_POWER_MANAGER
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#define CONFIG_SYS_OSC0_HZ 20000000
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#define CONFIG_SYS_PLL0_DIV 1
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#define CONFIG_SYS_PLL0_MUL 7
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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/*
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* Set the CPU running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
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*/
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#define CONFIG_SYS_CLKDIV_CPU 0
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/*
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* Set the HSB running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
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*/
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#define CONFIG_SYS_CLKDIV_HSB 1
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/*
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* Set the PBA running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
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*/
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#define CONFIG_SYS_CLKDIV_PBA 2
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/*
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* Set the PBB running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
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*/
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#define CONFIG_SYS_CLKDIV_PBB 1
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/* Reserve VM regions for SDRAM and NOR flash */
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#define CONFIG_SYS_NR_VM_REGIONS 2
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CONFIG_SYS_PLL0_OPT 0x04
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#define CONFIG_USART_BASE ATMEL_BASE_USART1
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#define CONFIG_USART_ID 1
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/* User serviceable stuff */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
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#define CONFIG_BOOTCOMMAND \
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"mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
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#define CONFIG_BOOTDELAY 1
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_XIMG
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#define CONFIG_ATMEL_USART
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#define CONFIG_PORTMUX_PIO
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#define CONFIG_SYS_HSDRAMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SYS_DCACHE_LINESZ 32
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#define CONFIG_SYS_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
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#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
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#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 65536
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (256*1024)
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/* Allow 4MB for the kernel run-time image */
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#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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#endif /* __CONFIG_H */
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@ -1,150 +0,0 @@
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/*
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* Copyright (C) 2007 Atmel Corporation
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*
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* Configuration settings for the ATSTK1003 CPU daughterboard
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/hardware.h>
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7002
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#define CONFIG_ATSTK1004
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#define CONFIG_ATSTK1000
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
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* PLL frequency.
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* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
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*/
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#define CONFIG_PLL
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#define CONFIG_SYS_POWER_MANAGER
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#define CONFIG_SYS_OSC0_HZ 20000000
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#define CONFIG_SYS_PLL0_DIV 1
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#define CONFIG_SYS_PLL0_MUL 7
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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/*
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* Set the CPU running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
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*/
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#define CONFIG_SYS_CLKDIV_CPU 0
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/*
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* Set the HSB running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
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*/
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#define CONFIG_SYS_CLKDIV_HSB 1
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/*
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* Set the PBA running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
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*/
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#define CONFIG_SYS_CLKDIV_PBA 2
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/*
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* Set the PBB running at:
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* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
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*/
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#define CONFIG_SYS_CLKDIV_PBB 1
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/* Reserve VM regions for SDRAM and NOR flash */
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#define CONFIG_SYS_NR_VM_REGIONS 2
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CONFIG_SYS_PLL0_OPT 0x04
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#define CONFIG_USART_BASE ATMEL_BASE_USART1
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#define CONFIG_USART_ID 1
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/* User serviceable stuff */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"console=ttyS0 root=/dev/mmcblk0p1 rootwait"
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#define CONFIG_BOOTCOMMAND \
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"mmc rescan; ext2load mmc 0:1 0x10200000 /boot/uImage; bootm"
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#define CONFIG_BOOTDELAY 1
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_NFS
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#undef CONFIG_CMD_SETGETDCR
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#undef CONFIG_CMD_XIMG
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#define CONFIG_ATMEL_USART
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#define CONFIG_PORTMUX_PIO
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#define CONFIG_SYS_HSDRAMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SYS_DCACHE_LINESZ 32
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#define CONFIG_SYS_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
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#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
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#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 65536
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (256*1024)
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/* Allow 2MB for the kernel run-time image */
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#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00200000)
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CONFIG_SYS_PROMPT "U-Boot> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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#endif /* __CONFIG_H */
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@ -1,168 +0,0 @@
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/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* Configuration settings for the ATSTK1002 CPU daughterboard
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/arch/hardware.h>
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7000
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#define CONFIG_ATSTK1006
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#define CONFIG_ATSTK1000
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/*
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* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
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* PLL frequency.
|
||||
* (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
|
||||
*/
|
||||
#define CONFIG_PLL
|
||||
#define CONFIG_SYS_POWER_MANAGER
|
||||
#define CONFIG_SYS_OSC0_HZ 20000000
|
||||
#define CONFIG_SYS_PLL0_DIV 1
|
||||
#define CONFIG_SYS_PLL0_MUL 7
|
||||
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
|
||||
/*
|
||||
* Set the CPU running at:
|
||||
* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
|
||||
*/
|
||||
#define CONFIG_SYS_CLKDIV_CPU 0
|
||||
/*
|
||||
* Set the HSB running at:
|
||||
* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
|
||||
*/
|
||||
#define CONFIG_SYS_CLKDIV_HSB 1
|
||||
/*
|
||||
* Set the PBA running at:
|
||||
* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
|
||||
*/
|
||||
#define CONFIG_SYS_CLKDIV_PBA 2
|
||||
/*
|
||||
* Set the PBB running at:
|
||||
* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
|
||||
*/
|
||||
#define CONFIG_SYS_CLKDIV_PBB 1
|
||||
|
||||
/* Reserve VM regions for SDRAM and NOR flash */
|
||||
#define CONFIG_SYS_NR_VM_REGIONS 2
|
||||
|
||||
/*
|
||||
* The PLLOPT register controls the PLL like this:
|
||||
* icp = PLLOPT<2>
|
||||
* ivco = PLLOPT<1:0>
|
||||
*
|
||||
* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
|
||||
*/
|
||||
#define CONFIG_SYS_PLL0_OPT 0x04
|
||||
|
||||
#define CONFIG_USART_BASE ATMEL_BASE_USART1
|
||||
#define CONFIG_USART_ID 1
|
||||
|
||||
/* User serviceable stuff */
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
#define CONFIG_STACKSIZE (2048)
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
#define CONFIG_BOOTARGS \
|
||||
"console=ttyS0 root=mtd3 fbmem=2400k"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"fsload; bootm $(fileaddr)"
|
||||
|
||||
#define CONFIG_BOOTDELAY 1
|
||||
|
||||
/*
|
||||
* After booting the board for the first time, new ethernet addresses
|
||||
* should be generated and assigned to the environment variables
|
||||
* "ethaddr" and "eth1addr". This is normally done during production.
|
||||
*/
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
*/
|
||||
#define CONFIG_BOOTP_SUBNETMASK
|
||||
#define CONFIG_BOOTP_GATEWAY
|
||||
|
||||
|
||||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#define CONFIG_CMD_ASKENV
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_EXT2
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_JFFS2
|
||||
#define CONFIG_CMD_MMC
|
||||
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_SETGETDCR
|
||||
#undef CONFIG_CMD_SOURCE
|
||||
#undef CONFIG_CMD_XIMG
|
||||
|
||||
#define CONFIG_ATMEL_USART
|
||||
#define CONFIG_MACB
|
||||
#define CONFIG_PORTMUX_PIO
|
||||
#define CONFIG_SYS_NR_PIOS 5
|
||||
#define CONFIG_SYS_HSDRAMC
|
||||
#define CONFIG_MMC
|
||||
#define CONFIG_GENERIC_ATMEL_MCI
|
||||
#define CONFIG_GENERIC_MMC
|
||||
|
||||
#define CONFIG_SYS_DCACHE_LINESZ 32
|
||||
#define CONFIG_SYS_ICACHE_LINESZ 32
|
||||
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_SIZE 0x800000
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 135
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_TEXT_BASE 0x00000000
|
||||
|
||||
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
|
||||
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
|
||||
#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SIZE 65536
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
|
||||
|
||||
#define CONFIG_SYS_MALLOC_LEN (256*1024)
|
||||
|
||||
/* Allow 4MB for the kernel run-time image */
|
||||
#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
|
||||
#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
|
||||
|
||||
/* Other configuration settings that shouldn't have to change all that often */
|
||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||
#define CONFIG_SYS_CBSIZE 256
|
||||
#define CONFIG_SYS_MAXARGS 16
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000)
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user