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https://github.com/u-boot/u-boot.git
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avr32: delete non generic board hammerhead
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Andreas Bießmann
parent
9eb45aabe0
commit
e369307644
@ -32,9 +32,6 @@ config TARGET_GRASSHOPPER
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config TARGET_MIMC200
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bool "Support mimc200"
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config TARGET_HAMMERHEAD
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bool "Support hammerhead"
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endchoice
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source "board/atmel/atngw100/Kconfig"
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@ -42,6 +39,5 @@ source "board/atmel/atngw100mkii/Kconfig"
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source "board/atmel/atstk1000/Kconfig"
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source "board/in-circuit/grasshopper/Kconfig"
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source "board/mimc/mimc200/Kconfig"
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source "board/miromico/hammerhead/Kconfig"
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endmenu
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@ -1,15 +0,0 @@
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if TARGET_HAMMERHEAD
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config SYS_BOARD
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default "hammerhead"
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config SYS_VENDOR
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default "miromico"
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config SYS_SOC
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default "at32ap700x"
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config SYS_CONFIG_NAME
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default "hammerhead"
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endif
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@ -1,6 +0,0 @@
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HAMMERHEAD BOARD
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M: Alex Raimondi <alex.raimondi@miromico.ch>
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S: Maintained
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F: board/miromico/hammerhead/
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F: include/configs/hammerhead.h
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F: configs/hammerhead_defconfig
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@ -1,6 +0,0 @@
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#
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# Copyright (C) 2008 Miromico AG
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#
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# SPDX-License-Identifier: GPL-2.0+
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obj-y := hammerhead.o
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@ -1,91 +0,0 @@
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/*
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* Copyright (C) 2008 Miromico AG
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*
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* Mostly copied form atmel ATNGW100 sources
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hmatrix.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mmu.h>
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#include <asm/arch/portmux.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
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{
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.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
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.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
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.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
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| MMU_VMR_CACHE_NONE,
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}, {
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.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
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.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
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.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
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| MMU_VMR_CACHE_WRBACK,
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},
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};
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static const struct sdram_config sdram_config = {
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.data_bits = SDRAM_DATA_32BIT,
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.row_bits = 13,
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.col_bits = 9,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 7,
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.trp = 2,
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.trcd = 2,
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.tras = 5,
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.txsr = 5,
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/* 7.81 us */
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.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
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};
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
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bis->bi_phy_id[0]);
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}
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#endif
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
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portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
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sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
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portmux_enable_usart1(PORTMUX_DRIVE_MIN);
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#if defined(CONFIG_MACB)
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portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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#endif
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#if defined(CONFIG_MMC)
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portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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gd->bd->bi_phy_id[0] = 0x01;
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return 0;
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}
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int board_postclk_init(void)
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{
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/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
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gclk_enable_output(3, PORTMUX_DRIVE_LOW);
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gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
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return 0;
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}
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@ -1,7 +0,0 @@
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CONFIG_AVR32=y
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CONFIG_CMD_NET=y
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CONFIG_TARGET_HAMMERHEAD=y
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CONFIG_AUTOBOOT_KEYED=y
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CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds"
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CONFIG_AUTOBOOT_DELAY_STR="d"
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CONFIG_AUTOBOOT_STOP_STR=" "
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@ -1,147 +0,0 @@
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/*
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* Copyright (C) 2008 Miromico AG
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*
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* Configuration settings for the Miromico Hammerhead AVR32 board
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_AT32AP
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#define CONFIG_AT32AP7000
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#define CONFIG_HAMMERHEAD
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/*
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* Set up the PLL to run at 125 MHz, the CPU to run at the PLL
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* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
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* and the PBA bus to run at 1/4 the PLL frequency.
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*/
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#define CONFIG_PLL
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#define CONFIG_SYS_POWER_MANAGER
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#define CONFIG_SYS_OSC0_HZ 25000000
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#define CONFIG_SYS_PLL0_DIV 1
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#define CONFIG_SYS_PLL0_MUL 5
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#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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#define CONFIG_SYS_CLKDIV_CPU 0
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#define CONFIG_SYS_CLKDIV_HSB 1
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#define CONFIG_SYS_CLKDIV_PBA 2
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#define CONFIG_SYS_CLKDIV_PBB 1
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/* Reserve VM regions for SDRAM and NOR flash */
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#define CONFIG_SYS_NR_VM_REGIONS 2
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/*
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* The PLLOPT register controls the PLL like this:
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* icp = PLLOPT<2>
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* ivco = PLLOPT<1:0>
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*
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* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
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*/
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#define CONFIG_SYS_PLL0_OPT 0x04
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#define CONFIG_USART_BASE ATMEL_BASE_USART1
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#define CONFIG_USART_ID 1
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#define CONFIG_HOSTNAME hammerhead
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/* User serviceable stuff */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_STACKSIZE (2048)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BOOTARGS \
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"console=ttyS0 root=mtd1 rootfstype=jffs2"
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#define CONFIG_BOOTCOMMAND \
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"fsload; bootm"
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#define CONFIG_BOOTDELAY 1
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/*
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* After booting the board for the first time, new ethernet address
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* should be generated and assigned to the environment variables
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* "ethaddr". This is normally done during production.
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*/
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#define CONFIG_OVERWRITE_ETHADDR_ONCE
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/*
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* BOOTP/DHCP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_MMC
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#undef CONFIG_CMD_FPGA
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#undef CONFIG_CMD_SETGETDCR
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#define CONFIG_ATMEL_USART
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#define CONFIG_MACB
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#define CONFIG_PORTMUX_PIO
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#define CONFIG_SYS_NR_PIOS 5
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#define CONFIG_SYS_HSDRAMC
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#define CONFIG_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_GENERIC_MMC
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#define CONFIG_SYS_DCACHE_LINESZ 32
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#define CONFIG_SYS_ICACHE_LINESZ 32
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_BASE 0x00000000
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#define CONFIG_SYS_FLASH_SIZE 0x800000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 135
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_TEXT_BASE 0x00000000
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#define CONFIG_SYS_INTRAM_BASE 0x24000000
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#define CONFIG_SYS_INTRAM_SIZE 0x8000
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#define CONFIG_SYS_SDRAM_BASE 0x10000000
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 65536
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
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#define CONFIG_SYS_MALLOC_LEN (256*1024)
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/* Allow 4MB for the kernel run-time image */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
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#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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/* Other configuration settings that shouldn't have to change all that often */
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#define CONFIG_SYS_PROMPT "Hammerhead> "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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#endif /* __CONFIG_H */
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