mirror of
https://github.com/u-boot/u-boot.git
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sata: Drop Silicon Image SIL3114 SATA driver
This is not used in U-Boot and has not been converted to driver model. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Simon Glass
Tom Rini
parent
a8c281d4b7
commit
e32ec06c9e
@ -109,12 +109,6 @@ config SATA_SIL
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Enable this driver to support the SIL3131, SIL3132 and SIL3124
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SATA controllers.
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config SATA_SIL3114
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bool "Enable Silicon Image SIL3114 SATA driver support"
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select LIBATA
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help
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Enable this driver to support the SIL3114 SATA controllers.
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config SUNXI_AHCI
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bool "Enable Allwinner SATA driver support"
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depends on AHCI
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@ -13,7 +13,6 @@ obj-$(CONFIG_LIBATA) += libata.o
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obj-$(CONFIG_SATA) += sata.o
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obj-$(CONFIG_SATA_CEVA) += sata_ceva.o
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obj-$(CONFIG_SATA_MV) += sata_mv.o
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obj-$(CONFIG_SATA_SIL3114) += sata_sil3114.o
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obj-$(CONFIG_SATA_SIL) += sata_sil.o
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obj-$(CONFIG_SANDBOX) += sata_sandbox.o
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obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o
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@ -1,838 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
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* Author: Tor Krill <tor@excito.com>
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*
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* This is a driver for Silicon Image sil3114 sata chip modelled on
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* the ata_piix driver
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*/
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#include <common.h>
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#include <blk.h>
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#include <log.h>
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#include <part.h>
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#include <pci.h>
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#include <command.h>
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#include <config.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <ide.h>
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#include <sata.h>
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#include <libata.h>
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#include <linux/delay.h>
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#include "sata_sil3114.h"
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/* Convert sectorsize to wordsize */
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#define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
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/* Forwards */
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u8 sil3114_spin_up (int num);
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u8 sil3114_spin_down (int num);
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static int sata_bus_softreset (int num);
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static void sata_identify (int num, int dev);
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static u8 check_power_mode (int num);
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static void sata_port (struct sata_ioports *ioport);
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static void set_Feature_cmd (int num, int dev);
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static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
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unsigned int max, u8 usealtstatus);
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static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
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static void msleep (int count);
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static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
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static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
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static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
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{
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while (words--) {
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__raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
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}
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}
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static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
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{
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while (words--) {
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*sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
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}
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return 0;
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}
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static int sata_bus_softreset (int num)
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{
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u8 status = 0;
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port[num].dev_mask = 1;
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port[num].ctl_reg = 0x08; /*Default value of control reg */
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writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
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udelay(10);
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writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
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udelay(10);
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writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
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/* spec mandates ">= 2ms" before checking status.
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* We wait 150ms, because that was the magic delay used for
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* ATAPI devices in Hale Landis's ATADRVR, for the period of time
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* between when the ATA command register is written, and then
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* status is checked. Because waiting for "a while" before
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* checking status is fine, post SRST, we perform this magic
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* delay here as well.
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*/
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msleep (150);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
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while ((status & ATA_BUSY)) {
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msleep (100);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
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}
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if (status & ATA_BUSY) {
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printf ("ata%u is slow to respond,plz be patient\n", num);
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}
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while ((status & ATA_BUSY)) {
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msleep (100);
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status = sata_chk_status (&port[num].ioaddr, 0);
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}
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if (status & ATA_BUSY) {
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printf ("ata%u failed to respond : ", num);
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printf ("bus reset failed\n");
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port[num].dev_mask = 0;
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return 1;
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}
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return 0;
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}
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static void sata_identify (int num, int dev)
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{
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u8 cmd = 0, status = 0, devno = num;
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u16 iobuf[ATA_SECTOR_WORDS];
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u64 n_sectors = 0;
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memset (iobuf, 0, sizeof (iobuf));
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if (!(port[num].dev_mask & 0x01)) {
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printf ("dev%d is not present on port#%d\n", dev, num);
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return;
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}
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debug ("port=%d dev=%d\n", num, dev);
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status = 0;
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cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
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writeb (cmd, port[num].ioaddr.command_addr);
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readb (port[num].ioaddr.altstatus_addr);
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udelay(10);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
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if (status & ATA_ERR) {
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printf ("\ndevice not responding\n");
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port[num].dev_mask &= ~0x01;
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return;
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}
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input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
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ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
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debug ("Specific config: %x\n", iobuf[2]);
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/* we require LBA and DMA support (bits 8 & 9 of word 49) */
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if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
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debug ("ata%u: no dma/lba\n", num);
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}
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#ifdef DEBUG
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ata_dump_id (iobuf);
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#endif
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n_sectors = ata_id_n_sectors (iobuf);
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if (n_sectors == 0) {
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port[num].dev_mask &= ~0x01;
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return;
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}
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ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
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ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
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ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
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ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
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ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
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ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
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/* TODO - atm we asume harddisk ie not removable */
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sata_dev_desc[devno].removable = 0;
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sata_dev_desc[devno].lba = (u32) n_sectors;
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debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
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#ifdef CONFIG_LBA48
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if (iobuf[83] & (1 << 10)) {
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sata_dev_desc[devno].lba48 = 1;
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} else {
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sata_dev_desc[devno].lba48 = 0;
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}
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#endif
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/* assuming HD */
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sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
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sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
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sata_dev_desc[devno].lun = 0; /* just to fill something in... */
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}
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static void set_Feature_cmd (int num, int dev)
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{
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u8 status = 0;
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if (!(port[num].dev_mask & 0x01)) {
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debug ("dev%d is not present on port#%d\n", dev, num);
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return;
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}
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writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
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writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
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writeb (0, port[num].ioaddr.lbal_addr);
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writeb (0, port[num].ioaddr.lbam_addr);
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writeb (0, port[num].ioaddr.lbah_addr);
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writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
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writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
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udelay(50);
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msleep (150);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
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if ((status & (ATA_BUSY | ATA_ERR))) {
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printf ("Error : status 0x%02x\n", status);
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port[num].dev_mask &= ~0x01;
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}
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}
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u8 sil3114_spin_down (int num)
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{
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u8 status = 0;
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debug ("Spin down disk\n");
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if (!(port[num].dev_mask & 0x01)) {
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debug ("Device ata%d is not present\n", num);
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return 1;
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}
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if ((status = check_power_mode (num)) == 0x00) {
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debug ("Already in standby\n");
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return 0;
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}
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if (status == 0x01) {
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printf ("Failed to check power mode on ata%d\n", num);
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return 1;
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}
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if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
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printf ("Device ata%d not ready\n", num);
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return 1;
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}
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writeb (0x00, port[num].ioaddr.feature_addr);
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writeb (0x00, port[num].ioaddr.nsect_addr);
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writeb (0x00, port[num].ioaddr.lbal_addr);
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writeb (0x00, port[num].ioaddr.lbam_addr);
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writeb (0x00, port[num].ioaddr.lbah_addr);
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writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
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writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
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if ((status & (ATA_BUSY | ATA_ERR))) {
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printf ("Error waiting for disk spin down: status 0x%02x\n",
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status);
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port[num].dev_mask &= ~0x01;
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return 1;
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}
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return 0;
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}
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u8 sil3114_spin_up (int num)
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{
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u8 status = 0;
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debug ("Spin up disk\n");
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if (!(port[num].dev_mask & 0x01)) {
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debug ("Device ata%d is not present\n", num);
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return 1;
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}
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if ((status = check_power_mode (num)) != 0x00) {
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if (status == 0x01) {
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printf ("Failed to check power mode on ata%d\n", num);
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return 1;
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} else {
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/* should be up and running already */
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return 0;
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}
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}
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if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
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printf ("Device ata%d not ready\n", num);
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return 1;
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}
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debug ("Stautus of device check: %d\n", status);
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writeb (0x00, port[num].ioaddr.feature_addr);
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writeb (0x00, port[num].ioaddr.nsect_addr);
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writeb (0x00, port[num].ioaddr.lbal_addr);
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writeb (0x00, port[num].ioaddr.lbam_addr);
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writeb (0x00, port[num].ioaddr.lbah_addr);
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writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
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writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
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if ((status & (ATA_BUSY | ATA_ERR))) {
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printf ("Error waiting for disk spin up: status 0x%02x\n",
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status);
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port[num].dev_mask &= ~0x01;
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return 1;
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}
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/* Wait for disk to enter Active state */
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do {
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msleep (10);
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status = check_power_mode (num);
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} while ((status == 0x00) || (status == 0x80));
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if (status == 0x01) {
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printf ("Falied waiting for disk to spin up\n");
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return 1;
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}
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return 0;
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}
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/* Return value is not the usual here
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* 0x00 - Device stand by
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* 0x01 - Operation failed
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* 0x80 - Device idle
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* 0xff - Device active
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*/
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static u8 check_power_mode (int num)
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{
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u8 status = 0;
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u8 res = 0;
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if (!(port[num].dev_mask & 0x01)) {
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debug ("Device ata%d is not present\n", num);
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return 1;
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}
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if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
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printf ("Device ata%d not ready\n", num);
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return 1;
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}
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writeb (0, port[num].ioaddr.feature_addr);
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writeb (0, port[num].ioaddr.nsect_addr);
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writeb (0, port[num].ioaddr.lbal_addr);
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writeb (0, port[num].ioaddr.lbam_addr);
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writeb (0, port[num].ioaddr.lbah_addr);
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writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
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writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
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status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
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if ((status & (ATA_BUSY | ATA_ERR))) {
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printf
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("Error waiting for check power mode complete : status 0x%02x\n",
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status);
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port[num].dev_mask &= ~0x01;
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return 1;
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}
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res = readb (port[num].ioaddr.nsect_addr);
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debug ("Check powermode: %d\n", res);
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return res;
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}
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static void sata_port (struct sata_ioports *ioport)
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{
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ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
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ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
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ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
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ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
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ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
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ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
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ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
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ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
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ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
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ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
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}
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static u8 wait_for_irq (int num, unsigned int max)
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{
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u32 port = iobase[5];
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switch (num) {
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case 0:
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port += VND_TF_CNST_CH0;
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break;
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case 1:
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port += VND_TF_CNST_CH1;
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break;
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case 2:
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port += VND_TF_CNST_CH2;
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break;
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case 3:
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port += VND_TF_CNST_CH3;
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break;
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default:
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return 1;
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}
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do {
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if (readl (port) & VND_TF_CNST_INTST) {
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break;
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}
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udelay(1000);
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max--;
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} while ((max > 0));
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return (max == 0);
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}
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static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
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unsigned int max, u8 usealtstatus)
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{
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u8 status;
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do {
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if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
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break;
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}
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udelay(1000);
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max--;
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} while ((status & bits) && (max > 0));
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return status;
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}
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static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
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{
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if (!usealtstatus) {
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return readb (ioaddr->status_addr);
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} else {
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return readb (ioaddr->altstatus_addr);
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}
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}
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static void msleep (int count)
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{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < count; i++)
|
||||
udelay(1000);
|
||||
}
|
||||
|
||||
/* Read up to 255 sectors
|
||||
*
|
||||
* Returns sectors read
|
||||
*/
|
||||
static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
|
||||
uchar lba48)
|
||||
{
|
||||
|
||||
u8 sr = 0;
|
||||
u8 status;
|
||||
u64 blknr = (u64) block;
|
||||
|
||||
if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
|
||||
printf ("Device ata%d not ready\n", device);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Set up transfer */
|
||||
#ifdef CONFIG_LBA48
|
||||
if (lba48) {
|
||||
/* write high bits */
|
||||
writeb (0, port[device].ioaddr.nsect_addr);
|
||||
writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
|
||||
writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
|
||||
writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
|
||||
}
|
||||
#endif
|
||||
writeb (blkcnt, port[device].ioaddr.nsect_addr);
|
||||
writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
|
||||
writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
|
||||
writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
|
||||
|
||||
#ifdef CONFIG_LBA48
|
||||
if (lba48) {
|
||||
writeb (ATA_LBA, port[device].ioaddr.device_addr);
|
||||
writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
writeb (ATA_LBA | ((blknr >> 24) & 0xF),
|
||||
port[device].ioaddr.device_addr);
|
||||
writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
|
||||
}
|
||||
|
||||
status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
|
||||
|
||||
if (status & ATA_BUSY) {
|
||||
u8 err = 0;
|
||||
|
||||
printf ("Device %d not responding status %d\n", device, status);
|
||||
err = readb (port[device].ioaddr.error_addr);
|
||||
printf ("Error reg = 0x%x\n", err);
|
||||
|
||||
return (sr);
|
||||
}
|
||||
while (blkcnt--) {
|
||||
|
||||
if (wait_for_irq (device, 500)) {
|
||||
printf ("ata%u irq failed\n", device);
|
||||
return sr;
|
||||
}
|
||||
|
||||
status = sata_chk_status (&port[device].ioaddr, 0);
|
||||
if (status & ATA_ERR) {
|
||||
printf ("ata%u error %d\n", device,
|
||||
readb (port[device].ioaddr.error_addr));
|
||||
return sr;
|
||||
}
|
||||
/* Read one sector */
|
||||
input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
|
||||
buff += ATA_SECTOR_WORDS;
|
||||
sr++;
|
||||
|
||||
}
|
||||
return sr;
|
||||
}
|
||||
|
||||
ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
|
||||
{
|
||||
ulong n = 0, sread;
|
||||
u16 *buffer = (u16 *) buff;
|
||||
u8 status = 0;
|
||||
u64 blknr = (u64) block;
|
||||
unsigned char lba48 = 0;
|
||||
|
||||
#ifdef CONFIG_LBA48
|
||||
if (blknr > 0xfffffff) {
|
||||
if (!sata_dev_desc[device].lba48) {
|
||||
printf ("Drive doesn't support 48-bit addressing\n");
|
||||
return 0;
|
||||
}
|
||||
/* more than 28 bits used, use 48bit mode */
|
||||
lba48 = 1;
|
||||
}
|
||||
#endif
|
||||
|
||||
while (blkcnt > 0) {
|
||||
|
||||
if (blkcnt > 255) {
|
||||
sread = 255;
|
||||
} else {
|
||||
sread = blkcnt;
|
||||
}
|
||||
|
||||
status = do_one_read (device, blknr, sread, buffer, lba48);
|
||||
if (status != sread) {
|
||||
printf ("Read failed\n");
|
||||
return n;
|
||||
}
|
||||
|
||||
blkcnt -= sread;
|
||||
blknr += sread;
|
||||
n += sread;
|
||||
buffer += sread * ATA_SECTOR_WORDS;
|
||||
}
|
||||
return n;
|
||||
}
|
||||
|
||||
ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
|
||||
{
|
||||
ulong n = 0;
|
||||
u16 *buffer = (u16 *) buff;
|
||||
unsigned char status = 0, num = 0;
|
||||
u64 blknr = (u64) block;
|
||||
#ifdef CONFIG_LBA48
|
||||
unsigned char lba48 = 0;
|
||||
|
||||
if (blknr > 0xfffffff) {
|
||||
if (!sata_dev_desc[device].lba48) {
|
||||
printf ("Drive doesn't support 48-bit addressing\n");
|
||||
return 0;
|
||||
}
|
||||
/* more than 28 bits used, use 48bit mode */
|
||||
lba48 = 1;
|
||||
}
|
||||
#endif
|
||||
/*Port Number */
|
||||
num = device;
|
||||
|
||||
while (blkcnt-- > 0) {
|
||||
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
|
||||
if (status & ATA_BUSY) {
|
||||
printf ("ata%u failed to respond\n", port[num].port_no);
|
||||
return n;
|
||||
}
|
||||
#ifdef CONFIG_LBA48
|
||||
if (lba48) {
|
||||
/* write high bits */
|
||||
writeb (0, port[num].ioaddr.nsect_addr);
|
||||
writeb ((blknr >> 24) & 0xFF,
|
||||
port[num].ioaddr.lbal_addr);
|
||||
writeb ((blknr >> 32) & 0xFF,
|
||||
port[num].ioaddr.lbam_addr);
|
||||
writeb ((blknr >> 40) & 0xFF,
|
||||
port[num].ioaddr.lbah_addr);
|
||||
}
|
||||
#endif
|
||||
writeb (1, port[num].ioaddr.nsect_addr);
|
||||
writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
|
||||
writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
|
||||
writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
|
||||
#ifdef CONFIG_LBA48
|
||||
if (lba48) {
|
||||
writeb (ATA_LBA, port[num].ioaddr.device_addr);
|
||||
writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
|
||||
} else
|
||||
#endif
|
||||
{
|
||||
writeb (ATA_LBA | ((blknr >> 24) & 0xF),
|
||||
port[num].ioaddr.device_addr);
|
||||
writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
|
||||
}
|
||||
|
||||
msleep (50);
|
||||
/*may take up to 4 sec */
|
||||
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
|
||||
if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
|
||||
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
|
||||
device, (ulong) blknr, status);
|
||||
return (n);
|
||||
}
|
||||
|
||||
output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
|
||||
readb (port[num].ioaddr.altstatus_addr);
|
||||
udelay(50);
|
||||
|
||||
++n;
|
||||
++blknr;
|
||||
buffer += ATA_SECTOR_WORDS;
|
||||
}
|
||||
return n;
|
||||
}
|
||||
|
||||
/* Driver implementation */
|
||||
static u8 sil_get_device_cache_line (pci_dev_t pdev)
|
||||
{
|
||||
u8 cache_line = 0;
|
||||
pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
|
||||
return cache_line;
|
||||
}
|
||||
|
||||
int init_sata (int dev)
|
||||
{
|
||||
static u8 init_done = 0;
|
||||
static int res = 1;
|
||||
pci_dev_t devno;
|
||||
u8 cls = 0;
|
||||
u16 cmd = 0;
|
||||
u32 sconf = 0;
|
||||
|
||||
if (init_done) {
|
||||
return res;
|
||||
}
|
||||
|
||||
init_done = 1;
|
||||
|
||||
if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
|
||||
res = 1;
|
||||
return res;
|
||||
}
|
||||
|
||||
/* Read out all BARs, even though we only use MMIO from BAR5 */
|
||||
pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
|
||||
pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
|
||||
pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
|
||||
pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
|
||||
pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
|
||||
pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
|
||||
|
||||
if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
|
||||
(iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
|
||||
(iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
|
||||
printf ("Error no base addr for SATA controller\n");
|
||||
res = 1;
|
||||
return res;
|
||||
}
|
||||
|
||||
/* mask off unused bits */
|
||||
iobase[0] &= 0xfffffffc;
|
||||
iobase[1] &= 0xfffffff8;
|
||||
iobase[2] &= 0xfffffffc;
|
||||
iobase[3] &= 0xfffffff8;
|
||||
iobase[4] &= 0xfffffff0;
|
||||
iobase[5] &= 0xfffffc00;
|
||||
|
||||
/* from sata_sil in Linux kernel */
|
||||
cls = sil_get_device_cache_line (devno);
|
||||
if (cls) {
|
||||
cls >>= 3;
|
||||
cls++; /* cls = (line_size/8)+1 */
|
||||
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
|
||||
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
|
||||
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
|
||||
writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
|
||||
} else {
|
||||
printf ("Cache line not set. Driver may not function\n");
|
||||
}
|
||||
|
||||
/* Enable operation */
|
||||
pci_read_config_word (devno, PCI_COMMAND, &cmd);
|
||||
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
|
||||
pci_write_config_word (devno, PCI_COMMAND, cmd);
|
||||
|
||||
/* Disable interrupt usage */
|
||||
pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
|
||||
sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
|
||||
pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
|
||||
|
||||
res = 0;
|
||||
return res;
|
||||
}
|
||||
|
||||
int reset_sata(int dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Check if device is connected to port */
|
||||
int sata_bus_probe (int portno)
|
||||
{
|
||||
u32 port = iobase[5];
|
||||
u32 val;
|
||||
switch (portno) {
|
||||
case 0:
|
||||
port += VND_SSTATUS_CH0;
|
||||
break;
|
||||
case 1:
|
||||
port += VND_SSTATUS_CH1;
|
||||
break;
|
||||
case 2:
|
||||
port += VND_SSTATUS_CH2;
|
||||
break;
|
||||
case 3:
|
||||
port += VND_SSTATUS_CH3;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
val = readl (port);
|
||||
if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
|
||||
return 1;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
int sata_phy_reset (int portno)
|
||||
{
|
||||
u32 port = iobase[5];
|
||||
u32 val;
|
||||
switch (portno) {
|
||||
case 0:
|
||||
port += VND_SCONTROL_CH0;
|
||||
break;
|
||||
case 1:
|
||||
port += VND_SCONTROL_CH1;
|
||||
break;
|
||||
case 2:
|
||||
port += VND_SCONTROL_CH2;
|
||||
break;
|
||||
case 3:
|
||||
port += VND_SCONTROL_CH3;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
val = readl (port);
|
||||
writel (val | SATA_SC_DET_RST, port);
|
||||
msleep (150);
|
||||
writel (val & ~SATA_SC_DET_RST, port);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int scan_sata (int dev)
|
||||
{
|
||||
/* A bit brain dead, but the code has a legacy */
|
||||
switch (dev) {
|
||||
case 0:
|
||||
port[0].port_no = 0;
|
||||
port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
|
||||
port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
|
||||
(iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
|
||||
port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
|
||||
break;
|
||||
#if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
|
||||
case 1:
|
||||
port[1].port_no = 0;
|
||||
port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
|
||||
port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
|
||||
(iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
|
||||
port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
|
||||
break;
|
||||
#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
|
||||
case 2:
|
||||
port[2].port_no = 0;
|
||||
port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
|
||||
port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
|
||||
(iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
|
||||
port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
|
||||
break;
|
||||
#elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
|
||||
case 3:
|
||||
port[3].port_no = 0;
|
||||
port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
|
||||
port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
|
||||
(iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
|
||||
port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
printf ("Tried to scan unknown port: ata%d\n", dev);
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Initialize other registers */
|
||||
sata_port (&port[dev].ioaddr);
|
||||
|
||||
/* Check for attached device */
|
||||
if (!sata_bus_probe (dev)) {
|
||||
port[dev].port_state = 0;
|
||||
debug ("SATA#%d port is not present\n", dev);
|
||||
} else {
|
||||
debug ("SATA#%d port is present\n", dev);
|
||||
if (sata_bus_softreset (dev)) {
|
||||
/* soft reset failed, try a hard one */
|
||||
sata_phy_reset (dev);
|
||||
if (sata_bus_softreset (dev)) {
|
||||
port[dev].port_state = 0;
|
||||
} else {
|
||||
port[dev].port_state = 1;
|
||||
}
|
||||
} else {
|
||||
port[dev].port_state = 1;
|
||||
}
|
||||
}
|
||||
if (port[dev].port_state == 1) {
|
||||
/* Probe device and set xfer mode */
|
||||
sata_identify (dev, 0);
|
||||
set_Feature_cmd (dev, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,133 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
|
||||
* Author: Tor Krill <tor@excito.com>
|
||||
*/
|
||||
|
||||
#ifndef SATA_SIL3114_H
|
||||
#define SATA_SIL3114_H
|
||||
|
||||
struct sata_ioports {
|
||||
unsigned long cmd_addr;
|
||||
unsigned long data_addr;
|
||||
unsigned long error_addr;
|
||||
unsigned long feature_addr;
|
||||
unsigned long nsect_addr;
|
||||
unsigned long lbal_addr;
|
||||
unsigned long lbam_addr;
|
||||
unsigned long lbah_addr;
|
||||
unsigned long device_addr;
|
||||
unsigned long status_addr;
|
||||
unsigned long command_addr;
|
||||
unsigned long altstatus_addr;
|
||||
unsigned long ctl_addr;
|
||||
unsigned long bmdma_addr;
|
||||
unsigned long scr_addr;
|
||||
};
|
||||
|
||||
struct sata_port {
|
||||
unsigned char port_no; /* primary=0, secondary=1 */
|
||||
struct sata_ioports ioaddr; /* ATA cmd/ctl/dma reg blks */
|
||||
unsigned char ctl_reg;
|
||||
unsigned char last_ctl;
|
||||
unsigned char port_state; /* 1-port is available and */
|
||||
/* 0-port is not available */
|
||||
unsigned char dev_mask;
|
||||
};
|
||||
|
||||
/* Missing ata defines */
|
||||
#define ATA_CMD_STANDBY 0xE2
|
||||
#define ATA_CMD_STANDBYNOW1 0xE0
|
||||
#define ATA_CMD_IDLE 0xE3
|
||||
#define ATA_CMD_IDLEIMMEDIATE 0xE1
|
||||
|
||||
/* Defines for SIL3114 chip */
|
||||
|
||||
/* PCI defines */
|
||||
#define SIL_VEND_ID 0x1095
|
||||
#define SIL3114_DEVICE_ID 0x3114
|
||||
|
||||
/* some vendor specific registers */
|
||||
#define VND_SYSCONFSTAT 0x88 /* System Configuration Status and Command */
|
||||
#define VND_SYSCONFSTAT_CHN_0_INTBLOCK (1<<22)
|
||||
#define VND_SYSCONFSTAT_CHN_1_INTBLOCK (1<<23)
|
||||
#define VND_SYSCONFSTAT_CHN_2_INTBLOCK (1<<24)
|
||||
#define VND_SYSCONFSTAT_CHN_3_INTBLOCK (1<<25)
|
||||
|
||||
/* internal registers mapped by BAR5 */
|
||||
/* SATA Control*/
|
||||
#define VND_SCONTROL_CH0 0x100
|
||||
#define VND_SCONTROL_CH1 0x180
|
||||
#define VND_SCONTROL_CH2 0x300
|
||||
#define VND_SCONTROL_CH3 0x380
|
||||
|
||||
#define SATA_SC_IPM_T2P (1<<16)
|
||||
#define SATA_SC_IPM_T2S (2<<16)
|
||||
#define SATA_SC_SPD_1_5 (1<<4)
|
||||
#define SATA_SC_SPD_3_0 (2<<4)
|
||||
#define SATA_SC_DET_RST (1) /* ATA Reset sequence */
|
||||
#define SATA_SC_DET_PDIS (4) /* PHY Disable */
|
||||
|
||||
/* SATA Status */
|
||||
#define VND_SSTATUS_CH0 0x104
|
||||
#define VND_SSTATUS_CH1 0x184
|
||||
#define VND_SSTATUS_CH2 0x304
|
||||
#define VND_SSTATUS_CH3 0x384
|
||||
|
||||
#define SATA_SS_IPM_ACTIVE (1<<8)
|
||||
#define SATA_SS_IPM_PARTIAL (2<<8)
|
||||
#define SATA_SS_IPM_SLUMBER (6<<8)
|
||||
#define SATA_SS_SPD_1_5 (1<<4)
|
||||
#define SATA_SS_SPD_3_0 (2<<4)
|
||||
#define SATA_DET_P_NOPHY (1) /* Device presence but no PHY connection established */
|
||||
#define SATA_DET_PRES (3) /* Device presence and active PHY */
|
||||
#define SATA_DET_OFFLINE (4) /* Device offline or in loopback mode */
|
||||
|
||||
/* Task file registers in BAR5 mapping */
|
||||
#define VND_TF0_CH0 0x80
|
||||
#define VND_TF0_CH1 0xc0
|
||||
#define VND_TF0_CH2 0x280
|
||||
#define VND_TF0_CH3 0x2c0
|
||||
#define VND_TF1_CH0 0x88
|
||||
#define VND_TF1_CH1 0xc8
|
||||
#define VND_TF1_CH2 0x288
|
||||
#define VND_TF1_CH3 0x2c8
|
||||
#define VND_TF2_CH0 0x88
|
||||
#define VND_TF2_CH1 0xc8
|
||||
#define VND_TF2_CH2 0x288
|
||||
#define VND_TF2_CH3 0x2c8
|
||||
|
||||
#define VND_BMDMA_CH0 0x00
|
||||
#define VND_BMDMA_CH1 0x08
|
||||
#define VND_BMDMA_CH2 0x200
|
||||
#define VND_BMDMA_CH3 0x208
|
||||
#define VND_BMDMA2_CH0 0x10
|
||||
#define VND_BMDMA2_CH1 0x18
|
||||
#define VND_BMDMA2_CH2 0x210
|
||||
#define VND_BMDMA2_CH3 0x218
|
||||
|
||||
/* FIFO control */
|
||||
#define VND_FIFOCFG_CH0 0x40
|
||||
#define VND_FIFOCFG_CH1 0x44
|
||||
#define VND_FIFOCFG_CH2 0x240
|
||||
#define VND_FIFOCFG_CH3 0x244
|
||||
|
||||
/* Task File configuration and status */
|
||||
#define VND_TF_CNST_CH0 0xa0
|
||||
#define VND_TF_CNST_CH1 0xe0
|
||||
#define VND_TF_CNST_CH2 0x2a0
|
||||
#define VND_TF_CNST_CH3 0x2e0
|
||||
|
||||
#define VND_TF_CNST_BFCMD (1<<1)
|
||||
#define VND_TF_CNST_CHNRST (1<<2)
|
||||
#define VND_TF_CNST_VDMA (1<<10)
|
||||
#define VND_TF_CNST_INTST (1<<11)
|
||||
#define VND_TF_CNST_WDTO (1<<12)
|
||||
#define VND_TF_CNST_WDEN (1<<13)
|
||||
#define VND_TF_CNST_WDIEN (1<<14)
|
||||
|
||||
/* for testing */
|
||||
#define VND_SSDR 0x04c /* System Software Data Register */
|
||||
#define VND_FMACS 0x050 /* Flash Memory Address control and status */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user