From b106a14e2f5dfac53d9cd64a11875c011628558d Mon Sep 17 00:00:00 2001 From: Daniel Wagenknecht Date: Thu, 16 Dec 2021 20:42:10 +0100 Subject: [PATCH 01/14] sunxi: SPI: fix pinmuxing for Allwinner H6 SoCs The driver for SPI0 on Allwinner H6 SoCs did not use the correct define SUN50I_GPC_SPI0 for the pin function, but one for a different Allwinner SoC series. Fix the conditionals to use the correct define for H6 SoCs. This matches the conditional logic in the SPL spi driver. Tested by probing the spi-flash on a pine64_h64-model-b board with adapted device-tree (disable mmc2, enable spi0). Signed-off-by: Daniel Wagenknecht Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/spi/spi-sunxi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index bc2f544e863..d62355ec6fb 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -249,7 +249,8 @@ static int sun4i_spi_parse_pins(struct udevice *dev) if (pin < 0) break; - if (IS_ENABLED(CONFIG_MACH_SUN50I)) + if (IS_ENABLED(CONFIG_MACH_SUN50I) || + IS_ENABLED(CONFIG_SUN50I_GEN_H6)) sunxi_gpio_set_cfgpin(pin, SUN50I_GPC_SPI0); else sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SPI0); From 2753b07269c099844ccd4c21de5790e3f9b8bdbd Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sat, 11 Sep 2021 19:39:16 +0200 Subject: [PATCH 02/14] sunxi: call fdt_fixup_ethernet again to set macaddr for more aliases Sometimes some ethernet aliases do not exist in U-Boot DT but they exist in the DT used to boot the system (for example, modified via DT overlays). In this situation setup_environment is called again in ft_board_setup() to generate macaddr environment variable for them. However now the call to fdt_fixup_ethernet() is moved before the call of ft_board_setup(). Call fdt_fixup_ethernet() again to add MAC addresses for the extra ethernet aliases. Signed-off-by: Icenowy Zheng [updated commit message] Signed-off-by: Jernej Skrabec Signed-off-by: Andre Przywara --- board/sunxi/board.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 2790a0f9e87..d0a93da4092 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -912,10 +912,12 @@ int ft_board_setup(void *blob, struct bd_info *bd) int __maybe_unused r; /* - * Call setup_environment again in case the boot fdt has - * ethernet aliases the u-boot copy does not have. + * Call setup_environment and fdt_fixup_ethernet again + * in case the boot fdt has ethernet aliases the u-boot + * copy does not have. */ setup_environment(blob); + fdt_fixup_ethernet(blob); bluetooth_dt_fixup(blob); From eb31a4a141bf401f92426bd053a965022e47290d Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 7 Jan 2022 11:52:54 -0600 Subject: [PATCH 03/14] i2c: mvtwsi: Add compatible string for allwinner, sun4i-a10-i2c This adds a compatible string for the Allwinner Sun4i-A10 I2C controller. Without this, boards based on the R8 and A13 (at a minimum) fail to boot. Signed-off-by: Chris Morgan Acked-by: Akash Gajjar Signed-off-by: Andre Przywara --- drivers/i2c/mvtwsi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index bad4b1484fd..f48a4f25aae 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -900,6 +900,7 @@ static const struct dm_i2c_ops mvtwsi_i2c_ops = { static const struct udevice_id mvtwsi_i2c_ids[] = { { .compatible = "marvell,mv64xxx-i2c", }, { .compatible = "marvell,mv78230-i2c", }, + { .compatible = "allwinner,sun4i-a10-i2c", }, { .compatible = "allwinner,sun6i-a31-i2c", }, { /* sentinel */ } }; From d0ffd15cffa1467bcc5537d255e0d57d5a1c0128 Mon Sep 17 00:00:00 2001 From: Giulio Benetti Date: Fri, 3 Dec 2021 00:57:54 +0100 Subject: [PATCH 04/14] sunxi: dram_sun4i/5i: use DRAM_MEMORY_TYPE_DDR3 instead of magic number 3 Since DRAM_MEMORY_TYPE_DDR3 is defined let's use it instead of magic number 3. Signed-off-by: Giulio Benetti Signed-off-by: Andre Przywara --- board/sunxi/dram_sun4i_auto.c | 2 +- board/sunxi/dram_sun5i_auto.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c index e8bbee4ee5e..547d1c0cb4d 100644 --- a/board/sunxi/dram_sun4i_auto.c +++ b/board/sunxi/dram_sun4i_auto.c @@ -4,7 +4,7 @@ static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, - .type = 3, + .type = DRAM_MEMORY_TYPE_DDR3, .rank_num = 1, .density = 0, .io_width = 0, diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index a5f4f8b7434..517506ccc4f 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -7,7 +7,7 @@ static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, .mbus_clock = CONFIG_DRAM_MBUS_CLK, - .type = 3, + .type = DRAM_MEMORY_TYPE_DDR3, .rank_num = 1, .density = 0, .io_width = 0, From ac5397a21964f9d6e9206c243d53c615e2562e58 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 20 Oct 2021 23:52:54 -0500 Subject: [PATCH 05/14] sunxi: gpio: Return void from setter functions The return values of these functions are always zero, and they are never checked. Since they are not needed, remove them. Signed-off-by: Samuel Holland Reviewed-by: Heinrich Schuchardt Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/gpio.h | 4 ++-- arch/arm/mach-sunxi/pinmux.c | 8 ++------ 2 files changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index f3ab1aea0ef..2b72b2263b9 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -226,8 +226,8 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); void sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); int sunxi_gpio_get_cfgpin(u32 pin); -int sunxi_gpio_set_drv(u32 pin, u32 val); -int sunxi_gpio_set_pull(u32 pin, u32 val); +void sunxi_gpio_set_drv(u32 pin, u32 val); +void sunxi_gpio_set_pull(u32 pin, u32 val); int sunxi_name_to_gpio(const char *name); #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c index 642483f06c5..cf9d9daf7ca 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/arch/arm/mach-sunxi/pinmux.c @@ -45,7 +45,7 @@ int sunxi_gpio_get_cfgpin(u32 pin) return sunxi_gpio_get_cfgbank(pio, pin); } -int sunxi_gpio_set_drv(u32 pin, u32 val) +void sunxi_gpio_set_drv(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); u32 index = GPIO_DRV_INDEX(pin); @@ -53,11 +53,9 @@ int sunxi_gpio_set_drv(u32 pin, u32 val) struct sunxi_gpio *pio = BANK_TO_GPIO(bank); clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); - - return 0; } -int sunxi_gpio_set_pull(u32 pin, u32 val) +void sunxi_gpio_set_pull(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); u32 index = GPIO_PULL_INDEX(pin); @@ -65,6 +63,4 @@ int sunxi_gpio_set_pull(u32 pin, u32 val) struct sunxi_gpio *pio = BANK_TO_GPIO(bank); clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); - - return 0; } From efdd656659e54049f5a9e31f3ff7c3f42e0e454c Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 20 Oct 2021 23:52:55 -0500 Subject: [PATCH 06/14] sunxi: gpio: Add per-bank drive and pull setters The GPIO and pinctrl drivers need these setters for pin configuration. Since they are DM drivers, they should not be using hardcoded base addresses. Factor out variants of the setter functions which take a pointer to the GPIO bank's MMIO registers. Signed-off-by: Samuel Holland Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/gpio.h | 2 ++ arch/arm/mach-sunxi/pinmux.c | 20 ++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 2b72b2263b9..106605adf5e 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -227,7 +227,9 @@ void sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); int sunxi_gpio_get_cfgpin(u32 pin); void sunxi_gpio_set_drv(u32 pin, u32 val); +void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); void sunxi_gpio_set_pull(u32 pin, u32 val); +void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val); int sunxi_name_to_gpio(const char *name); #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c index cf9d9daf7ca..b2093b623ae 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/arch/arm/mach-sunxi/pinmux.c @@ -48,19 +48,31 @@ int sunxi_gpio_get_cfgpin(u32 pin) void sunxi_gpio_set_drv(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); - u32 index = GPIO_DRV_INDEX(pin); - u32 offset = GPIO_DRV_OFFSET(pin); struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + sunxi_gpio_set_drv_bank(pio, pin, val); +} + +void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val) +{ + u32 index = GPIO_DRV_INDEX(bank_offset); + u32 offset = GPIO_DRV_OFFSET(bank_offset); + clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); } void sunxi_gpio_set_pull(u32 pin, u32 val) { u32 bank = GPIO_BANK(pin); - u32 index = GPIO_PULL_INDEX(pin); - u32 offset = GPIO_PULL_OFFSET(pin); struct sunxi_gpio *pio = BANK_TO_GPIO(bank); + sunxi_gpio_set_pull_bank(pio, pin, val); +} + +void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val) +{ + u32 index = GPIO_PULL_INDEX(bank_offset); + u32 offset = GPIO_PULL_OFFSET(bank_offset); + clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); } From 35ae126c16a6a9149edc6638faaa247f67b8a400 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 20 Oct 2021 23:52:56 -0500 Subject: [PATCH 07/14] gpio: sunxi: Implement .set_flags This, along with gpio_flags_xlate(), allows the GPIO driver to handle pull-up/down flags provided by consumer drivers or in the device tree. Signed-off-by: Samuel Holland Reviewed-by: Simon Glass Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- drivers/gpio/sunxi_gpio.c | 62 +++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 35 deletions(-) diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index caefb1447cb..6c3c10862c4 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -139,27 +139,6 @@ int sunxi_name_to_gpio(const char *name) return ret ? ret : gpio; } -static int sunxi_gpio_direction_input(struct udevice *dev, unsigned offset) -{ - struct sunxi_gpio_plat *plat = dev_get_plat(dev); - - sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT); - - return 0; -} - -static int sunxi_gpio_direction_output(struct udevice *dev, unsigned offset, - int value) -{ - struct sunxi_gpio_plat *plat = dev_get_plat(dev); - u32 num = GPIO_NUM(offset); - - sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); - clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0); - - return 0; -} - static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) { struct sunxi_gpio_plat *plat = dev_get_plat(dev); @@ -172,16 +151,6 @@ static int sunxi_gpio_get_value(struct udevice *dev, unsigned offset) return dat & 0x1; } -static int sunxi_gpio_set_value(struct udevice *dev, unsigned offset, - int value) -{ - struct sunxi_gpio_plat *plat = dev_get_plat(dev); - u32 num = GPIO_NUM(offset); - - clrsetbits_le32(&plat->regs->dat, 1 << num, value ? (1 << num) : 0); - return 0; -} - static int sunxi_gpio_get_function(struct udevice *dev, unsigned offset) { struct sunxi_gpio_plat *plat = dev_get_plat(dev); @@ -205,18 +174,41 @@ static int sunxi_gpio_xlate(struct udevice *dev, struct gpio_desc *desc, if (ret) return ret; desc->offset = args->args[1]; - desc->flags = args->args[2] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0; + desc->flags = gpio_flags_xlate(args->args[2]); + + return 0; +} + +static int sunxi_gpio_set_flags(struct udevice *dev, unsigned int offset, + ulong flags) +{ + struct sunxi_gpio_plat *plat = dev_get_plat(dev); + + if (flags & GPIOD_IS_OUT) { + u32 value = !!(flags & GPIOD_IS_OUT_ACTIVE); + u32 num = GPIO_NUM(offset); + + clrsetbits_le32(&plat->regs->dat, 1 << num, value << num); + sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_OUTPUT); + } else if (flags & GPIOD_IS_IN) { + u32 pull = 0; + + if (flags & GPIOD_PULL_UP) + pull = 1; + else if (flags & GPIOD_PULL_DOWN) + pull = 2; + sunxi_gpio_set_pull_bank(plat->regs, offset, pull); + sunxi_gpio_set_cfgbank(plat->regs, offset, SUNXI_GPIO_INPUT); + } return 0; } static const struct dm_gpio_ops gpio_sunxi_ops = { - .direction_input = sunxi_gpio_direction_input, - .direction_output = sunxi_gpio_direction_output, .get_value = sunxi_gpio_get_value, - .set_value = sunxi_gpio_set_value, .get_function = sunxi_gpio_get_function, .xlate = sunxi_gpio_xlate, + .set_flags = sunxi_gpio_set_flags, }; /** From fb6f67013e3a6d74988615a4bea5f5926ec328d5 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Wed, 20 Oct 2021 23:52:57 -0500 Subject: [PATCH 08/14] mmc: sunxi: Use DM_GPIO flags to set pull-up Now that the sunxi_gpio driver handles pull-up/down via the driver model, pin configuration does not need a platform-specific function. Signed-off-by: Samuel Holland Tested-by: Heinrich Schuchardt Signed-off-by: Andre Przywara --- drivers/mmc/sunxi_mmc.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 4bf8a9b92ce..1bb7b6d0e92 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -702,12 +702,8 @@ static int sunxi_mmc_probe(struct udevice *dev) return ret; /* This GPIO is optional */ - if (!gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, - GPIOD_IS_IN)) { - int cd_pin = gpio_get_number(&priv->cd_gpio); - - sunxi_gpio_set_pull(cd_pin, SUNXI_GPIO_PULL_UP); - } + gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, + GPIOD_IS_IN | GPIOD_PULL_UP); upriv->mmc = &plat->mmc; From 8695b5111c5cf6587e5e97d6e879421fc54dc8d8 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 30 Jan 2022 01:19:42 +0000 Subject: [PATCH 09/14] sunxi: gpio: Fix up pointer arithmetic The calls for flipping bits in the Allwinner pin controller registers were using unnecessarily complex pointer arithmetic. Improve readability by simplifying the expression. Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/pinmux.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c index b2093b623ae..c95fcee9f6c 100644 --- a/arch/arm/mach-sunxi/pinmux.c +++ b/arch/arm/mach-sunxi/pinmux.c @@ -14,7 +14,7 @@ void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val) u32 index = GPIO_CFG_INDEX(bank_offset); u32 offset = GPIO_CFG_OFFSET(bank_offset); - clrsetbits_le32(&pio->cfg[0] + index, 0xf << offset, val << offset); + clrsetbits_le32(&pio->cfg[index], 0xf << offset, val << offset); } void sunxi_gpio_set_cfgpin(u32 pin, u32 val) @@ -31,7 +31,7 @@ int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset) u32 offset = GPIO_CFG_OFFSET(bank_offset); u32 cfg; - cfg = readl(&pio->cfg[0] + index); + cfg = readl(&pio->cfg[index]); cfg >>= offset; return cfg & 0xf; @@ -58,7 +58,7 @@ void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val) u32 index = GPIO_DRV_INDEX(bank_offset); u32 offset = GPIO_DRV_OFFSET(bank_offset); - clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); + clrsetbits_le32(&pio->drv[index], 0x3 << offset, val << offset); } void sunxi_gpio_set_pull(u32 pin, u32 val) @@ -74,5 +74,5 @@ void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val) u32 index = GPIO_PULL_INDEX(bank_offset); u32 offset = GPIO_PULL_OFFSET(bank_offset); - clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); + clrsetbits_le32(&pio->pull[index], 0x3 << offset, val << offset); } From 78592c094e7a81cc099b3f71b05463ddcabe2a73 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Fri, 21 Jan 2022 13:37:31 +0000 Subject: [PATCH 10/14] pmic: axp: define ALDO_IN startup bit Most AXP PMICs feature a "startup source" register, which keeps information about how the PMIC started operation. Bit 0 in there means it has been started by "plugging in the power cable". Define a symbol in each PMIC's header file to be able to use that register and bit later on. Signed-off-by: Andre Przywara --- include/axp152.h | 2 ++ include/axp209.h | 3 ++- include/axp221.h | 3 ++- include/axp305.h | 3 +++ include/axp809.h | 3 ++- include/axp818.h | 3 ++- 6 files changed, 13 insertions(+), 4 deletions(-) diff --git a/include/axp152.h b/include/axp152.h index 10d845fec42..bac6526a362 100644 --- a/include/axp152.h +++ b/include/axp152.h @@ -16,6 +16,8 @@ enum axp152_reg { /* For axp_gpio.c */ #ifdef CONFIG_AXP152_POWER +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_ALDO_IN BIT(0) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x91 #define AXP_GPIO2_CTRL 0x92 diff --git a/include/axp209.h b/include/axp209.h index 30399a8d621..414f88a32c6 100644 --- a/include/axp209.h +++ b/include/axp209.h @@ -76,7 +76,8 @@ enum axp209_reg { /* For axp_gpio.c */ #ifdef CONFIG_AXP209_POWER #define AXP_POWER_STATUS 0x00 -#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) +#define AXP_POWER_STATUS_ALDO_IN BIT(0) +#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) #define AXP_GPIO0_CTRL 0x90 #define AXP_GPIO1_CTRL 0x92 #define AXP_GPIO2_CTRL 0x93 diff --git a/include/axp221.h b/include/axp221.h index a02e9b4f645..8dfcc5b5a23 100644 --- a/include/axp221.h +++ b/include/axp221.h @@ -52,7 +52,8 @@ /* For axp_gpio.c */ #ifdef CONFIG_AXP221_POWER #define AXP_POWER_STATUS 0x00 -#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_POWER_STATUS_ALDO_IN BIT(0) +#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) #define AXP_VBUS_IPSOUT 0x30 #define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) #define AXP_MISC_CTRL 0x8f diff --git a/include/axp305.h b/include/axp305.h index 225c5040a32..0a42bc68042 100644 --- a/include/axp305.h +++ b/include/axp305.h @@ -15,3 +15,6 @@ enum axp305_reg { #define AXP305_OUTPUT_CTRL1_DCDCD_EN (1 << 3) #define AXP305_POWEROFF (1 << 7) + +#define AXP_POWER_STATUS 0x00 +#define AXP_POWER_STATUS_ALDO_IN BIT(0) diff --git a/include/axp809.h b/include/axp809.h index 430dbef622b..8082e402e2a 100644 --- a/include/axp809.h +++ b/include/axp809.h @@ -46,7 +46,8 @@ /* For axp_gpio.c */ #ifdef CONFIG_AXP809_POWER #define AXP_POWER_STATUS 0x00 -#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_POWER_STATUS_ALDO_IN BIT(0) +#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) #define AXP_VBUS_IPSOUT 0x30 #define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) #define AXP_MISC_CTRL 0x8f diff --git a/include/axp818.h b/include/axp818.h index 8bac6b67ca2..8ac517a2bf2 100644 --- a/include/axp818.h +++ b/include/axp818.h @@ -60,7 +60,8 @@ /* For axp_gpio.c */ #ifdef CONFIG_AXP818_POWER #define AXP_POWER_STATUS 0x00 -#define AXP_POWER_STATUS_VBUS_PRESENT (1 << 5) +#define AXP_POWER_STATUS_ALDO_IN BIT(0) +#define AXP_POWER_STATUS_VBUS_PRESENT BIT(5) #define AXP_VBUS_IPSOUT 0x30 #define AXP_VBUS_IPSOUT_DRIVEBUS (1 << 2) #define AXP_MISC_CTRL 0x8f From 52bcc4f053bd25e3508887da01c9e8cddac49b2e Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Fri, 21 Jan 2022 13:37:32 +0000 Subject: [PATCH 11/14] sunxi: Add option to prevent booting on power plug-in For sunxi boards with the AXP209, AXP221, AXP809, and AXP818 PMICs (plus possibly others, I only confirmed the datasheets for these), it is sometimes desirable to not boot whenever the device is plugged in. An example would be when using the NTC CHIP inside a PocketCHIP. This provides a configurable option to check if bit 0 of register 0 of the PMIC says it was powered because of a power button press (0) or a plug-in event (1). If the value is 1 and this option is selected, the device shuts down shortly after printing a message to console stating the reason why it's shutting down. Powering up the board with the power button is not affected. Signed-off-by: Chris Morgan [Andre: reword to speak of boot, remove #ifdefs] Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/Kconfig | 10 ++++++++++ board/sunxi/board.c | 11 +++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index 2c18cf02d1a..d7f9a03152f 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -785,6 +785,16 @@ config AXP_GPIO ---help--- Say Y here to enable support for the gpio pins of the axp PMIC ICs. +config AXP_DISABLE_BOOT_ON_POWERON + bool "Disable device boot on power plug-in" + depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER + default n + ---help--- + Say Y here to prevent the device from booting up because of a plug-in + event. When set, the device will boot into the SPL briefly to + determine why it was powered on, and if it was determined because of + a plug-in event instead of a button press event it will shut back off. + config VIDEO_SUNXI bool "Enable graphical uboot console on HDMI, LCD or VGA" depends on !MACH_SUN8I_A83T diff --git a/board/sunxi/board.c b/board/sunxi/board.c index d0a93da4092..91463009b01 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include #include @@ -602,6 +603,16 @@ void sunxi_board_init(void) defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER power_failed = axp_init(); + if (IS_ENABLED(CONFIG_AXP_DISABLE_BOOT_ON_POWERON) && !power_failed) { + u8 boot_reason; + + pmic_bus_read(AXP_POWER_STATUS, &boot_reason); + if (boot_reason & AXP_POWER_STATUS_ALDO_IN) { + printf("Power on by plug-in, shutting down.\n"); + pmic_bus_write(0x32, BIT(7)); + } + } + #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \ defined CONFIG_AXP818_POWER power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT); From 18a59276983903ea4364d2945c880a62392e4e34 Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 29 Jan 2022 16:58:42 +0100 Subject: [PATCH 12/14] sunxi: fix H616 DRAM ODT support Kconfig symbol is missing CONFIG_ prefix, so compiler will always skip ODT configuration. Fix symbol name. Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support") Signed-off-by: Jernej Skrabec Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index acdfb3ceef8..76f520f4e78 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -720,7 +720,7 @@ static bool mctl_phy_init(struct dram_para *para) writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x3dc); writel(0x80, SUNXI_DRAM_PHY0_BASE + 0x45c); - if (IS_ENABLED(DRAM_ODT_EN)) + if (IS_ENABLED(CONFIG_DRAM_ODT_EN)) mctl_phy_configure_odt(); clrsetbits_le32(SUNXI_DRAM_PHY0_BASE + 4, 7, 0xa); From e97943b732d0e0588cfab3a8cb53459ca14dc81d Mon Sep 17 00:00:00 2001 From: Jernej Skrabec Date: Sat, 29 Jan 2022 16:58:43 +0100 Subject: [PATCH 13/14] sunxi: Fix H616 DRAM read calibration for dual rank Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that it has to be set before read calibration and cleared afterwards. This is already done for first rank, but not for second (copy & paste error.) Fix it. Fixes: f4317dbd06b6 ("sunxi: Add H616 DRAM support") Signed-off-by: Jernej Skrabec Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/mach-sunxi/dram_sun50i_h616.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 76f520f4e78..83e8abc2f8d 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -360,7 +360,7 @@ static bool mctl_phy_read_calibration(struct dram_para *para) } } - setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); + clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 1); } clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 0x30); From 50d5c6428fc280c095b0edd1a612b3661b5db77d Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Tue, 12 Oct 2021 19:21:27 -0500 Subject: [PATCH 14/14] mkimage: sunxi_egon: Allow overriding the padding size Due to a bug in the H3 SoC, where the CPU 0 hotplug flag cannot be written, resuming CPU 0 requires using the "Super Standby" code path in the BROM instead of the hotplug path. This path requires jumping to an eGON image in SRAM. This resume image, whose single purpose is to jump back to the secure monitor, only needs to contain a single instruction. Padding the image to 8 KiB would be wasteful of SRAM. Hook up the -B (block size) option so users can set the block/padding size. Signed-off-by: Samuel Holland Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- tools/sunxi_egon.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c index a5299eb6a11..d1398c07fb0 100644 --- a/tools/sunxi_egon.c +++ b/tools/sunxi_egon.c @@ -10,9 +10,10 @@ /* * NAND requires 8K padding. SD/eMMC gets away with 512 bytes, - * but let's use the larger padding to cover both. + * but let's use the larger padding by default to cover both. */ #define PAD_SIZE 8192 +#define PAD_SIZE_MIN 512 static int egon_check_params(struct image_tool_params *params) { @@ -114,10 +115,12 @@ static int egon_check_image_type(uint8_t type) static int egon_vrec_header(struct image_tool_params *params, struct image_type_params *tparams) { + int pad_size = ALIGN(params->bl_len ?: PAD_SIZE, PAD_SIZE_MIN); + tparams->hdr = calloc(sizeof(struct boot_file_head), 1); - /* Return padding to 8K blocks. */ - return ALIGN(params->file_size, PAD_SIZE) - params->file_size; + /* Return padding to complete blocks. */ + return ALIGN(params->file_size, pad_size) - params->file_size; } U_BOOT_IMAGE_TYPE(