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ppc4xx: Fix GPIO configuration for pcs440ep

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The SRD0_PFC0 register was not configured correctly to enable the GPIO's
49-63 for GPIO. They have been configured as trace signals. This patch
fixes this by clearing the corresponding bit.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-01-30 15:35:50 +01:00
parent 28d77d968b
commit e1d1429b49
1 changed files with 1 additions and 1 deletions
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2
board/pcs440ep/pcs440ep.c
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@ -175,7 +175,7 @@ int board_early_init_f(void)
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00000100); /* Pin function: enable GPIO49-63 */
mtsdr(sdr_pfc0, 0x00000000); /* Pin function: enable GPIO49-63 */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins, select IRQ5 */
return 0;