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mpc83xx: cosmetic: TQM834x.h checkpatch compliance
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger
Kim Phillips
parent
bb0f5bc92d
commit
df939e1647
@ -66,26 +66,27 @@
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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/* DDR is system memory*/
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#define CONFIG_SYS_DDR_BASE 0x00000000
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
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#undef CONFIG_DDR_ECC /* only for ECC DDR module */
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#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
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#define DDR_CASLAT_25 /* CASLAT set to 2.5 */
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#undef CONFIG_DDR_ECC /* only for ECC DDR module */
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#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00100000
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
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#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */
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#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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/*
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@ -93,34 +94,41 @@
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*/
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/*
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* When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of Flash
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* banks has to be determined at runtime and stored in a gloabl variable
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* tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is only
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* used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array flash_info, and
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* should be made sufficiently large to accomodate the number of banks that
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* might actually be detected. Since most (all?) Flash related functions use
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* CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on the board, it is
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* defined as tqm834x_num_flash_banks.
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* When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of
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* Flash banks has to be determined at runtime and stored in a gloabl variable
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* tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is
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* only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array
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* flash_info, and should be made sufficiently large to accomodate the number
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* of banks that might actually be detected. Since most (all?) Flash related
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* functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on
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* the board, it is defined as tqm834x_num_flash_banks.
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */
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/* 32 bit device at 0x80000000 via GPCM (0x8000_1801) */
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) | \
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BR_MS_GPCM | BR_PS_32 | BR_V)
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#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA) \
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| BR_MS_GPCM \
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| BR_PS_32 \
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| BR_V)
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/* FLASH timing (0x0000_0c54) */
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \
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OR_GPCM_SCY_5 | OR_GPCM_TRLX)
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#define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT \
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| OR_GPCM_ACS_DIV4 \
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| OR_GPCM_SCY_5 \
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| OR_GPCM_TRLX)
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#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \
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| CONFIG_SYS_OR_TIMING_FLASH)
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */
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/* 1 GiB window size (2^(size + 1)) */
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
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/* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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/* disable remaining mappings */
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#define CONFIG_SYS_BR1_PRELIM 0x00000000
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@ -150,14 +158,17 @@
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#endif
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
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/* Reserve 384 kB = 3 sect. for Mon */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
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/* Reserve 512 kB for malloc */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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/*
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* Serial Port
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@ -169,7 +180,7 @@
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
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@ -177,30 +188,30 @@
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/*
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* I2C
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*/
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_FSL_I2C
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed: 400KHz */
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#define CONFIG_SYS_I2C_SLAVE 0x7F /* slave address */
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#define CONFIG_SYS_I2C_OFFSET 0x3000
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/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes per write */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
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#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */
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#define CONFIG_SYS_I2C_MULTI_EEPROMS /* more than one eeprom */
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/* I2C RTC */
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#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/* I2C SYSMON (LM75) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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/*
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* TSEC
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@ -209,9 +220,9 @@
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#define CONFIG_MII
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET)
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#if defined(CONFIG_TSEC_ENET)
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@ -219,15 +230,15 @@
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#define CONFIG_TSEC1_NAME "TSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "TSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "TSEC0"
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#define CONFIG_ETHPRIME "TSEC0"
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#endif /* CONFIG_TSEC_ENET */
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@ -239,19 +250,20 @@
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#if defined(CONFIG_PCI)
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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/* PCI1 host bridge */
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#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
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#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
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#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
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#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000
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#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
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#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_MMIO_BASE \
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(CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE)
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#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
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#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
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#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
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#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */
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#undef CONFIG_EEPRO100
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#define CONFIG_EEPRO100
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@ -270,15 +282,16 @@
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/*
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* Environment
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
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#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */
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#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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@ -319,30 +332,32 @@
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#endif
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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@ -354,7 +369,8 @@
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/
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/* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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#define CONFIG_SYS_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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@ -375,7 +391,7 @@
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_TSEC1M_IN_GMII |\
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HRCWH_TSEC2M_IN_GMII )
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HRCWH_TSEC2M_IN_GMII)
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#else
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#define CONFIG_SYS_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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@ -388,7 +404,7 @@
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_TSEC1M_IN_GMII |\
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HRCWH_TSEC2M_IN_GMII )
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HRCWH_TSEC2M_IN_GMII)
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#endif
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/* System IO Config */
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@ -404,23 +420,55 @@
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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/* DDR 0 - 512M */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
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| BATU_BL_256M \
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| BATU_VS \
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| BATU_VP)
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
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| BATL_PP_10 \
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| BATL_MEMCOHERENCE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 \
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| BATU_BL_256M \
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| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
/* stack in DCACHE @ 512M (no backing mem) */
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR \
|
||||
| BATL_PP_10 \
|
||||
| BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR \
|
||||
| BATU_BL_128K \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
/* PCI */
|
||||
#ifdef CONFIG_PCI
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE \
|
||||
| BATL_PP_10 \
|
||||
| BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE \
|
||||
| BATL_PP_10 \
|
||||
| BATL_MEMCOHERENCE \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE \
|
||||
| BATL_PP_10 \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE \
|
||||
| BATU_BL_16M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
#else
|
||||
#define CONFIG_SYS_IBAT3L (0)
|
||||
#define CONFIG_SYS_IBAT3U (0)
|
||||
@ -431,12 +479,24 @@
|
||||
#endif
|
||||
|
||||
/* IMMRBAR */
|
||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR \
|
||||
| BATL_PP_10 \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR \
|
||||
| BATU_BL_1M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
/* FLASH */
|
||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE \
|
||||
| BATL_PP_10 \
|
||||
| BATL_CACHEINHIBIT \
|
||||
| BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE \
|
||||
| BATU_BL_256M \
|
||||
| BATU_VS \
|
||||
| BATU_VP)
|
||||
|
||||
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
|
||||
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
|
||||
@ -464,10 +524,11 @@
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_LOADADDR 400000 /* default location for tftp and bootm */
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 400000
|
||||
|
||||
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
@ -486,7 +547,7 @@
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
|
||||
"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
|
||||
"flash_nfs_old=run nfsargs addip addcons;" \
|
||||
"bootm ${kernel_addr}\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
@ -530,8 +591,8 @@
|
||||
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
|
||||
|
||||
/* default mtd partition table */
|
||||
#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
|
||||
"1m(kernel),2m(initrd),"\
|
||||
"-(user);"\
|
||||
#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env)," \
|
||||
"1m(kernel),2m(initrd)," \
|
||||
"-(user);" \
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user