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ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c

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The new boardspecific DDR2 controller configuration is used for the Yucca
board. Now the Yucca board with 440SPe Rev. A chips is also supported.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-07-16 10:00:43 +02:00
parent 6ed14addf9
commit df3f17422a
1 changed files with 34 additions and 0 deletions
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34
board/amcc/yucca/yucca.c
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@ -562,6 +562,40 @@ int checkboard (void)
return 0;
}
/*
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
static int ppc440spe_rev_a(void)
{
if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA))
return 1;
else
return 0;
}
u32 ddr_wrdtr(u32 default_val) {
/*
* Yucca boards with 440SPe rev. A need a slightly different setup
* for the MCIF0_WRDTR register.
*/
if (ppc440spe_rev_a())
return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV);
return default_val;
}
u32 ddr_clktr(u32 default_val) {
/*
* Yucca boards with 440SPe rev. A need a slightly different setup
* for the MCIF0_CLKTR register.
*/
if (ppc440spe_rev_a())
return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
return default_val;
}
#if defined(CFG_DRAM_TEST)
int testdram (void)
{