mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-24 04:34:22 +08:00
arm: Remove titanium board
This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
80b386abe3
commit
defd0dcfb9
@ -542,10 +542,6 @@ config TARGET_TBS2910
|
||||
bool "TBS2910 Matrix ARM mini PC"
|
||||
depends on MX6Q
|
||||
|
||||
config TARGET_TITANIUM
|
||||
bool "titanium"
|
||||
depends on MX6Q
|
||||
|
||||
config TARGET_KP_IMX6Q_TPC
|
||||
bool "K+P KP_IMX6Q_TPC i.MX6 Quad"
|
||||
depends on MX6QDL
|
||||
@ -644,7 +640,6 @@ source "board/ge/bx50v3/Kconfig"
|
||||
source "board/ge/b1x5v2/Kconfig"
|
||||
source "board/aristainetos/Kconfig"
|
||||
source "board/armadeus/opos6uldev/Kconfig"
|
||||
source "board/barco/titanium/Kconfig"
|
||||
source "board/boundary/nitrogen6x/Kconfig"
|
||||
source "board/bticino/mamoj/Kconfig"
|
||||
source "board/compulab/cm_fx6/Kconfig"
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
if TARGET_TITANIUM
|
||||
|
||||
config SYS_BOARD
|
||||
default "titanium"
|
||||
|
||||
config SYS_VENDOR
|
||||
default "barco"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "titanium"
|
||||
|
||||
endif
|
||||
@ -1,6 +0,0 @@
|
||||
TITANIUM BOARD
|
||||
M: Stefan Roese <sr@denx.de>
|
||||
S: Maintained
|
||||
F: board/barco/titanium/
|
||||
F: include/configs/titanium.h
|
||||
F: configs/titanium_defconfig
|
||||
@ -1,7 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
|
||||
#
|
||||
# (C) Copyright 2011 Freescale Semiconductor, Inc.
|
||||
|
||||
obj-y := titanium.o
|
||||
@ -1,166 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Projectiondesign AS
|
||||
* Derived from ./board/freescale/mx6qsabrelite/imximage.cfg
|
||||
*
|
||||
* Copyright (C) 2011 Freescale Semiconductor, Inc.
|
||||
* Jason Liu <r64343@freescale.com>
|
||||
*
|
||||
* Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
|
||||
* and create imximage boot image
|
||||
*
|
||||
* The syntax is taken as close as possible with the kwbimage
|
||||
*/
|
||||
|
||||
/* image version */
|
||||
|
||||
IMAGE_VERSION 2
|
||||
|
||||
/*
|
||||
* Boot Device : one of
|
||||
* sd, nand
|
||||
*/
|
||||
BOOT_FROM nand
|
||||
|
||||
/*
|
||||
* Device Configuration Data (DCD)
|
||||
*
|
||||
* Each entry must have the format:
|
||||
* Addr-type Address Value
|
||||
*
|
||||
* where:
|
||||
* Addr-type register length (1,2 or 4 bytes)
|
||||
* Address absolute address of the register
|
||||
* value value to be stored in the register
|
||||
*/
|
||||
|
||||
#define __ASSEMBLY__
|
||||
#include <config.h>
|
||||
#include "asm/arch/mx6-ddr.h"
|
||||
#include "asm/arch/iomux.h"
|
||||
#include "asm/arch/crm_regs.h"
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030
|
||||
DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_DQM0, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM1, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM2, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM3, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM4, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM5, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM6, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_DQM7, 0x00020030
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_CAS, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_RAS, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_RESET, 0x00020030
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
|
||||
DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
|
||||
|
||||
DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030
|
||||
DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030
|
||||
|
||||
DATA 4, MX6_IOM_GRP_B0DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B1DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B2DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B3DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B4DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B5DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B6DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_B7DS, 0x00000030
|
||||
DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030
|
||||
|
||||
/* (differential input) */
|
||||
DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
|
||||
/* disable ddr pullups */
|
||||
DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
|
||||
/* (differential input) */
|
||||
DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
|
||||
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
|
||||
DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030
|
||||
/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
|
||||
DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000
|
||||
|
||||
/* Read data DQ Byte0-3 delay */
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
|
||||
DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
|
||||
|
||||
/*
|
||||
* MDMISC mirroring interleaved (row/bank/col)
|
||||
*/
|
||||
DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740
|
||||
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
|
||||
DATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975
|
||||
DATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64
|
||||
DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
|
||||
DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2
|
||||
DATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21
|
||||
DATA 4, MX6_MMDC_P0_MDOTC, 0x09444040
|
||||
DATA 4, MX6_MMDC_P0_MDPDC, 0x00025576
|
||||
DATA 4, MX6_MMDC_P0_MDASP, 0x00000017
|
||||
DATA 4, MX6_MMDC_P0_MDCTL, 0x83190000
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04088032
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408030
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x09408038
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048
|
||||
DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003
|
||||
DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003
|
||||
DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
|
||||
DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350
|
||||
DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350
|
||||
DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348
|
||||
DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B
|
||||
DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341
|
||||
DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933
|
||||
DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
|
||||
DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044
|
||||
DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044
|
||||
DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
|
||||
DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000
|
||||
DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
|
||||
|
||||
/* set the default clock gate to save power */
|
||||
DATA 4, CCM_CCGR0, 0x00C03F3F
|
||||
DATA 4, CCM_CCGR1, 0x0030FC03
|
||||
DATA 4, CCM_CCGR2, 0x0FFFC000
|
||||
DATA 4, CCM_CCGR3, 0x3FF00000
|
||||
DATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */
|
||||
DATA 4, CCM_CCGR5, 0x0F0000C3
|
||||
DATA 4, CCM_CCGR6, 0x000003FF
|
||||
|
||||
/* enable AXI cache for VDOA/VPU/IPU */
|
||||
DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
|
||||
/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
|
||||
DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
|
||||
DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
|
||||
@ -1,320 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2013 Stefan Roese <sr@denx.de>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <net.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/clock.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
#include <asm/arch/iomux.h>
|
||||
#include <asm/arch/mx6-pins.h>
|
||||
#include <asm/arch/crm_regs.h>
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/mach-imx/iomux-v3.h>
|
||||
#include <asm/mach-imx/mxc_i2c.h>
|
||||
#include <asm/mach-imx/boot_mode.h>
|
||||
#include <mmc.h>
|
||||
#include <fsl_esdhc_imx.h>
|
||||
#include <micrel.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
|
||||
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
|
||||
|
||||
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
|
||||
|
||||
#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
|
||||
PAD_CTL_ODE | PAD_CTL_SRE_FAST)
|
||||
|
||||
int dram_init(void)
|
||||
{
|
||||
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
iomux_v3_cfg_t const uart1_pads[] = {
|
||||
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const uart2_pads[] = {
|
||||
MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const uart4_pads[] = {
|
||||
MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
|
||||
|
||||
struct i2c_pads_info i2c_pad_info0 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
|
||||
.gp = IMX_GPIO_NR(5, 27)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
|
||||
.gp = IMX_GPIO_NR(5, 26)
|
||||
}
|
||||
};
|
||||
|
||||
struct i2c_pads_info i2c_pad_info2 = {
|
||||
.scl = {
|
||||
.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
|
||||
.gp = IMX_GPIO_NR(1, 3)
|
||||
},
|
||||
.sda = {
|
||||
.i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
|
||||
.gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
|
||||
.gp = IMX_GPIO_NR(7, 11)
|
||||
}
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const usdhc3_pads[] = {
|
||||
MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
|
||||
MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads1[] = {
|
||||
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
/* pin 35 - 1 (PHY_AD2) on reset */
|
||||
MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 32 - 1 - (MODE0) all */
|
||||
MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 31 - 1 - (MODE1) all */
|
||||
MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 28 - 1 - (MODE2) all */
|
||||
MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 27 - 1 - (MODE3) all */
|
||||
MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
|
||||
MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
/* pin 42 PHY nRST */
|
||||
MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t const enet_pads2[] = {
|
||||
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
|
||||
};
|
||||
|
||||
iomux_v3_cfg_t nfc_pads[] = {
|
||||
MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_gpmi_nand(void)
|
||||
{
|
||||
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
|
||||
|
||||
/* config gpmi nand iomux */
|
||||
imx_iomux_v3_setup_multiple_pads(nfc_pads,
|
||||
ARRAY_SIZE(nfc_pads));
|
||||
|
||||
/* config gpmi and bch clock to 100 MHz */
|
||||
clrsetbits_le32(&mxc_ccm->cs2cdr,
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
|
||||
MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
|
||||
|
||||
/* enable gpmi and bch clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR4,
|
||||
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
|
||||
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
|
||||
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
|
||||
|
||||
/* enable apbh clock gating */
|
||||
setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
|
||||
}
|
||||
|
||||
static void setup_iomux_enet(void)
|
||||
{
|
||||
gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
|
||||
gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
|
||||
|
||||
/* Need delay 10ms according to KSZ9021 spec */
|
||||
udelay(1000 * 10);
|
||||
gpio_set_value(IMX_GPIO_NR(3, 23), 1);
|
||||
|
||||
imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
|
||||
}
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
|
||||
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_MX6
|
||||
int board_ehci_hcd_init(int port)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_ESDHC_IMX
|
||||
struct fsl_esdhc_cfg usdhc_cfg[1] = {
|
||||
{ USDHC3_BASE_ADDR },
|
||||
};
|
||||
|
||||
int board_mmc_getcd(struct mmc *mmc)
|
||||
{
|
||||
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
|
||||
|
||||
if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
|
||||
gpio_direction_input(IMX_GPIO_NR(7, 0));
|
||||
return !gpio_get_value(IMX_GPIO_NR(7, 0));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_mmc_init(struct bd_info *bis)
|
||||
{
|
||||
/*
|
||||
* Only one USDHC controller on titianium
|
||||
*/
|
||||
imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
|
||||
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
|
||||
|
||||
return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
/* min rx data delay */
|
||||
ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
|
||||
/* min tx data delay */
|
||||
ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
|
||||
/* max rx/tx clock delay, min rx/tx control */
|
||||
ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
setup_iomux_enet();
|
||||
|
||||
return cpu_eth_init(bis);
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
|
||||
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
|
||||
setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
|
||||
|
||||
setup_gpmi_nand();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: Titanium\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
static const struct boot_mode board_boot_modes[] = {
|
||||
/* NAND */
|
||||
{ "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
|
||||
/* 4 bit bus width */
|
||||
{ "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
|
||||
{ "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
|
||||
{ NULL, 0 },
|
||||
};
|
||||
#endif
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_CMD_BMODE
|
||||
add_board_boot_modes(board_boot_modes);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -1,55 +0,0 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MX6=y
|
||||
CONFIG_SYS_TEXT_BASE=0x17800000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0x1000000
|
||||
CONFIG_MX6Q=y
|
||||
CONFIG_TARGET_TITANIUM=y
|
||||
CONFIG_ENV_OFFSET_REDUND=0x1080000
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/barco/titanium/imximage.cfg"
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_MISC_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_PROMPT="Titanium > "
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND_TRIMFFS=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_FS_GENERIC=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=gpmi-nand:16M(uboot),512k(env1),512k(env2),-(ubi)"
|
||||
CONFIG_CMD_UBI=y
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_BOUNCE_BUFFER=y
|
||||
CONFIG_FSL_USDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_MXS=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_MICREL=y
|
||||
CONFIG_PHY_MICREL_KSZ90X1=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_MXC_UART=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
@ -1,151 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2013 Stefan Roese <sr@denx.de>
|
||||
*
|
||||
* Configuration settings for the ProjectionDesign / Barco
|
||||
* Titanium board.
|
||||
*
|
||||
* Based on mx6qsabrelite.h which is:
|
||||
* Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include "mx6_common.h"
|
||||
|
||||
/* Provide the MACH_TYPE value that the vendor kernel requires. */
|
||||
#define CONFIG_MACH_TYPE 3769
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
|
||||
|
||||
#define CONFIG_MXC_UART_BASE UART1_BASE
|
||||
|
||||
/* I2C Configs */
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_MXC
|
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
|
||||
#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* MMC Configs */
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1
|
||||
|
||||
#define CONFIG_FEC_MXC
|
||||
#define IMX_FEC_BASE ENET_BASE_ADDR
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define CONFIG_FEC_MXC_PHYADDR 4
|
||||
|
||||
/* USB Configs */
|
||||
#define CONFIG_MXC_USB_PORT 1
|
||||
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
|
||||
#define CONFIG_MXC_USB_FLAGS 0
|
||||
|
||||
#define CONFIG_HOSTNAME "titanium"
|
||||
#define CONFIG_UBI_PART ubi
|
||||
#define CONFIG_UBIFS_VOLUME rootfs0
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"kernel=" CONFIG_HOSTNAME "/uImage\0" \
|
||||
"kernel_fs=/boot/uImage\0" \
|
||||
"kernel_addr=11000000\0" \
|
||||
"dtb=" CONFIG_HOSTNAME "/" \
|
||||
CONFIG_HOSTNAME ".dtb\0" \
|
||||
"dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \
|
||||
"dtb_addr=12800000\0" \
|
||||
"script=boot.scr\0" \
|
||||
"uimage=uImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"baudrate=115200\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"mmcdev=0\0" \
|
||||
"mmcpart=1\0" \
|
||||
"uimage=uImage\0" \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
|
||||
" ${script}\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; source\0" \
|
||||
"loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
|
||||
"mmcroot=/dev/mmcblk0p2\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot} rootwait rw\0" \
|
||||
"bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \
|
||||
" ${uimage}; bootm\0" \
|
||||
"addip=setenv bootargs ${bootargs} " \
|
||||
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||
":${hostname}:${netdev}:off panic=1\0" \
|
||||
"addcon=setenv bootargs ${bootargs} console=ttymxc0," \
|
||||
"${baudrate}\0" \
|
||||
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
|
||||
"rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=${serverip}:${rootpath}\0" \
|
||||
"ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \
|
||||
"part=" __stringify(CONFIG_UBI_PART) "\0" \
|
||||
"boot_vol=0\0" \
|
||||
"vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
|
||||
"load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
|
||||
"update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
|
||||
" ${filesize}\0" \
|
||||
"upd_ubifs=run load_ubifs update_ubifs\0" \
|
||||
"init_ubi=nand erase.part ubi;ubi part ${part};" \
|
||||
"ubi create ${vol} c800000\0" \
|
||||
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
|
||||
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
|
||||
"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
|
||||
" addcon addmtd;" \
|
||||
"bootm ${kernel_addr} - ${dtb_addr}\0" \
|
||||
"ubifsargs=set bootargs ubi.mtd=ubi " \
|
||||
"root=ubi:rootfs${boot_vol} rootfstype=ubifs\0" \
|
||||
"ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0" \
|
||||
"ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
|
||||
"ubifsload ${dtb_addr} ${dtb_fs};\0" \
|
||||
"nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
|
||||
"addmtd;bootm ${kernel_addr} - ${dtb_addr}\0" \
|
||||
"load_kernel=tftp ${kernel_addr} ${kernel}\0" \
|
||||
"load_dtb=tftp ${dtb_addr} ${dtb}\0" \
|
||||
"net_nfs=run load_dtb load_kernel; " \
|
||||
"run nfsargs addip addcon addmtd;" \
|
||||
"bootm ${kernel_addr} - ${dtb_addr}\0" \
|
||||
"delenv=env default -a -f; saveenv; reset\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND "run nand_ubifs"
|
||||
|
||||
/* Physical Memory Map */
|
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
|
||||
#define PHYS_SDRAM_SIZE (512 << 20)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
|
||||
|
||||
/* Enable NAND support */
|
||||
#ifdef CONFIG_CMD_NAND
|
||||
|
||||
/* NAND stuff */
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BASE 0x40000000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* DMA stuff, needed for GPMI/MXS NAND support */
|
||||
|
||||
/* Environment in NAND */
|
||||
|
||||
#else /* CONFIG_CMD_NAND */
|
||||
|
||||
/* Environment in MMC */
|
||||
|
||||
#endif /* CONFIG_CMD_NAND */
|
||||
|
||||
/* UBI/UBIFS config options */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user