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da850/omap-l138: Fix NAND flash timings

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Though Commit id a3f88293dd (da850evm:
setup the NAND flash timings) has configured the AEMIF timings, they
are not exactly in sync with the timings used in Linux. Linux is
configuring the timing register as 0x08222204, where as currently it
configured to 0x00100084 in U-Boot. This issue was found out when
support for NAND SPL is added in U-Boot. Without this patch U-Boot
does not come up with SPL.

Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
This commit is contained in:
Lad, Prabhakar 2012-06-24 21:35:21 +00:00 committed by Albert ARIBAUD
parent 0d986e61e2
commit de94b80d3c
1 changed files with 5 additions and 5 deletions
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10
board/davinci/da8xxevm/da850evm.c
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@ -348,11 +348,11 @@ int board_init(void)
* NAND CS setup - cycle counts based on da850evm NAND timings in the
* Linux kernel @ 25MHz EMIFA
*/
writel((DAVINCI_ABCR_WSETUP(0) |
DAVINCI_ABCR_WSTROBE(1) |
DAVINCI_ABCR_WHOLD(0) |
DAVINCI_ABCR_RSETUP(0) |
DAVINCI_ABCR_RSTROBE(1) |
writel((DAVINCI_ABCR_WSETUP(2) |
DAVINCI_ABCR_WSTROBE(2) |
DAVINCI_ABCR_WHOLD(1) |
DAVINCI_ABCR_RSETUP(1) |
DAVINCI_ABCR_RSTROBE(4) |
DAVINCI_ABCR_RHOLD(0) |
DAVINCI_ABCR_TA(1) |
DAVINCI_ABCR_ASIZE_8BIT),