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arm: socfpga: Add watchdog disable for socfpga

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This adds watchdog disable. It is neccessary for running Linux kernel.

Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>

V2: Move RSTMGR_PERMODRST_L4WD0_LSB to reset_manager.h
    Reset watchdog only if CONFIG_HW_WATCHDOG is undefined (the default)
This commit is contained in:
Pavel Machek 2014-09-09 14:03:28 +02:00 committed by Marek Vasut
parent be324354ee
commit de6da9255a
3 changed files with 30 additions and 0 deletions
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14
arch/arm/cpu/armv7/socfpga/misc.c
View File

@ -8,6 +8,7 @@
#include <asm/io.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/reset_manager.h>
DECLARE_GLOBAL_DATA_PTR;
@ -36,6 +37,19 @@ int overwrite_console(void)
}
#endif
int arch_cpu_init(void)
{
/*
* If the HW watchdog is NOT enabled, make sure it is not running,
* for example because it was enabled in the preloader. This might
* trigger a watchdog-triggered reboot of Linux kernel later.
*/
#ifndef CONFIG_HW_WATCHDOG
socfpga_watchdog_reset();
#endif
return 0;
}
int misc_init_r(void)
{
return 0;

12
arch/arm/cpu/armv7/socfpga/reset_manager.c
View File

@ -14,6 +14,18 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS;
/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
void socfpga_watchdog_reset(void)
{
/* assert reset for watchdog */
setbits_le32(&reset_manager_base->per_mod_reset,
1 << RSTMGR_PERMODRST_L4WD0_LSB);
/* deassert watchdog from reset (watchdog in not running state) */
clrbits_le32(&reset_manager_base->per_mod_reset,
1 << RSTMGR_PERMODRST_L4WD0_LSB);
}
/*
* Write the reset manager register to cause reset
*/

4
arch/arm/include/asm/arch-socfpga/reset_manager.h
View File

@ -10,6 +10,8 @@
void reset_cpu(ulong addr);
void reset_deassert_peripherals_handoff(void);
void socfpga_watchdog_reset(void);
struct socfpga_reset_manager {
u32 status;
u32 ctrl;
@ -27,4 +29,6 @@ struct socfpga_reset_manager {
#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
#endif
#define RSTMGR_PERMODRST_L4WD0_LSB 6
#endif /* _RESET_MANAGER_H_ */