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mx5: Optimize lowlevel_init code size
Optimize mx5 lowlevel_init.S code size: - Compute values at compile time rather than at runtime where possible. - Assign r4 to hold the zero value rather than setting registers to 0 again and again. - Associate a function to setup_pll rather than expanding its large macro code multiple times. - Allocate constant values in section only if used. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Stefano Babic <sbabic@denx.de> Tested-by: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Benoît Thébaudeau
Tom Rini
parent
51535d9f6f
commit
dd227b6ea0
@ -24,6 +24,8 @@
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#include <generated/asm-offsets.h>
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#include <linux/linkage.h>
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.section ".text.init", "x"
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/*
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* L2CC Cache setup/invalidation/disable
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*/
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@ -34,15 +36,14 @@
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mcr 15, 0, r0, c1, c0, 1
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/* reconfigure L2 cache aux control reg */
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mov r0, #0xC0 /* tag RAM */
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add r0, r0, #0x4 /* data RAM */
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orr r0, r0, #1 << 24 /* disable write allocate delay */
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orr r0, r0, #1 << 23 /* disable write allocate combine */
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orr r0, r0, #1 << 22 /* disable write allocate */
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ldr r0, =0xC0 | /* tag RAM */ \
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0x4 | /* data RAM */ \
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1 << 24 | /* disable write allocate delay */ \
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1 << 23 | /* disable write allocate combine */ \
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1 << 22 /* disable write allocate */
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#if defined(CONFIG_MX51)
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ldr r1, =0x0
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ldr r3, [r1, #ROM_SI_REV]
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ldr r3, [r4, #ROM_SI_REV]
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cmp r3, #0x10
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/* disable write combine for TO 2 and lower revs */
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@ -84,8 +85,7 @@
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ldr r1, =0x00000203
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str r1, [r0, #0x40]
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ldr r1, =0x0
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str r1, [r0, #0x44]
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str r4, [r0, #0x44]
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ldr r1, =0x00120125
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str r1, [r0, #0x9C]
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@ -98,20 +98,29 @@
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.macro setup_pll pll, freq
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ldr r0, =\pll
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adr r2, W_DP_\freq
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bl setup_pll_func
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.endm
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#define W_DP_OP 0
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#define W_DP_MFD 4
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#define W_DP_MFN 8
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setup_pll_func:
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ldr r1, =0x00001232
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str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
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mov r1, #0x2
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str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
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ldr r1, W_DP_OP_\freq
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ldr r1, [r2, #W_DP_OP]
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str r1, [r0, #PLL_DP_OP]
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str r1, [r0, #PLL_DP_HFS_OP]
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ldr r1, W_DP_MFD_\freq
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ldr r1, [r2, #W_DP_MFD]
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str r1, [r0, #PLL_DP_MFD]
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str r1, [r0, #PLL_DP_HFS_MFD]
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ldr r1, W_DP_MFN_\freq
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ldr r1, [r2, #W_DP_MFN]
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str r1, [r0, #PLL_DP_MFN]
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str r1, [r0, #PLL_DP_HFS_MFN]
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@ -120,12 +129,13 @@
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1: ldr r1, [r0, #PLL_DP_CTL]
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ands r1, r1, #0x1
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beq 1b
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.endm
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/* r10 saved upper lr */
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mov pc, lr
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.macro setup_pll_errata pll, freq
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ldr r2, =\pll
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mov r1, #0x0
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str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
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str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
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ldr r1, =0x00001236
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str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
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1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
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@ -158,10 +168,9 @@
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/* Gate of clocks to the peripherals first */
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ldr r1, =0x3FFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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ldr r1, =0x0
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str r1, [r0, #CLKCTL_CCGR1]
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str r1, [r0, #CLKCTL_CCGR2]
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str r1, [r0, #CLKCTL_CCGR3]
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str r4, [r0, #CLKCTL_CCGR1]
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str r4, [r0, #CLKCTL_CCGR2]
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str r4, [r0, #CLKCTL_CCGR3]
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ldr r1, =0x00030000
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str r1, [r0, #CLKCTL_CCGR4]
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@ -184,11 +193,10 @@
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#else
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ldr r1, =0x3FFFFFFF
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str r1, [r0, #CLKCTL_CCGR0]
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ldr r1, =0x0
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str r1, [r0, #CLKCTL_CCGR1]
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str r1, [r0, #CLKCTL_CCGR2]
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str r1, [r0, #CLKCTL_CCGR3]
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str r1, [r0, #CLKCTL_CCGR7]
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str r4, [r0, #CLKCTL_CCGR1]
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str r4, [r0, #CLKCTL_CCGR2]
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str r4, [r0, #CLKCTL_CCGR3]
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str r4, [r0, #CLKCTL_CCGR7]
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ldr r1, =0x00030000
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str r1, [r0, #CLKCTL_CCGR4]
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@ -214,8 +222,7 @@
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/* Switch peripheral to PLL 3 */
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x000010C0
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orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
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ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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ldr r1, =0x13239145
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str r1, [r0, #CLKCTL_CBCDR]
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@ -225,8 +232,7 @@
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x19239145
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str r1, [r0, #CLKCTL_CBCDR]
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ldr r1, =0x000020C0
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orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
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ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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#endif
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setup_pll PLL3_BASE_ADDR, 216
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@ -240,8 +246,7 @@
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#if defined(CONFIG_MX51)
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/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
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ldr r1, =0x0
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ldr r3, [r1, #ROM_SI_REV]
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ldr r3, [r4, #ROM_SI_REV]
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cmp r3, #0x10
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movls r1, #0x1
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movhi r1, #0
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@ -251,14 +256,12 @@
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str r1, [r0, #CLKCTL_CACRR]
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/* Switch ARM back to PLL 1 */
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mov r1, #0
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str r1, [r0, #CLKCTL_CCSR]
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str r4, [r0, #CLKCTL_CCSR]
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#if defined(CONFIG_MX51)
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/* setup the rest */
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/* Use lp_apm (24MHz) source for perclk */
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ldr r1, =0x000020C2
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orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
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ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
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str r1, [r0, #CLKCTL_CBCMR]
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/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
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ldr r1, =CONFIG_SYS_CLKTL_CBCDR
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@ -289,7 +292,6 @@
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ldr r0, =CCM_BASE_ADDR
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ldr r1, =0x00808145
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orr r1, r1, #2 << 10
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orr r1, r1, #0 << 16
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orr r1, r1, #1 << 19
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str r1, [r0, #CLKCTL_CBCDR]
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@ -310,8 +312,7 @@
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cmp r1, #0x0
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bne 1b
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mov r1, #0x0
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str r1, [r0, #CLKCTL_CCDR]
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str r4, [r0, #CLKCTL_CCDR]
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/* for cko - for ARM div by 8 */
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mov r1, #0x000A0000
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@ -325,9 +326,10 @@
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strh r1, [r0]
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.endm
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.section ".text.init", "x"
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ENTRY(lowlevel_init)
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mov r10, lr
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mov r4, #0 /* Fix R4 to 0 */
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#if defined(CONFIG_MX51)
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ldr r0, =GPIO1_BASE_ADDR
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ldr r1, [r0, #0x0]
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@ -346,21 +348,25 @@ ENTRY(lowlevel_init)
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init_clock
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/* r12 saved upper lr*/
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mov pc,lr
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mov pc, r10
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ENDPROC(lowlevel_init)
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/* Board level setting value */
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W_DP_OP_864: .word DP_OP_864
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W_DP_MFD_864: .word DP_MFD_864
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W_DP_MFN_864: .word DP_MFN_864
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#if defined(CONFIG_MX51_PLL_ERRATA)
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W_DP_864: .word DP_OP_864
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.word DP_MFD_864
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.word DP_MFN_864
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W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
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W_DP_OP_800: .word DP_OP_800
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W_DP_MFD_800: .word DP_MFD_800
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W_DP_MFN_800: .word DP_MFN_800
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W_DP_OP_665: .word DP_OP_665
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W_DP_MFD_665: .word DP_MFD_665
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W_DP_MFN_665: .word DP_MFN_665
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W_DP_OP_216: .word DP_OP_216
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W_DP_MFD_216: .word DP_MFD_216
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W_DP_MFN_216: .word DP_MFN_216
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#else
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W_DP_800: .word DP_OP_800
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.word DP_MFD_800
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.word DP_MFN_800
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#endif
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#if defined(CONFIG_MX51)
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W_DP_665: .word DP_OP_665
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.word DP_MFD_665
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.word DP_MFN_665
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#endif
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W_DP_216: .word DP_OP_216
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.word DP_MFD_216
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.word DP_MFN_216
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