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mx6qsabreauto: Pass the board revision to the kernel
The kernel from Freescale expects that the bootloader passes the board revision. Read the board revision and pass it via get_board_rev(). Without passing the board revision the kernel does not operate properly as the initialization of peripherals are different in revA versus revB boards. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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@ -200,6 +200,12 @@ struct src {
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u32 gpr10;
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};
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/* OCOTP Registers */
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struct ocotp_regs {
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u32 reserved[0x198];
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u32 gp1; /* 0x660 */
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};
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/* GPR3 bitfields */
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#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
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#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
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@ -30,6 +30,8 @@
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#include <fsl_esdhc.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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@ -165,9 +167,38 @@ int board_eth_init(bd_t *bis)
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return 0;
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}
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#define BOARD_REV_B 0x200
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#define BOARD_REV_A 0x100
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static int mx6sabre_rev(void)
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{
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/*
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* Get Board ID information from OCOTP_GP1[15:8]
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* i.MX6Q ARD RevA: 0x01
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* i.MX6Q ARD RevB: 0x02
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*/
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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int reg = readl(&ocotp->gp1);
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int ret;
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switch (reg >> 8 & 0x0F) {
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case 0x02:
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ret = BOARD_REV_B;
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break;
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case 0x01:
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default:
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ret = BOARD_REV_A;
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break;
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}
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return ret;
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}
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u32 get_board_rev(void)
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{
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return 0x63000;
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int rev = mx6sabre_rev();
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return (get_cpu_rev() & ~(0xF << 8)) | rev;
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}
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int board_early_init_f(void)
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@ -187,7 +218,20 @@ int board_init(void)
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int checkboard(void)
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{
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puts("Board: MX6Q-Sabreauto\n");
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int rev = mx6sabre_rev();
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char *revname;
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switch (rev) {
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case BOARD_REV_B:
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revname = "B";
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break;
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case BOARD_REV_A:
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default:
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revname = "A";
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break;
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}
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printf("Board: MX6Q-Sabreauto rev%s\n", revname);
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return 0;
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}
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