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powerpc: t1040: Correct RCW EC2 settings

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Per T1040RM (Rev. 1, 08/2015), there are 2 issues with the RCW EC2
settings.

- The value of FSL_CORENET_RCWSR13_EC2_FM1_GPIO is wrong and should
  be 0x04000000 (value of 1 in RCW bit [420:421])
- Value of 2/3 are reserved in RCW bit [420:421], hence there is no
  macro FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Bin Meng 2018-10-08 06:55:57 -07:00 committed by York Sun
parent c00d0012f5
commit db148f2a69
2 changed files with 1 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1785,8 +1785,7 @@ typedef struct ccsr_gur {
#define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII 0x20000000
#define FSL_CORENET_RCWSR13_EC2 0x0c000000 /* bits 420..421 */
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000
#define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII 0x20000000
#define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x04000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL 0x00000080
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH 0x00000000
#define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT 0x00000080

3
drivers/net/fm/t1040.c
View File

@ -41,9 +41,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)
return PHY_INTERFACE_MODE_RGMII;
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII)
return PHY_INTERFACE_MODE_MII;
}
switch (port) {