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Add support for TQM8541/8555 boards, TQM85xx support reworked:
- Support for TQM8541/8555 boards added. - Complete rework of TQM8540/8560 support. - Common TQM85xx code now supports all current TQM85xx platforms (TQM8540/8541/8555/8560). - DDR SDRAM size detection added. - CAS latency default values can be overwritten by setting "serial#" to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used. If problems are detected with this non default CAS latency, the defualt values will be used instead. - FLASH size detection added. - Moved FCC ethernet driver initialization behind TSEC driver init -> TSEC is first device. Patch by Stefan Roese, 30 Nov 2005
This commit is contained in:
Stefan Roese
parent
a46726fdba
commit
d96f41e016
15
CHANGELOG
15
CHANGELOG
@ -2,6 +2,21 @@
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Changes for U-Boot 1.1.4:
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======================================================================
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* Add support for TQM8541/8555 boards, TQM85xx support reworked:
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- Support for TQM8541/8555 boards added.
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- Complete rework of TQM8540/8560 support.
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- Common TQM85xx code now supports all current TQM85xx platforms
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(TQM8540/8541/8555/8560).
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- DDR SDRAM size detection added.
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- CAS latency default values can be overwritten by setting "serial#"
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to e.g. "ABC0001 casl=25" -> CAS latency 2.5 will be used.
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If problems are detected with this non default CAS latency,
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the defualt values will be used instead.
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- FLASH size detection added.
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- Moved FCC ethernet driver initialization behind TSEC driver init
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-> TSEC is first device.
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Patch by Stefan Roese, 30 Nov 2005
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* Add support for AMCC 440SP, add support for AMCC Luan 440SP eval board.
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Patch by John Otken, 23 Nov 2005
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@ -274,10 +274,15 @@ Daniel Poirot <dan.poirot@windriver.com>
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Stefan Roese <sr@denx.de>
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uc100 MPC857
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TQM85xx MPC8540/8541/8555/8560
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bamboo PPC440EP
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bunbinga PPC405EP
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ebony PPC440GP
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ocotea PPC440GX
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p3p440 PPC440GP
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sycamore PPC405GPr
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walnut PPC405GP
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yellowstone PPC440GR
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2
MAKEALL
2
MAKEALL
@ -128,7 +128,7 @@ LIST_85xx=" \
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MPC8540ADS MPC8540EVAL MPC8541CDS MPC8548CDS \
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MPC8555CDS MPC8560ADS PM854 PM856 \
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sbc8540 sbc8560 stxgp3 TQM8540 \
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TQM8560 \
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TQM8541 TQM8555 TQM8560 \
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"
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#########################################################################
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23
Makefile
23
Makefile
@ -1325,11 +1325,24 @@ sbc8560_66_config: unconfig
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stxgp3_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc85xx stxgp3
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TQM8540_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc85xx tqm8540
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TQM8560_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc85xx tqm8560
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TQM8540_config \
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TQM8541_config \
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TQM8555_config \
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TQM8560_config: unconfig
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@case "$@" in \
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TQM8540_config) CTYPE=8540;; \
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TQM8541_config) CTYPE=8541;; \
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TQM8555_config) CTYPE=8555;; \
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TQM8560_config) CTYPE=8560;; \
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esac; \
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>include/config.h ; \
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echo "... TQM"$${CTYPE}; \
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echo "#define CONFIG_MPC$${CTYPE}">>include/config.h; \
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echo "#define CONFIG_TQM$${CTYPE}">>include/config.h; \
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echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>include/config.h; \
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echo "#define CONFIG_BOARDNAME \"TQM$${CTYPE}\"">>include/config.h; \
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echo "#define CFG_BOOTFILE \"bootfile=/tftpboot/tqm$${CTYPE}/uImage\0\"">>include/config.h
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@./mkconfig -a TQM85xx ppc mpc85xx tqm85xx
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#########################################################################
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## 74xx/7xx Systems
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@ -1,241 +0,0 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright (C) 2002,2003, Motorola Inc.
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* Xianghua Xiao <X.Xiao@motorola.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc85xx.h>
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/*
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* TLB0 and TLB1 Entries
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*
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* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
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* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
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* these TLB entries are established.
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*
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* The TLB entries for DDR are dynamically setup in spd_sdram()
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* and use TLB1 Entries 8 through 15 as needed according to the
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* size of DDR memory.
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*
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* MAS0: tlbsel, esel, nv
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* MAS1: valid, iprot, tid, ts, tsize
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* MAS2: epn, sharen, x0, x1, w, i, m, g, e
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* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
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*/
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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.section .bootpg, "ax"
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.globl tlb1_entry
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tlb1_entry:
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entry_start
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/*
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* Number of TLB0 and TLB1 entries in the following table
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*/
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.long 13
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/*
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* TLB0 16K Cacheable, non-guarded
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* 0xd001_0000 16K Temporary Global data for initialization
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*
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* Use four 4K TLB0 entries. These entries must be cacheable
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* as they provide the bootstrap memory before the memory
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* controler and real memory have been configured.
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*
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* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
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* and must not collide with other TLB0 entries.
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*/
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR),
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0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024),
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0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024),
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0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(0, 0, 0)
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.long TLB1_MAS1(1, 0, 0, 0, 0)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024),
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0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024),
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0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 0, 1: 32M Non-cacheable, guarded
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* 0xfe000000 32M FLASH
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* Out of reset this entry is only 4K.
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*/
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.long TLB1_MAS0(1, 1, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(1, 0, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 2: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM First half
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*/
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.long TLB1_MAS0(1, 2, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 3: 256M Non-cacheable, guarded
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* 0x90000000 256M PCI1 MEM Second half
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*/
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.long TLB1_MAS0(1, 3, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000),
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0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000),
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0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 4: 256M Non-cacheable, guarded
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* 0xc0000000 256M Rapid IO MEM First half
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*/
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.long TLB1_MAS0(1, 4, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 5: 256M Non-cacheable, guarded
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* 0xd0000000 256M Rapid IO MEM Second half
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*/
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.long TLB1_MAS0(1, 5, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000),
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0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000),
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0,0,0,0,0,1,0,1,0,1)
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/*
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* TLB 6: 64M Non-cacheable, guarded
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* 0xe000_0000 1M CCSRBAR
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* 0xe200_0000 16M PCI1 IO
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*/
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.long TLB1_MAS0(1, 6, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* TLB 7: 256M DDR
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* 0x00000000 256M DDR System memory
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* Without SPD EEPROM configured DDR, this must be setup manually.
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* Make sure the TLB count at the top of this table is correct.
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* Likely it needs to be increased by two for these entries.
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*/
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.long TLB1_MAS0(1, 7, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
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.long TLB1_MAS0(1, 8, 0)
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.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
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.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
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#endif
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entry_end
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xc000_0000 0xdfff_ffff RapidIO 512M
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* 0xe000_0000 0xe000_ffff CCSR 1M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xf800_0000 0xf80f_ffff BCSR 1M
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* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
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*
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* Notes:
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* CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
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#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR0 0
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#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
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#endif
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|
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#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
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|
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#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
|
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
|
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|
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#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
|
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
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|
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/*
|
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* Rapid IO at 0xc000_0000 for 512 M
|
||||
*/
|
||||
#define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
|
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
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|
||||
|
||||
.section .bootpg, "ax"
|
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.globl law_entry
|
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law_entry:
|
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entry_start
|
||||
.long 0x05
|
||||
.long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3
|
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.long LAWBAR4,LAWAR4
|
||||
entry_end
|
||||
@ -1,284 +0,0 @@
|
||||
/*
|
||||
* Copyright 2005 DENX Software Engineering
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2002,2003, Motorola Inc.
|
||||
* Xianghua Xiao, (X.Xiao@motorola.com)
|
||||
*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <spd.h>
|
||||
|
||||
#if defined(CONFIG_DDR_ECC)
|
||||
extern void ddr_enable_ecc (unsigned int dram_size);
|
||||
#endif
|
||||
|
||||
extern long int spd_sdram (void);
|
||||
|
||||
void local_bus_init (void);
|
||||
long int fixed_sdram (void);
|
||||
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: TQM8540\n");
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
|
||||
CONFIG_SYS_CLK_FREQ / 1000000);
|
||||
#else
|
||||
printf ("PCI1: disabled\n");
|
||||
#endif
|
||||
/*
|
||||
* Initialize local bus.
|
||||
*/
|
||||
local_bus_init ();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
extern long spd_sdram (void);
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
|
||||
#if defined(CONFIG_DDR_DLL)
|
||||
{
|
||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
||||
int i,x;
|
||||
|
||||
x = 10;
|
||||
|
||||
/*
|
||||
* Work around to stabilize DDR DLL
|
||||
*/
|
||||
gur->ddrdllcr = 0x81000000;
|
||||
asm("sync;isync;msync");
|
||||
udelay (200);
|
||||
while (gur->ddrdllcr != 0x81000100) {
|
||||
gur->devdisr = gur->devdisr | 0x00010000;
|
||||
asm("sync;isync;msync");
|
||||
for (i=0; i<x; i++)
|
||||
;
|
||||
gur->devdisr = gur->devdisr & 0xfff7ffff;
|
||||
asm("sync;isync;msync");
|
||||
x++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
dram_size = spd_sdram ();
|
||||
#else
|
||||
dram_size = fixed_sdram ();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_ECC)
|
||||
/*
|
||||
* Initialize and enable DDR ECC.
|
||||
*/
|
||||
ddr_enable_ecc (dram_size);
|
||||
#endif
|
||||
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize Local Bus
|
||||
*/
|
||||
|
||||
void local_bus_init (void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ccsr_gur_t *gur = &immap->im_gur;
|
||||
volatile ccsr_lbc_t *lbc = &immap->im_lbc;
|
||||
|
||||
uint clkdiv;
|
||||
uint lbc_hz;
|
||||
sys_info_t sysinfo;
|
||||
|
||||
/*
|
||||
* Errata LBC11.
|
||||
* Fix Local Bus clock glitch when DLL is enabled.
|
||||
*
|
||||
* If localbus freq is < 66Mhz, DLL bypass mode must be used.
|
||||
* If localbus freq is > 133Mhz, DLL can be safely enabled.
|
||||
* Between 66 and 133, the DLL is enabled with an override workaround.
|
||||
*/
|
||||
|
||||
get_sys_info (&sysinfo);
|
||||
clkdiv = lbc->lcrr & 0x0f;
|
||||
lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
|
||||
|
||||
if (lbc_hz < 66) {
|
||||
lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
|
||||
lbc->ltedr = 0xa4c80000; /* DK: !!! */
|
||||
|
||||
} else if (lbc_hz >= 133) {
|
||||
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
|
||||
|
||||
} else {
|
||||
/*
|
||||
* On REV1 boards, need to change CLKDIV before enable DLL.
|
||||
* Default CLKDIV is 8, change it to 4 temporarily.
|
||||
*/
|
||||
uint pvr = get_pvr ();
|
||||
uint temp_lbcdll = 0;
|
||||
|
||||
if (pvr == PVR_85xx_REV1) {
|
||||
/* FIXME: Justify the high bit here. */
|
||||
lbc->lcrr = 0x10000004;
|
||||
}
|
||||
|
||||
lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
|
||||
udelay (200);
|
||||
|
||||
/*
|
||||
* Sample LBC DLL ctrl reg, upshift it to set the
|
||||
* override bits.
|
||||
*/
|
||||
temp_lbcdll = gur->lbcdllcr;
|
||||
gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
|
||||
asm ("sync;isync;msync");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||||
uint *pend = (uint *) CFG_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf ("SDRAM test phase 1:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf ("SDRAM test phase 2:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf ("SDRAM test passed.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect.
|
||||
************************************************************************/
|
||||
long int fixed_sdram (void)
|
||||
{
|
||||
#ifndef CFG_RAMBOOT
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
|
||||
|
||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||||
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
|
||||
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
|
||||
ddr->sdram_mode = CFG_DDR_MODE;
|
||||
ddr->sdram_interval = CFG_DDR_INTERVAL;
|
||||
ddr->err_disable = 0x0000000D;
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
ddr->err_disable = 0x0000000D;
|
||||
ddr->err_sbe = 0x00ff0000;
|
||||
#endif
|
||||
asm ("sync;isync;msync");
|
||||
udelay (500);
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
/* Enable ECC checking */
|
||||
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
|
||||
#else
|
||||
ddr->sdram_cfg = CFG_DDR_CONTROL;
|
||||
#endif
|
||||
asm ("sync; isync; msync");
|
||||
udelay (500);
|
||||
#endif
|
||||
return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
|
||||
}
|
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
static struct pci_config_table pci_mpc85xxads_config_table[] = {
|
||||
{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
|
||||
PCI_IDSEL_NUMBER, PCI_ANY_ID,
|
||||
pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
|
||||
PCI_ENET0_MEMADDR,
|
||||
PCI_COMMAND_MEMORY |
|
||||
PCI_COMMAND_MASTER}},
|
||||
{}
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
static struct pci_controller hose = {
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
config_table:pci_mpc85xxads_config_table,
|
||||
#endif
|
||||
};
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
void pci_init_board (void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
extern void pci_mpc85xx_init (struct pci_controller *hose);
|
||||
|
||||
pci_mpc85xx_init (&hose);
|
||||
#endif /* CONFIG_PCI */
|
||||
}
|
||||
@ -1,48 +0,0 @@
|
||||
#
|
||||
# (C) Copyright 2001
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := $(BOARD).o
|
||||
SOBJS := init.o
|
||||
#SOBJS :=
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(OBJS) $(SOBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
|
||||
-include .depend
|
||||
|
||||
#########################################################################
|
||||
@ -1,29 +0,0 @@
|
||||
# Copyright 2004 Freescale Semiconductor.
|
||||
# Modified by Xianghua Xiao, X.Xiao@motorola.com
|
||||
# (C) Copyright 2002,Motorola Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# tqm8560 board
|
||||
# default CCARBAR is at 0xff700000
|
||||
# assume U-Boot is less than 256k
|
||||
#
|
||||
TEXT_BASE = 0xfffc0000
|
||||
@ -1,149 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002,2003, Motorola,Inc.
|
||||
* Xianghua Xiao, X.Xiao@motorola.com.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFFFFFFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.bootpg)
|
||||
board/tqm8560/init.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.text)
|
||||
board/tqm8560/init.o (.text)
|
||||
cpu/mpc85xx/traps.o (.text)
|
||||
cpu/mpc85xx/interrupts.o (.text)
|
||||
cpu/mpc85xx/cpu_init.o (.text)
|
||||
cpu/mpc85xx/cpu.o (.text)
|
||||
cpu/mpc85xx/speed.o (.text)
|
||||
cpu/mpc85xx/pci.o (.text)
|
||||
common/dlmalloc.o (.text)
|
||||
lib_generic/crc32.o (.text)
|
||||
lib_ppc/extable.o (.text)
|
||||
lib_generic/zlib.o (.text)
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
|
||||
OBJS := $(BOARD).o
|
||||
OBJS := $(BOARD).o sdram.o
|
||||
SOBJS := init.o
|
||||
#SOBJS :=
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
#
|
||||
|
||||
#
|
||||
# tqm8540 board
|
||||
# tqm85xx board
|
||||
# default CCARBAR is at 0xff700000
|
||||
# assume U-Boot is less than 256k
|
||||
#
|
||||
@ -108,18 +108,18 @@ tlb1_entry:
|
||||
|
||||
|
||||
/*
|
||||
* TLB 0, 1: 32M Non-cacheable, guarded
|
||||
* 0xfe000000 32M FLASH
|
||||
* TLB 0, 1: 128M Non-cacheable, guarded
|
||||
* 0xf8000000 128M FLASH
|
||||
* Out of reset this entry is only 4K.
|
||||
*/
|
||||
.long TLB1_MAS0(1, 1, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
.long TLB1_MAS0(1, 0, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x1000000), 0,0,0,0,0,1,0,1,0,1)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE+0x4000000), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
/*
|
||||
* TLB 2: 256M Non-cacheable, guarded
|
||||
@ -171,23 +171,21 @@ tlb1_entry:
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1)
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* TLB 7: 256M DDR
|
||||
* 0x00000000 256M DDR System memory
|
||||
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
|
||||
* 0x00000000 512M DDR System memory
|
||||
* Without SPD EEPROM configured DDR, this must be setup manually.
|
||||
* Make sure the TLB count at the top of this table is correct.
|
||||
* Likely it needs to be increased by two for these entries.
|
||||
*/
|
||||
.long TLB1_MAS0(1, 7, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1)
|
||||
.long TLB1_MAS0(1, 8, 0)
|
||||
.long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,0,0,0)
|
||||
.long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,1,0,1,0)
|
||||
.long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE+0x10000000), 0,0,0,0,0,1,0,1,0,1)
|
||||
#endif
|
||||
|
||||
entry_end
|
||||
|
||||
@ -207,19 +205,14 @@ tlb1_entry:
|
||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
||||
*/
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
#define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
||||
#else
|
||||
#define LAWBAR0 0
|
||||
#define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
|
||||
#endif
|
||||
#define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
|
||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
||||
|
||||
#define LAWBAR2 ((CFG_LBC_FLASH_BASE>>12) & 0xfffff)
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
|
||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M))
|
||||
|
||||
#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
|
||||
#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
||||
226
board/tqm85xx/sdram.c
Normal file
226
board/tqm85xx/sdram.c
Normal file
@ -0,0 +1,226 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <spd.h>
|
||||
|
||||
struct sdram_conf_s {
|
||||
unsigned long size;
|
||||
unsigned long reg;
|
||||
};
|
||||
|
||||
typedef struct sdram_conf_s sdram_conf_t;
|
||||
|
||||
sdram_conf_t ddr_cs_conf[] = {
|
||||
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
|
||||
{(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
|
||||
{(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
|
||||
{(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
|
||||
};
|
||||
|
||||
#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
|
||||
|
||||
int cas_latency(void);
|
||||
|
||||
/*
|
||||
* Autodetect onboard DDR SDRAM on 85xx platforms
|
||||
*
|
||||
* NOTE: Some of the hardcoded values are hardware dependant,
|
||||
* so this should be extended for other future boards
|
||||
* using this routine!
|
||||
*/
|
||||
long int sdram_setup(int casl)
|
||||
{
|
||||
int i;
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
|
||||
unsigned long cfg_ddr_timing1;
|
||||
unsigned long cfg_ddr_mode;
|
||||
|
||||
/*
|
||||
* Disable memory controller.
|
||||
*/
|
||||
ddr->cs0_config = 0;
|
||||
ddr->sdram_cfg = 0;
|
||||
|
||||
switch (casl) {
|
||||
case 20:
|
||||
cfg_ddr_timing1 = 0x47405331 | (3 << 16);
|
||||
cfg_ddr_mode = 0x40020002 | (2 << 4);
|
||||
break;
|
||||
|
||||
case 25:
|
||||
cfg_ddr_timing1 = 0x47405331 | (4 << 16);
|
||||
cfg_ddr_mode = 0x40020002 | (6 << 4);
|
||||
break;
|
||||
|
||||
case 30:
|
||||
default:
|
||||
cfg_ddr_timing1 = 0x47405331 | (5 << 16);
|
||||
cfg_ddr_mode = 0x40020002 | (3 << 4);
|
||||
break;
|
||||
}
|
||||
|
||||
ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
|
||||
ddr->cs0_config = ddr_cs_conf[0].reg;
|
||||
ddr->timing_cfg_1 = cfg_ddr_timing1;
|
||||
ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
|
||||
ddr->sdram_mode = cfg_ddr_mode;
|
||||
ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
|
||||
ddr->err_disable = 0x0000000D;
|
||||
|
||||
asm ("sync;isync;msync");
|
||||
udelay(1000);
|
||||
|
||||
ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
|
||||
asm ("sync; isync; msync");
|
||||
udelay(1000);
|
||||
|
||||
for (i=0; i<N_DDR_CS_CONF; i++) {
|
||||
ddr->cs0_config = ddr_cs_conf[i].reg;
|
||||
|
||||
if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) {
|
||||
/*
|
||||
* OK, size detected -> all done
|
||||
*/
|
||||
return ddr_cs_conf[i].size;
|
||||
}
|
||||
}
|
||||
|
||||
return 0; /* nothing found ! */
|
||||
}
|
||||
|
||||
void board_add_ram_info(int use_default)
|
||||
{
|
||||
int casl;
|
||||
|
||||
if (use_default)
|
||||
casl = CONFIG_DDR_DEFAULT_CL;
|
||||
else
|
||||
casl = cas_latency();
|
||||
|
||||
puts(" (CL=");
|
||||
switch (casl) {
|
||||
case 20:
|
||||
puts("2)");
|
||||
break;
|
||||
|
||||
case 25:
|
||||
puts("2.5)");
|
||||
break;
|
||||
|
||||
case 30:
|
||||
puts("3)");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
int casl;
|
||||
|
||||
#if defined(CONFIG_DDR_DLL)
|
||||
/*
|
||||
* This DLL-Override only used on TQM8540 and TQM8560
|
||||
*/
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
||||
int i,x;
|
||||
|
||||
x = 10;
|
||||
|
||||
/*
|
||||
* Work around to stabilize DDR DLL
|
||||
*/
|
||||
gur->ddrdllcr = 0x81000000;
|
||||
asm("sync;isync;msync");
|
||||
udelay (200);
|
||||
while (gur->ddrdllcr != 0x81000100) {
|
||||
gur->devdisr = gur->devdisr | 0x00010000;
|
||||
asm("sync;isync;msync");
|
||||
for (i=0; i<x; i++)
|
||||
;
|
||||
gur->devdisr = gur->devdisr & 0xfff7ffff;
|
||||
asm("sync;isync;msync");
|
||||
x++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
casl = cas_latency();
|
||||
dram_size = sdram_setup(casl);
|
||||
if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
|
||||
/*
|
||||
* Try again with default CAS latency
|
||||
*/
|
||||
puts("Problem with CAS lantency");
|
||||
board_add_ram_info(1);
|
||||
puts(", using default CL!\n");
|
||||
casl = CONFIG_DDR_DEFAULT_CL;
|
||||
dram_size = sdram_setup(casl);
|
||||
puts(" ");
|
||||
}
|
||||
|
||||
return dram_size;
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||||
uint *pend = (uint *) CFG_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf ("SDRAM test phase 1:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf ("SDRAM test phase 2:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf ("SDRAM test passed.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
@ -1,5 +1,7 @@
|
||||
/*
|
||||
* Copyright 2005 DENX Software Engineering
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2002,2003, Motorola Inc.
|
||||
* Xianghua Xiao, (X.Xiao@motorola.com)
|
||||
@ -32,16 +34,15 @@
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <ioports.h>
|
||||
#include <spd.h>
|
||||
#include <flash.h>
|
||||
|
||||
#if defined(CONFIG_DDR_ECC)
|
||||
extern void ddr_enable_ecc (unsigned int dram_size);
|
||||
#endif
|
||||
|
||||
extern long int spd_sdram (void);
|
||||
extern flash_info_t flash_info[]; /* FLASH chips info */
|
||||
|
||||
void local_bus_init (void);
|
||||
long int fixed_sdram (void);
|
||||
ulong flash_get_size (ulong base, int banknum);
|
||||
|
||||
#ifdef CONFIG_CPM2
|
||||
/*
|
||||
* I/O Port configuration table
|
||||
*
|
||||
@ -53,24 +54,24 @@ const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port A configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
|
||||
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
|
||||
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
|
||||
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
|
||||
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
|
||||
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
|
||||
/* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
|
||||
/* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
|
||||
/* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
|
||||
/* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
|
||||
/* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
|
||||
/* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
|
||||
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
|
||||
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
|
||||
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
|
||||
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
|
||||
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
|
||||
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
|
||||
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
|
||||
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
|
||||
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
|
||||
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
|
||||
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
|
||||
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
|
||||
/* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
|
||||
/* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
|
||||
/* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
|
||||
/* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
|
||||
/* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
|
||||
/* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
|
||||
/* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
|
||||
/* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
|
||||
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
|
||||
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
|
||||
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
|
||||
@ -89,20 +90,20 @@ const iop_conf_t iop_conf_tab[4][32] = {
|
||||
|
||||
/* Port B configuration */
|
||||
{ /* conf ppar psor pdir podr pdat */
|
||||
/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
||||
/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
||||
/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
||||
/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
||||
/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
||||
/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
||||
/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
||||
/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
||||
/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
||||
/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
||||
/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
||||
/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
||||
/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
||||
/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
||||
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
|
||||
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
|
||||
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
|
||||
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
|
||||
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
|
||||
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
|
||||
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
|
||||
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
|
||||
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
|
||||
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
|
||||
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
|
||||
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
|
||||
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
|
||||
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
|
||||
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
|
||||
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
|
||||
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
|
||||
@ -135,12 +136,12 @@ const iop_conf_t iop_conf_tab[4][32] = {
|
||||
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
|
||||
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
|
||||
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
|
||||
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
||||
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
||||
/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
|
||||
/* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
|
||||
/* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
|
||||
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
|
||||
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
|
||||
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */
|
||||
/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
|
||||
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
|
||||
/* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
|
||||
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
|
||||
/* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */
|
||||
@ -195,16 +196,49 @@ const iop_conf_t iop_conf_tab[4][32] = {
|
||||
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
|
||||
}
|
||||
};
|
||||
#endif /* CONFIG_CPM2 */
|
||||
|
||||
#define CASL_STRING1 "casl=xx"
|
||||
#define CASL_STRING2 "casl="
|
||||
|
||||
int board_early_init_f (void)
|
||||
static const int casl_table[] = { 20, 25, 30 };
|
||||
#define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
|
||||
|
||||
int cas_latency(void)
|
||||
{
|
||||
return 0;
|
||||
char *s = getenv("serial#");
|
||||
int casl;
|
||||
int val;
|
||||
int i;
|
||||
|
||||
casl = CONFIG_DDR_DEFAULT_CL;
|
||||
|
||||
if (s != NULL) {
|
||||
if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2,
|
||||
strlen(CASL_STRING2)) == 0) {
|
||||
val = simple_strtoul(s + strlen(s) - 2, NULL, 10);
|
||||
|
||||
for (i=0; i<N_CASL; ++i) {
|
||||
if (val == casl_table[i]) {
|
||||
return val;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return casl;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
puts ("Board: TQM8560\n");
|
||||
char *s = getenv("serial#");
|
||||
|
||||
printf("Board: %s", CONFIG_BOARDNAME);
|
||||
if (s != NULL) {
|
||||
puts(", serial# ");
|
||||
puts(s);
|
||||
}
|
||||
putc('\n');
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
printf ("PCI1: 32 bit, %d MHz (compiled)\n",
|
||||
@ -212,6 +246,7 @@ int checkboard (void)
|
||||
#else
|
||||
printf ("PCI1: disabled\n");
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Initialize local bus.
|
||||
*/
|
||||
@ -220,59 +255,69 @@ int checkboard (void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
long int initdram (int board_type)
|
||||
int misc_init_r (void)
|
||||
{
|
||||
long dram_size = 0;
|
||||
extern long spd_sdram (void);
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||
volatile ccsr_lbc_t *memctl = &immap->im_lbc;
|
||||
|
||||
#if defined(CONFIG_DDR_DLL)
|
||||
{
|
||||
volatile ccsr_gur_t *gur= &immap->im_gur;
|
||||
int i,x;
|
||||
/*
|
||||
* Adjust flash start and offset to detected values
|
||||
*/
|
||||
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
|
||||
gd->bd->bi_flashoffset = 0;
|
||||
|
||||
x = 10;
|
||||
/*
|
||||
* Check if boot FLASH isn't max size
|
||||
*/
|
||||
if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
|
||||
memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
|
||||
memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
|
||||
|
||||
/*
|
||||
* Work around to stabilize DDR DLL
|
||||
* Re-check to get correct base address
|
||||
*/
|
||||
gur->ddrdllcr = 0x81000000;
|
||||
asm("sync;isync;msync");
|
||||
udelay (200);
|
||||
while (gur->ddrdllcr != 0x81000100) {
|
||||
gur->devdisr = gur->devdisr | 0x00010000;
|
||||
asm("sync;isync;msync");
|
||||
for (i=0; i<x; i++)
|
||||
;
|
||||
gur->devdisr = gur->devdisr & 0xfff7ffff;
|
||||
asm("sync;isync;msync");
|
||||
x++;
|
||||
}
|
||||
flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
dram_size = spd_sdram ();
|
||||
#else
|
||||
dram_size = fixed_sdram ();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_DDR_ECC)
|
||||
/*
|
||||
* Initialize and enable DDR ECC.
|
||||
* Check if only one FLASH bank is available
|
||||
*/
|
||||
ddr_enable_ecc (dram_size);
|
||||
#endif
|
||||
if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
|
||||
memctl->or1 = 0;
|
||||
memctl->br1 = 0;
|
||||
|
||||
return dram_size;
|
||||
/*
|
||||
* Re-do flash protection upon new addresses
|
||||
*/
|
||||
flash_protect (FLAG_PROTECT_CLEAR,
|
||||
gd->bd->bi_flashstart, 0xffffffff,
|
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
|
||||
|
||||
/* Monitor protection ON by default */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_MONITOR_BASE, 0xffffffff,
|
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
|
||||
|
||||
/* Environment protection ON by default */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
|
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
|
||||
|
||||
/* Redundant environment protection ON by default */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR_REDUND,
|
||||
CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1,
|
||||
&flash_info[CFG_MAX_FLASH_BANKS - 1]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Initialize Local Bus
|
||||
*/
|
||||
|
||||
void local_bus_init (void)
|
||||
{
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
@ -329,79 +374,6 @@ void local_bus_init (void)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
int testdram (void)
|
||||
{
|
||||
uint *pstart = (uint *) CFG_MEMTEST_START;
|
||||
uint *pend = (uint *) CFG_MEMTEST_END;
|
||||
uint *p;
|
||||
|
||||
printf ("SDRAM test phase 1:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0xaaaaaaaa;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0xaaaaaaaa) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf ("SDRAM test phase 2:\n");
|
||||
for (p = pstart; p < pend; p++)
|
||||
*p = 0x55555555;
|
||||
|
||||
for (p = pstart; p < pend; p++) {
|
||||
if (*p != 0x55555555) {
|
||||
printf ("SDRAM test fails at: %08x\n", (uint) p);
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
printf ("SDRAM test passed.\n");
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if !defined(CONFIG_SPD_EEPROM)
|
||||
/*************************************************************************
|
||||
* fixed sdram init -- doesn't use serial presence detect.
|
||||
************************************************************************/
|
||||
long int fixed_sdram (void)
|
||||
{
|
||||
#ifndef CFG_RAMBOOT
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile ccsr_ddr_t *ddr = &immap->im_ddr;
|
||||
|
||||
ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
|
||||
ddr->cs0_config = CFG_DDR_CS0_CONFIG;
|
||||
ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
|
||||
ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
|
||||
ddr->sdram_mode = CFG_DDR_MODE;
|
||||
ddr->sdram_interval = CFG_DDR_INTERVAL;
|
||||
ddr->err_disable = 0x0000000D;
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
ddr->err_disable = 0x0000000D;
|
||||
ddr->err_sbe = 0x00ff0000;
|
||||
#endif
|
||||
asm ("sync;isync;msync");
|
||||
udelay (500);
|
||||
#if defined (CONFIG_DDR_ECC)
|
||||
/* Enable ECC checking */
|
||||
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
|
||||
#else
|
||||
ddr->sdram_cfg = CFG_DDR_CONTROL;
|
||||
#endif
|
||||
asm ("sync; isync; msync");
|
||||
udelay (500);
|
||||
#endif
|
||||
return get_ram_size (0, CFG_SDRAM_SIZE * 1024 * 1024);
|
||||
}
|
||||
#endif /* !defined(CONFIG_SPD_EEPROM) */
|
||||
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*
|
||||
* Initialize PCI Devices, report devices found.
|
||||
@ -35,7 +35,7 @@ SECTIONS
|
||||
.bootpg 0xFFFFF000 :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.bootpg)
|
||||
board/tqm8540/init.o (.bootpg)
|
||||
board/tqm85xx/init.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
@ -65,7 +65,7 @@ SECTIONS
|
||||
.text :
|
||||
{
|
||||
cpu/mpc85xx/start.o (.text)
|
||||
board/tqm8540/init.o (.text)
|
||||
board/tqm85xx/init.o (.text)
|
||||
cpu/mpc85xx/traps.o (.text)
|
||||
cpu/mpc85xx/interrupts.o (.text)
|
||||
cpu/mpc85xx/cpu_init.o (.text)
|
||||
@ -1,464 +0,0 @@
|
||||
/*
|
||||
* Copyright 2005 DENX Software Engineering
|
||||
* Wolfgang Denk <wd@denx.de>
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2002,2003 Motorola,Inc.
|
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* TQM8540 board configuration file
|
||||
*
|
||||
* Make sure you change the MAC address and other network params first,
|
||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
|
||||
#define CONFIG_MPC8540 1 /* MPC8540 specific */
|
||||
#define CONFIG_TQM8540 1 /* TQM8540 board specific */
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
|
||||
|
||||
/*
|
||||
* sysclk for MPC85xx
|
||||
*
|
||||
* Two valid values are:
|
||||
* 33000000
|
||||
* 66000000
|
||||
*
|
||||
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
|
||||
* is likely the desired value here, so that is now the default.
|
||||
* The board, however, can run at 66MHz. In any event, this value
|
||||
* must match the settings of some switches. Details can be found
|
||||
* in the README.mpc85xxads.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
|
||||
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
|
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
|
||||
#define CFG_MEMTEST_END 0x10000000
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
|
||||
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
|
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* Determine DDR configuration from I2C interface.
|
||||
*/
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
|
||||
|
||||
#else
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
|
||||
#define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
|
||||
#define CFG_DDR_CS0_CONFIG 0x80000102
|
||||
#define CFG_DDR_TIMING_1 0x47445331
|
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
|
||||
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
|
||||
#define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
|
||||
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Flash on the Local Bus
|
||||
*/
|
||||
#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
|
||||
#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
|
||||
|
||||
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
|
||||
#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
|
||||
|
||||
#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
#define CFG_RAMBOOT
|
||||
#else
|
||||
#undef CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
|
||||
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
|
||||
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
|
||||
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
|
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
|
||||
|
||||
/*
|
||||
* LSDMR masks
|
||||
*/
|
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
|
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
|
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
|
||||
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
|
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
|
||||
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
|
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
|
||||
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
|
||||
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
|
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
|
||||
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
|
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
|
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
|
||||
|
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
|
||||
| CFG_LBC_LSDMR_RFCR5 \
|
||||
| CFG_LBC_LSDMR_PRETOACT3 \
|
||||
| CFG_LBC_LSDMR_ACTTORW3 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC2 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
| CFG_LBC_LSDMR_RFEN \
|
||||
)
|
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence.
|
||||
*/
|
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_PCHALL)
|
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_ARFRSH)
|
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_ARFRSH)
|
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_MRW)
|
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_NORMAL)
|
||||
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
|
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/* I2C EEPROM */
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
||||
/* RapidIO MMU */
|
||||
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
|
||||
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
|
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_MPC85XX_TSEC1 1
|
||||
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_MPC85XX_TSEC2 1
|
||||
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
#define CONFIG_MPC85XX_FEC 1
|
||||
#define CONFIG_MPC85XX_FEC_NAME "FEC"
|
||||
#define FEC_PHY_ADDR 3
|
||||
#define FEC_PHYIDX 0
|
||||
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
|
||||
/* Options are TSEC[0-1], FEC */
|
||||
#define CONFIG_ETHPRIME "TSEC1"
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
|
||||
#else
|
||||
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP )
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
# define ADD_PCI_CMD (CFG_CMD_PCI)
|
||||
#else
|
||||
# define ADD_PCI_CMD 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
|
||||
ADD_PCI_CMD | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING )
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consdev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $bootargs " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
|
||||
":$hostname:$netdev:off panic=1\0" \
|
||||
"addcons=setenv bootargs $bootargs " \
|
||||
"console=$consdev,$baudrate\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
"bootm $kernel_addr\0" \
|
||||
"flash_self=run ramargs addip addcons;" \
|
||||
"bootm $kernel_addr $ramdisk_addr\0" \
|
||||
"net_nfs=tftp $loadaddr $bootfile;" \
|
||||
"run nfsargs addip addcons;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_85xx\0" \
|
||||
"bootfile=/tftpboot/tqm8540/uImage\0" \
|
||||
"kernel_addr=FE000000\0" \
|
||||
"ramdisk_addr=FE100000\0" \
|
||||
"load=tftp 100000 /tftpboot/tqm8540/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -1,473 +0,0 @@
|
||||
/*
|
||||
* Copyright 2005 DENX Software Engineering
|
||||
* Wolfgang Denk <wd@denx.de>
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2002,2003 Motorola,Inc.
|
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* TQM8560 board configuration file
|
||||
*
|
||||
* Make sure you change the MAC address and other network params first,
|
||||
* search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
|
||||
#define CONFIG_CPM2 1 /* has CPM2 */
|
||||
#define CONFIG_MPC8560 1 /* MPC8560 specific */
|
||||
#define CONFIG_TQM8560 1 /* TQM8560 board specific */
|
||||
|
||||
/*
|
||||
* BIG FAT WARNING: Right now PCI seems to have a problem on the
|
||||
* TQM8560 on the Starter Kit. So, if the board doen't come up
|
||||
* please disable the PCI support for now. sr@denx.de, 15-09-2005
|
||||
*/
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
#undef CONFIG_DDR_ECC /* only for ECC DDR module */
|
||||
#define CONFIG_DDR_DLL /* possible DLL fix needed */
|
||||
#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
|
||||
|
||||
/*
|
||||
* sysclk for MPC85xx
|
||||
*
|
||||
* Two valid values are:
|
||||
* 33000000
|
||||
* 66000000
|
||||
*
|
||||
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
|
||||
* is likely the desired value here, so that is now the default.
|
||||
* The board, however, can run at 66MHz. In any event, this value
|
||||
* must match the settings of some switches. Details can be found
|
||||
* in the README.mpc85xxads.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
|
||||
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
|
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00000000 /* memtest region */
|
||||
#define CFG_MEMTEST_END 0x10000000
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
|
||||
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
|
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
|
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
|
||||
|
||||
#if defined(CONFIG_SPD_EEPROM)
|
||||
/*
|
||||
* Determine DDR configuration from I2C interface.
|
||||
*/
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
|
||||
|
||||
#else
|
||||
/*
|
||||
* Manually set up DDR parameters
|
||||
*/
|
||||
#define CFG_SDRAM_SIZE 512 /* DDR is 256MB */
|
||||
#define CFG_DDR_CS0_BNDS 0x0000001f /* 0-256MB */
|
||||
#define CFG_DDR_CS0_CONFIG 0x80000102
|
||||
#define CFG_DDR_TIMING_1 0x47445331
|
||||
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
|
||||
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
|
||||
#define CFG_DDR_MODE 0x40020062 /* DLL,normal,seq,4/2.5 */
|
||||
#define CFG_DDR_INTERVAL 0x05160100 /* autocharge,no open page */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Flash on the Local Bus
|
||||
*/
|
||||
#define CFG_LBC_FLASH_BASE 0xfe000000 /* Localbus SDRAM */
|
||||
#define CFG_LBC_FLASH_SIZE 32 /* LBC SDRAM is 32MB */
|
||||
|
||||
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH 32M */
|
||||
#define CFG_BR0_PRELIM 0xfe001801 /* port size 32bit */
|
||||
|
||||
#define CFG_OR0_PRELIM 0xfe000040 /* 32MB Flash */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
|
||||
#define CFG_RAMBOOT
|
||||
#else
|
||||
#undef CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CFG_FLASH_CFI_DRIVER
|
||||
#define CFG_FLASH_CFI
|
||||
#define CFG_FLASH_EMPTY_INFO
|
||||
|
||||
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
|
||||
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
|
||||
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
|
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
|
||||
|
||||
/*
|
||||
* LSDMR masks
|
||||
*/
|
||||
#define CFG_LBC_LSDMR_RFEN (1 << (31 - 1))
|
||||
#define CFG_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
|
||||
#define CFG_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
|
||||
#define CFG_LBC_LSDMR_RFCR5 (3 << (31 - 16))
|
||||
#define CFG_LBC_LSDMR_RFCR16 (7 << (31 - 16))
|
||||
#define CFG_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
|
||||
#define CFG_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
|
||||
#define CFG_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
|
||||
#define CFG_LBC_LSDMR_BL8 (1 << (31 - 23))
|
||||
#define CFG_LBC_LSDMR_WRC2 (2 << (31 - 27))
|
||||
#define CFG_LBC_LSDMR_WRC4 (0 << (31 - 27))
|
||||
#define CFG_LBC_LSDMR_BUFCMD (1 << (31 - 29))
|
||||
#define CFG_LBC_LSDMR_CL3 (3 << (31 - 31))
|
||||
|
||||
#define CFG_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_MRW (3 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
|
||||
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
|
||||
|
||||
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_BSMA1516 \
|
||||
| CFG_LBC_LSDMR_RFCR5 \
|
||||
| CFG_LBC_LSDMR_PRETOACT3 \
|
||||
| CFG_LBC_LSDMR_ACTTORW3 \
|
||||
| CFG_LBC_LSDMR_BL8 \
|
||||
| CFG_LBC_LSDMR_WRC2 \
|
||||
| CFG_LBC_LSDMR_CL3 \
|
||||
| CFG_LBC_LSDMR_RFEN \
|
||||
)
|
||||
|
||||
/*
|
||||
* SDRAM Controller configuration sequence.
|
||||
*/
|
||||
#define CFG_LBC_LSDMR_1 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_PCHALL)
|
||||
#define CFG_LBC_LSDMR_2 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_ARFRSH)
|
||||
#define CFG_LBC_LSDMR_3 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_ARFRSH)
|
||||
#define CFG_LBC_LSDMR_4 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_MRW)
|
||||
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
|
||||
| CFG_LBC_LSDMR_OP_NORMAL)
|
||||
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else */
|
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/* I2C EEPROM */
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
||||
/* RapidIO MMU */
|
||||
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
|
||||
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
|
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#if !defined(CONFIG_PCI_PNP)
|
||||
#define PCI_ENET0_IOADDR 0xe0000000
|
||||
#define PCI_ENET0_MEMADDR 0xe0000000
|
||||
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
|
||||
#endif
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#endif
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_MPC85XX_TSEC1 1
|
||||
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_MPC85XX_TSEC2 1
|
||||
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
#define CONFIG_MPC85XX_FEC 1
|
||||
#define CONFIG_MPC85XX_FEC_NAME "FEC"
|
||||
#define FEC_PHY_ADDR 3
|
||||
#define FEC_PHYIDX 0
|
||||
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
|
||||
/* Options are TSEC[0-1], FEC */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
#define CONFIG_ETHER_ON_FCC
|
||||
#define CONFIG_ETHER_ON_FCC3
|
||||
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
|
||||
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#ifndef CFG_RAMBOOT
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* Flash is not usable now */
|
||||
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with timestamp */
|
||||
|
||||
#if defined(CFG_RAMBOOT)
|
||||
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL & ~(CFG_CMD_ENV | CFG_CMD_LOADS))
|
||||
#else
|
||||
# define CONFIG_CMD_PRIV (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP )
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
# define ADD_PCI_CMD (CFG_CMD_PCI)
|
||||
#else
|
||||
# define ADD_PCI_CMD 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_PRIV | \
|
||||
ADD_PCI_CMD | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING )
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"consdev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $bootargs " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
|
||||
":$hostname:$netdev:off panic=1\0" \
|
||||
"addcons=setenv bootargs $bootargs " \
|
||||
"console=$consdev,$baudrate\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
"bootm $kernel_addr\0" \
|
||||
"flash_self=run ramargs addip addcons;" \
|
||||
"bootm $kernel_addr $ramdisk_addr\0" \
|
||||
"net_nfs=tftp $loadaddr $bootfile;" \
|
||||
"run nfsargs addip addcons;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_85xx\0" \
|
||||
"bootfile=/tftpboot/tqm8560/uImage\0" \
|
||||
"kernel_addr=FE000000\0" \
|
||||
"ramdisk_addr=FE100000\0" \
|
||||
"load=tftp 100000 /tftpboot/tqm8560/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
452
include/configs/TQM85xx.h
Normal file
452
include/configs/TQM85xx.h
Normal file
@ -0,0 +1,452 @@
|
||||
/*
|
||||
* (C) Copyright 2005
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Wolfgang Denk <wd@denx.de>
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* (C) Copyright 2002,2003 Motorola,Inc.
|
||||
* Xianghua Xiao <X.Xiao@motorola.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* TQM85xx (8560/40/55/41) board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_BOOKE 1 /* BOOKE */
|
||||
#define CONFIG_E500 1 /* BOOKE e500 family */
|
||||
#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
|
||||
/*
|
||||
* Only MPC8540 doesn't have CPM module
|
||||
*/
|
||||
#ifndef CONFIG_MPC8540
|
||||
#define CONFIG_CPM2 1 /* has CPM2 */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* sysclk for MPC85xx
|
||||
*
|
||||
* Two valid values are:
|
||||
* 33000000
|
||||
* 66000000
|
||||
*
|
||||
* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
|
||||
* is likely the desired value here, so that is now the default.
|
||||
* The board, however, can run at 66MHz. In any event, this value
|
||||
* must match the settings of some switches. Details can be found
|
||||
* in the README.mpc85xxads.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SYS_CLK_FREQ
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333
|
||||
#endif
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
|
||||
|
||||
#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
|
||||
|
||||
#undef CFG_DRAM_TEST /* memory test, takes time */
|
||||
#define CFG_MEMTEST_START 0x00000000
|
||||
#define CFG_MEMTEST_END 0x10000000
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
|
||||
#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
|
||||
#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
|
||||
#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
|
||||
#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
|
||||
|
||||
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
|
||||
/* TQM8540 & 8560 need DLL-override */
|
||||
#define CONFIG_DDR_DLL /* DLL fix needed */
|
||||
#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
|
||||
#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
|
||||
|
||||
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
|
||||
#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
|
||||
#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
|
||||
|
||||
/*
|
||||
* Flash on the Local Bus
|
||||
*/
|
||||
#define CFG_FLASH0 0xFC000000
|
||||
#define CFG_FLASH1 0xF8000000
|
||||
#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
|
||||
|
||||
#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
|
||||
#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
|
||||
|
||||
#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
|
||||
#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
|
||||
#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
|
||||
#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
|
||||
|
||||
#define CFG_FLASH_CFI /* flash is CFI compat. */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
|
||||
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
|
||||
#undef CFG_FLASH_CHECKSUM
|
||||
#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
|
||||
#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
|
||||
#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
|
||||
#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
|
||||
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CFG_INIT_RAM_LOCK 1
|
||||
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
|
||||
|
||||
#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
|
||||
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
#if defined(CONFIG_TQM8560)
|
||||
|
||||
#define CONFIG_CONS_ON_SCC /* define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* define if console on something else */
|
||||
#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
|
||||
|
||||
#else
|
||||
|
||||
#define CONFIG_CONS_INDEX 1
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CFG_NS16550
|
||||
#define CFG_NS16550_SERIAL
|
||||
#define CFG_NS16550_REG_SIZE 1
|
||||
#define CFG_NS16550_CLK get_bus_freq(0)
|
||||
|
||||
#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
|
||||
#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
|
||||
|
||||
#endif /* CONFIG_TQM8560 */
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CFG_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CFG_HUSH_PARSER
|
||||
#ifdef CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#undef CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
|
||||
#define CFG_I2C_SLAVE 0x7F
|
||||
#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
|
||||
|
||||
/* I2C RTC */
|
||||
#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
|
||||
#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
|
||||
|
||||
/* I2C EEPROM */
|
||||
/*
|
||||
* EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
|
||||
*/
|
||||
#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_ENABLE
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
|
||||
|
||||
/* I2C SYSMON (LM75) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CFG_DTT_MAX_TEMP 70
|
||||
#define CFG_DTT_LOW_TEMP -30
|
||||
#define CFG_DTT_HYSTERESIS 3
|
||||
|
||||
/* RapidIO MMU */
|
||||
#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
|
||||
#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
|
||||
#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Addresses are mapped 1-1.
|
||||
*/
|
||||
#define CFG_PCI1_MEM_BASE 0x80000000
|
||||
#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
|
||||
#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CFG_PCI1_IO_BASE 0xe2000000
|
||||
#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
|
||||
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
|
||||
#define CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
|
||||
#define CONFIG_NET_MULTI 1
|
||||
|
||||
#define CONFIG_MII 1 /* MII PHY management */
|
||||
#define CONFIG_MPC85XX_TSEC1 1
|
||||
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
|
||||
#define CONFIG_MPC85XX_TSEC2 1
|
||||
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
|
||||
#define TSEC1_PHY_ADDR 2
|
||||
#define TSEC2_PHY_ADDR 1
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC2_PHYIDX 0
|
||||
#define FEC_PHY_ADDR 3
|
||||
#define FEC_PHYIDX 0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
|
||||
/* Options are TSEC[0-1], FEC */
|
||||
#define CONFIG_ETHPRIME "TSEC0"
|
||||
|
||||
#if defined(CONFIG_TQM8540)
|
||||
/*
|
||||
* TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
|
||||
* The FEC port is connected on the same signals as the FCC3 port
|
||||
* of the TQM8560 to the baseboard (STK85xx Starterkit).
|
||||
*
|
||||
* On the STK85xx Starterkit the X47/X50 jumper has to be set to
|
||||
* a - d (X50.2 - 3) to enable the FEC port.
|
||||
*/
|
||||
#define CONFIG_MPC85XX_FEC 1
|
||||
#define CONFIG_MPC85XX_FEC_NAME "FEC"
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
|
||||
/*
|
||||
* TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
|
||||
* can be used at once, since only one FCC port is available on the STK85xx
|
||||
* Starterkit.
|
||||
*
|
||||
* To use this port you have to configure U-Boot to use the FCC port 1...2
|
||||
* and set the X47/X50 jumper to:
|
||||
* FCC1: a - b (X47.2 - X50.2)
|
||||
* FCC2: a - c (X50.2 - 1)
|
||||
*/
|
||||
#define CONFIG_ETHER_ON_FCC
|
||||
#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TQM8560)
|
||||
/*
|
||||
* TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
|
||||
* can be used at once, since only one FCC port is available on the STK85xx
|
||||
* Starterkit.
|
||||
*
|
||||
* To use this port you have to configure U-Boot to use the FCC port 1...3
|
||||
* and set the X47/X50 jumper to:
|
||||
* FCC1: a - b (X47.2 - X50.2)
|
||||
* FCC2: a - c (X50.2 - 1)
|
||||
* FCC3: a - d (X50.2 - 3)
|
||||
*/
|
||||
#define CONFIG_ETHER_ON_FCC
|
||||
#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
|
||||
#define CONFIG_ETHER_ON_FCC1
|
||||
#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
|
||||
#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
|
||||
#define CONFIG_ETHER_ON_FCC2
|
||||
#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
|
||||
#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
|
||||
#define CONFIG_ETHER_ON_FCC3
|
||||
#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
|
||||
#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
|
||||
#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#define CFG_ENV_SIZE 0x2000
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* Print image info with ts */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
# define ADD_PCI_CMD (CFG_CMD_PCI)
|
||||
#else
|
||||
# define ADD_PCI_CMD 0
|
||||
#endif
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_SNTP | \
|
||||
ADD_PCI_CMD | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_DATE | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_PING )
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/* Cache Configuration */
|
||||
#define CFG_DCACHE_SIZE 32768
|
||||
#define CFG_CACHELINE_SIZE 32
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
|
||||
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
||||
#endif
|
||||
|
||||
|
||||
#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
|
||||
|
||||
#define CONFIG_PREBOOT "echo;" \
|
||||
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||
"echo"
|
||||
|
||||
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CFG_BOOTFILE \
|
||||
"netdev=eth0\0" \
|
||||
"consdev=ttyS0\0" \
|
||||
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath\0" \
|
||||
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||
"addip=setenv bootargs $bootargs " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
|
||||
":$hostname:$netdev:off panic=1\0" \
|
||||
"addcons=setenv bootargs $bootargs " \
|
||||
"console=$consdev,$baudrate\0" \
|
||||
"flash_nfs=run nfsargs addip addcons;" \
|
||||
"bootm $kernel_addr\0" \
|
||||
"flash_self=run ramargs addip addcons;" \
|
||||
"bootm $kernel_addr $ramdisk_addr\0" \
|
||||
"net_nfs=tftp $loadaddr $bootfile;" \
|
||||
"run nfsargs addip addcons;bootm\0" \
|
||||
"rootpath=/opt/eldk/ppc_85xx\0" \
|
||||
"kernel_addr=FE000000\0" \
|
||||
"ramdisk_addr=FE100000\0" \
|
||||
"load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
|
||||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b 100000 fffc0000 40000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
@ -197,6 +197,10 @@ static int init_baudrate (void)
|
||||
|
||||
/***********************************************************************/
|
||||
|
||||
#ifdef CONFIG_ADD_RAM_INFO
|
||||
void board_add_ram_info(int);
|
||||
#endif
|
||||
|
||||
static int init_func_ram (void)
|
||||
{
|
||||
#ifdef CONFIG_BOARD_TYPES
|
||||
@ -207,7 +211,11 @@ static int init_func_ram (void)
|
||||
puts ("DRAM: ");
|
||||
|
||||
if ((gd->ram_size = initdram (board_type)) > 0) {
|
||||
print_size (gd->ram_size, "\n");
|
||||
print_size (gd->ram_size, "");
|
||||
#ifdef CONFIG_ADD_RAM_INFO
|
||||
board_add_ram_info(0);
|
||||
#endif
|
||||
putc('\n');
|
||||
return (0);
|
||||
}
|
||||
puts (failed);
|
||||
|
||||
@ -157,9 +157,6 @@ int eth_initialize(bd_t *bis)
|
||||
#ifdef SCC_ENET
|
||||
scc_initialize(bis);
|
||||
#endif
|
||||
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
|
||||
fec_initialize(bis);
|
||||
#endif
|
||||
#if defined(CONFIG_MPC5xxx_FEC)
|
||||
mpc5xxx_fec_initialize(bis);
|
||||
#endif
|
||||
@ -193,6 +190,9 @@ int eth_initialize(bd_t *bis)
|
||||
tsec_initialize(bis, 3, CONFIG_MPC83XX_TSEC4_NAME);
|
||||
# endif
|
||||
#endif
|
||||
#if defined(FEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
|
||||
fec_initialize(bis);
|
||||
#endif
|
||||
#if defined(CONFIG_AU1X00)
|
||||
au1x00_enet_initialize(bis);
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user