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ARM: socfpga: clk: Convert to clock framework
Use clock framework functions to fetch clock information now that there is a clock driver for Arria10, instead of custom coded register parsing. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Marek Vasut
parent
12ea13ad43
commit
d81b5da3fe
@ -903,50 +903,6 @@ void cm_use_intosc(void)
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CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
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}
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unsigned int cm_get_noc_clk_hz(void)
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{
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unsigned int clk_src, divisor, nocclk, src_hz;
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nocclk = readl(&clock_manager_base->main_pll.nocclk);
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clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) &
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CLKMGR_MAINPLL_NOCCLK_SRC_MSK;
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divisor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK);
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if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) {
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src_hz = cm_get_main_vco_clk_hz();
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src_hz /= 1 +
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(readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET) &
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CLKMGR_MAINPLL_NOCCLK_CNT_MSK);
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} else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) {
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src_hz = cm_get_per_vco_clk_hz();
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src_hz /= 1 +
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((readl(SOCFPGA_CLKMGR_ADDRESS +
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CLKMGR_MAINPLL_NOC_CLK_OFFSET) >>
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CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
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CLKMGR_MAINPLL_NOCCLK_CNT_MSK);
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} else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) {
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src_hz = eosc1_hz;
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} else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) {
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src_hz = cb_intosc_hz;
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} else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) {
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src_hz = f2s_free_hz;
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} else {
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src_hz = 0;
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}
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return src_hz / divisor;
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}
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unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift)
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{
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unsigned int divisor2 = 1 <<
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((readl(&clock_manager_base->main_pll.nocdiv) >>
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nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK);
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return cm_get_noc_clk_hz() / divisor2;
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}
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int cm_basic_init(const void *blob)
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{
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struct mainpll_cfg main_cfg;
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@ -964,199 +920,71 @@ int cm_basic_init(const void *blob)
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return cm_full_cfg(&main_cfg, &per_cfg);
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}
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static u32 cm_get_rate_dm(char *name)
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{
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struct uclass *uc;
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struct udevice *dev = NULL;
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struct clk clk = { 0 };
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ulong rate;
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int ret;
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/* Device addresses start at 1 */
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ret = uclass_get(UCLASS_CLK, &uc);
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if (ret)
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return 0;
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ret = uclass_get_device_by_name(UCLASS_CLK, name, &dev);
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if (ret)
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return 0;
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ret = device_probe(dev);
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if (ret)
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return 0;
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ret = clk_request(dev, &clk);
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if (ret)
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return 0;
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rate = clk_get_rate(&clk);
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clk_free(&clk);
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return rate;
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}
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static u32 cm_get_rate_dm_khz(char *name)
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{
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return cm_get_rate_dm(name) / 1000;
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}
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unsigned long cm_get_mpu_clk_hz(void)
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{
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u32 reg, clk_hz;
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u32 clk_src, mainmpuclk_reg;
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mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk);
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clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) &
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CLKMGR_MAINPLL_MPUCLK_SRC_MSK;
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reg = readl(&clock_manager_base->altera.mpuclk);
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/* Check MPU clock source: main, periph, osc1, intosc or f2s? */
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switch (clk_src) {
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case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
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clk_hz = cm_get_main_vco_clk_hz();
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clk_hz /= (reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
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break;
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case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
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clk_hz = cm_get_per_vco_clk_hz();
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clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
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CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1);
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break;
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case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
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clk_hz = eosc1_hz;
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break;
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case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
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clk_hz = cb_intosc_hz;
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break;
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case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
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clk_hz = f2s_free_hz;
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break;
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default:
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printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src);
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return 0;
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}
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clk_hz /= (mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
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return clk_hz;
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}
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unsigned int cm_get_per_vco_clk_hz(void)
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{
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u32 src_hz = 0;
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u32 clk_src = 0;
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u32 numer = 0;
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u32 denom = 0;
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u32 vco = 0;
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clk_src = readl(&clock_manager_base->per_pll.vco0);
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clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) &
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CLKMGR_PERPLL_VCO0_PSRC_MSK;
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if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) {
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src_hz = eosc1_hz;
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} else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) {
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src_hz = cb_intosc_hz;
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} else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) {
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src_hz = f2s_free_hz;
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} else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) {
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src_hz = cm_get_main_vco_clk_hz();
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src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) &
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CLKMGR_MAINPLL_CNTRCLK_MSK) + 1;
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} else {
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printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src);
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return 0;
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}
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vco = readl(&clock_manager_base->per_pll.vco1);
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numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK;
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denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) &
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CLKMGR_PERPLL_VCO1_DENOM_MSK;
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vco = src_hz;
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vco /= 1 + denom;
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vco *= 1 + numer;
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return vco;
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}
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unsigned int cm_get_main_vco_clk_hz(void)
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{
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u32 src_hz, numer, denom, vco;
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u32 clk_src = readl(&clock_manager_base->main_pll.vco0);
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clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) &
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CLKMGR_MAINPLL_VCO0_PSRC_MSK;
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if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) {
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src_hz = eosc1_hz;
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} else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) {
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src_hz = cb_intosc_hz;
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} else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) {
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src_hz = f2s_free_hz;
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} else {
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printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src);
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return 0;
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}
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vco = readl(&clock_manager_base->main_pll.vco1);
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numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK;
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denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
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CLKMGR_MAINPLL_VCO1_DENOM_MSK;
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vco = src_hz;
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vco /= 1 + denom;
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vco *= 1 + numer;
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return vco;
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}
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unsigned int cm_get_l4_sp_clk_hz(void)
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{
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return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB);
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}
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unsigned int cm_get_mmc_controller_clk_hz(void)
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{
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u32 clk_hz = 0;
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u32 clk_input = 0;
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clk_input = readl(&clock_manager_base->per_pll.cntr6clk);
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clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) &
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CLKMGR_PERPLLGRP_SRC_MSK;
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switch (clk_input) {
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case CLKMGR_PERPLLGRP_SRC_MAIN:
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clk_hz = cm_get_main_vco_clk_hz();
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clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
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CLKMGR_MAINPLL_CNTRCLK_MSK);
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break;
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case CLKMGR_PERPLLGRP_SRC_PERI:
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clk_hz = cm_get_per_vco_clk_hz();
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clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
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CLKMGR_PERPLL_CNTRCLK_MSK);
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break;
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case CLKMGR_PERPLLGRP_SRC_OSC1:
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clk_hz = eosc1_hz;
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break;
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case CLKMGR_PERPLLGRP_SRC_INTOSC:
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clk_hz = cb_intosc_hz;
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break;
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case CLKMGR_PERPLLGRP_SRC_FPGA:
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clk_hz = f2s_free_hz;
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break;
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}
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return clk_hz / 4;
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}
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unsigned int cm_get_spi_controller_clk_hz(void)
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{
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return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
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return cm_get_rate_dm("main_mpu_base_clk");
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}
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unsigned int cm_get_qspi_controller_clk_hz(void)
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{
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return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
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return cm_get_rate_dm("qspi_clk");
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}
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/* Override weak dw_spi_get_clk implementation in designware_spi.c driver */
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int dw_spi_get_clk(struct udevice *bus, ulong *rate)
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unsigned int cm_get_l4_sp_clk_hz(void)
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{
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*rate = cm_get_spi_controller_clk_hz();
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return 0;
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return cm_get_rate_dm("l4_sp_clk");
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}
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void cm_print_clock_quick_summary(void)
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{
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printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
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printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
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printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
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printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
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printf("EOSC1 %8d kHz\n", eosc1_hz / 1000);
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printf("cb_intosc %8d kHz\n", cb_intosc_hz / 1000);
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printf("f2s_free %8d kHz\n", f2s_free_hz / 1000);
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printf("Main VCO %8d kHz\n", cm_get_main_vco_clk_hz() / 1000);
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printf("NOC %8d kHz\n", cm_get_noc_clk_hz() / 1000);
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printf("L4 Main %8d kHz\n",
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cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000);
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printf("L4 MP %8d kHz\n",
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cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000);
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printf("L4 SP %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
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printf("L4 sys free %8d kHz\n", cm_get_noc_clk_hz() / 4000);
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printf("MPU %10d kHz\n", cm_get_rate_dm_khz("main_mpu_base_clk"));
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printf("MMC %8d kHz\n", cm_get_rate_dm_khz("sdmmc_clk"));
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printf("QSPI %8d kHz\n", cm_get_rate_dm_khz("qspi_clk"));
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printf("SPI %8d kHz\n", cm_get_rate_dm_khz("spi_m_clk"));
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printf("EOSC1 %8d kHz\n", cm_get_rate_dm_khz("osc1"));
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printf("cb_intosc %8d kHz\n", cm_get_rate_dm_khz("cb_intosc_ls_clk"));
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printf("f2s_free %8d kHz\n", cm_get_rate_dm_khz("f2s_free_clk"));
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printf("Main VCO %8d kHz\n", cm_get_rate_dm_khz("main_pll@40"));
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printf("NOC %8d kHz\n", cm_get_rate_dm_khz("main_noc_base_clk"));
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printf("L4 Main %8d kHz\n", cm_get_rate_dm_khz("l4_main_clk"));
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printf("L4 MP %8d kHz\n", cm_get_rate_dm_khz("l4_mp_clk"));
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printf("L4 SP %8d kHz\n", cm_get_rate_dm_khz("l4_sp_clk"));
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printf("L4 sys free %8d kHz\n", cm_get_rate_dm_khz("l4_sys_free_clk"));
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}
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@ -90,18 +90,12 @@ struct socfpga_clock_manager {
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};
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void cm_use_intosc(void);
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unsigned int cm_get_noc_clk_hz(void);
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unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift);
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int cm_basic_init(const void *blob);
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unsigned int cm_get_l4_sp_clk_hz(void);
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unsigned int cm_get_main_vco_clk_hz(void);
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unsigned int cm_get_per_vco_clk_hz(void);
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unsigned long cm_get_mpu_clk_hz(void);
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unsigned int cm_get_qspi_controller_clk_hz(void);
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unsigned int cm_get_mmc_controller_clk_hz(void);
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unsigned int cm_get_spi_controller_clk_hz(void);
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#endif /* __ASSEMBLER__ */
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