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* PPC405EP: Add support for board configuration of CPC0_PCI register

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This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
Patch by Tolunay Orkun, 07 Apr 2006
This commit is contained in:
Stefan Roese 2006-10-12 19:50:17 +02:00
parent e0a46554c3
commit d7762337cb
2 changed files with 9 additions and 1 deletions
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4
CHANGELOG
View File

@ -2,6 +2,10 @@
Changes since U-Boot 1.1.4: Changes since U-Boot 1.1.4:
====================================================================== ======================================================================
* PPC405EP: Add support for board configuration of CPC0_PCI register
This is needed to be able to configure PerWE*/PCI_INT* pin as PerWE*
Patch by Tolunay Orkun, 07 Apr 2006
* PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely. * PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.
- Add configuration of Open Drain GPIO Output selection - Add configuration of Open Drain GPIO Output selection
- Add configuration of initial value of GPIO output pins - Add configuration of initial value of GPIO output pins

6
cpu/ppc4xx/start.S
View File

@ -1697,7 +1697,8 @@ ppc405ep_init:
mtdcr ebccfgd,r3 mtdcr ebccfgd,r3
#endif #endif
addi r3,0,CPC0_PCI_HOST_CFG_EN #ifndef CFG_CPC0_PCI
li r3,CPC0_PCI_HOST_CFG_EN
#ifdef CONFIG_BUBINGA #ifdef CONFIG_BUBINGA
/* /*
!----------------------------------------------------------------------- !-----------------------------------------------------------------------
@ -1712,6 +1713,9 @@ ppc405ep_init:
beq ..pci_cfg_set /* if not set, then bypass reg write*/ beq ..pci_cfg_set /* if not set, then bypass reg write*/
#endif #endif
ori r3,r3,CPC0_PCI_ARBIT_EN ori r3,r3,CPC0_PCI_ARBIT_EN
#else /* CFG_CPC0_PCI */
li r3,CFG_CPC0_PCI
#endif /* CFG_CPC0_PCI */
..pci_cfg_set: ..pci_cfg_set:
mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/ mtdcr CPC0_PCI, r3 /* Enable internal arbiter*/