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dt-bindings: clock: rk3328: sync from upstream Linux kernel

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This syncs the rk3328 clock header file from Linux kernel next-20200324,
to support newer hardware blocks when syncing the device tree files.

The last non-merge commit to touch it was

    0dc14b013f79 ("clk: rockchip: add clock id for watchdog pclk on rk3328")

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
This commit is contained in:
Chen-Yu Tsai 2020-04-27 14:52:49 +08:00 committed by Kever Yang
parent 32fd6169a1
commit d751b0c000
1 changed files with 106 additions and 106 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

212
include/dt-bindings/clock/rk3328-cru.h
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
* Copyright (c) 2016 Rockchip Electronics Co. Ltd.
* Author: Elaine <zhangqing@rock-chips.com>
*/
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
@ -90,119 +91,118 @@
#define SCLK_MAC2IO_EXT 102
/* dclk gates */
#define DCLK_LCDC 180
#define DCLK_HDMIPHY 181
#define HDMIPHY 182
#define USB480M 183
#define DCLK_LCDC_SRC 184
#define DCLK_LCDC 120
#define DCLK_HDMIPHY 121
#define HDMIPHY 122
#define USB480M 123
#define DCLK_LCDC_SRC 124
/* aclk gates */
#define ACLK_AXISRAM 190
#define ACLK_VOP_PRE 191
#define ACLK_USB3OTG 192
#define ACLK_RGA_PRE 193
#define ACLK_DMAC 194
#define ACLK_GPU 195
#define ACLK_BUS_PRE 196
#define ACLK_PERI_PRE 197
#define ACLK_RKVDEC_PRE 198
#define ACLK_RKVDEC 199
#define ACLK_RKVENC 200
#define ACLK_VPU_PRE 201
#define ACLK_VIO_PRE 202
#define ACLK_VPU 203
#define ACLK_VIO 204
#define ACLK_VOP 205
#define ACLK_GMAC 206
#define ACLK_H265 207
#define ACLK_H264 208
#define ACLK_MAC2PHY 209
#define ACLK_MAC2IO 210
#define ACLK_DCF 211
#define ACLK_TSP 212
#define ACLK_PERI 213
#define ACLK_RGA 214
#define ACLK_IEP 215
#define ACLK_CIF 216
#define ACLK_HDCP 217
#define ACLK_AXISRAM 130
#define ACLK_VOP_PRE 131
#define ACLK_USB3OTG 132
#define ACLK_RGA_PRE 133
#define ACLK_DMAC 134
#define ACLK_GPU 135
#define ACLK_BUS_PRE 136
#define ACLK_PERI_PRE 137
#define ACLK_RKVDEC_PRE 138
#define ACLK_RKVDEC 139
#define ACLK_RKVENC 140
#define ACLK_VPU_PRE 141
#define ACLK_VIO_PRE 142
#define ACLK_VPU 143
#define ACLK_VIO 144
#define ACLK_VOP 145
#define ACLK_GMAC 146
#define ACLK_H265 147
#define ACLK_H264 148
#define ACLK_MAC2PHY 149
#define ACLK_MAC2IO 150
#define ACLK_DCF 151
#define ACLK_TSP 152
#define ACLK_PERI 153
#define ACLK_RGA 154
#define ACLK_IEP 155
#define ACLK_CIF 156
#define ACLK_HDCP 157
/* pclk gates */
#define PCLK_GPIO0 300
#define PCLK_GPIO1 301
#define PCLK_GPIO2 302
#define PCLK_GPIO3 303
#define PCLK_GRF 304
#define PCLK_I2C0 305
#define PCLK_I2C1 306
#define PCLK_I2C2 307
#define PCLK_I2C3 308
#define PCLK_SPI 309
#define PCLK_UART0 310
#define PCLK_UART1 311
#define PCLK_UART2 312
#define PCLK_TSADC 313
#define PCLK_PWM 314
#define PCLK_TIMER 315
#define PCLK_BUS_PRE 316
#define PCLK_PERI_PRE 317
#define PCLK_HDMI_CTRL 318
#define PCLK_HDMI_PHY 319
#define PCLK_GMAC 320
#define PCLK_H265 321
#define PCLK_MAC2PHY 322
#define PCLK_MAC2IO 323
#define PCLK_USB3PHY_OTG 324
#define PCLK_USB3PHY_PIPE 325
#define PCLK_USB3_GRF 326
#define PCLK_USB2_GRF 327
#define PCLK_HDMIPHY 328
#define PCLK_DDR 329
#define PCLK_PERI 330
#define PCLK_HDMI 331
#define PCLK_HDCP 332
#define PCLK_DCF 333
#define PCLK_SARADC 334
#define PCLK_GPIO0 200
#define PCLK_GPIO1 201
#define PCLK_GPIO2 202
#define PCLK_GPIO3 203
#define PCLK_GRF 204
#define PCLK_I2C0 205
#define PCLK_I2C1 206
#define PCLK_I2C2 207
#define PCLK_I2C3 208
#define PCLK_SPI 209
#define PCLK_UART0 210
#define PCLK_UART1 211
#define PCLK_UART2 212
#define PCLK_TSADC 213
#define PCLK_PWM 214
#define PCLK_TIMER 215
#define PCLK_BUS_PRE 216
#define PCLK_PERI_PRE 217
#define PCLK_HDMI_CTRL 218
#define PCLK_HDMI_PHY 219
#define PCLK_GMAC 220
#define PCLK_H265 221
#define PCLK_MAC2PHY 222
#define PCLK_MAC2IO 223
#define PCLK_USB3PHY_OTG 224
#define PCLK_USB3PHY_PIPE 225
#define PCLK_USB3_GRF 226
#define PCLK_USB2_GRF 227
#define PCLK_HDMIPHY 228
#define PCLK_DDR 229
#define PCLK_PERI 230
#define PCLK_HDMI 231
#define PCLK_HDCP 232
#define PCLK_DCF 233
#define PCLK_SARADC 234
#define PCLK_ACODECPHY 235
#define PCLK_WDT 236
/* hclk gates */
#define HCLK_PERI 408
#define HCLK_TSP 409
#define HCLK_GMAC 410
#define HCLK_I2S0_8CH 411
#define HCLK_I2S1_8CH 413
#define HCLK_I2S2_2CH 413
#define HCLK_SPDIF_8CH 414
#define HCLK_VOP 415
#define HCLK_NANDC 416
#define HCLK_SDMMC 417
#define HCLK_SDIO 418
#define HCLK_EMMC 419
#define HCLK_SDMMC_EXT 420
#define HCLK_RKVDEC_PRE 421
#define HCLK_RKVDEC 422
#define HCLK_RKVENC 423
#define HCLK_VPU_PRE 424
#define HCLK_VIO_PRE 425
#define HCLK_VPU 426
#define HCLK_VIO 427
#define HCLK_BUS_PRE 428
#define HCLK_PERI_PRE 429
#define HCLK_H264 430
#define HCLK_CIF 431
#define HCLK_OTG_PMU 432
#define HCLK_OTG 433
#define HCLK_HOST0 434
#define HCLK_HOST0_ARB 435
#define HCLK_CRYPTO_MST 436
#define HCLK_CRYPTO_SLV 437
#define HCLK_PDM 438
#define HCLK_IEP 439
#define HCLK_RGA 440
#define HCLK_HDCP 441
#define HCLK_PERI 308
#define HCLK_TSP 309
#define HCLK_GMAC 310
#define HCLK_I2S0_8CH 311
#define HCLK_I2S1_8CH 312
#define HCLK_I2S2_2CH 313
#define HCLK_SPDIF_8CH 314
#define HCLK_VOP 315
#define HCLK_NANDC 316
#define HCLK_SDMMC 317
#define HCLK_SDIO 318
#define HCLK_EMMC 319
#define HCLK_SDMMC_EXT 320
#define HCLK_RKVDEC_PRE 321
#define HCLK_RKVDEC 322
#define HCLK_RKVENC 323
#define HCLK_VPU_PRE 324
#define HCLK_VIO_PRE 325
#define HCLK_VPU 326
#define HCLK_BUS_PRE 328
#define HCLK_PERI_PRE 329
#define HCLK_H264 330
#define HCLK_CIF 331
#define HCLK_OTG_PMU 332
#define HCLK_OTG 333
#define HCLK_HOST0 334
#define HCLK_HOST0_ARB 335
#define HCLK_CRYPTO_MST 336
#define HCLK_CRYPTO_SLV 337
#define HCLK_PDM 338
#define HCLK_IEP 339
#define HCLK_RGA 340
#define HCLK_HDCP 341
#define CLK_NR_CLKS (HCLK_HDCP + 1)
#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
/* soft-reset indices */
#define SRST_CORE0_PO 0
#define SRST_CORE1_PO 1