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ARM: DRA7: emif: Fix disabling/enabling of refreshes

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clrsetbits_le32/clrbits_le32 takes mask of the bits as input that
are needed to be set/clear. But emif driver passes the shift of the bits.
Fixing it here.

Reported-by: Mark Mckeown <m-mckeown@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Lokesh Vutla 2015-08-28 12:28:25 +05:30 committed by Tom Rini
parent bab8d1e228
commit d6927a5d10
1 changed files with 3 additions and 3 deletions
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6
arch/arm/cpu/armv7/omap-common/emif-common.c
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@ -294,8 +294,8 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
EMIF_REG_PHY_FIFO_WE_IN_MISALINED_CLR);
/* Disable refreshed before leveling */
clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT,
EMIF_REG_INITREF_DIS_SHIFT);
clrsetbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK,
EMIF_REG_INITREF_DIS_MASK);
/* Start Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
@ -309,7 +309,7 @@ static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
}
/* Enable refreshes after leveling */
clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_SHIFT);
clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
debug("HW leveling success\n");
/*