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https://github.com/u-boot/u-boot.git
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arm: ls102xa: Add QSPI boot support for LS1021AQDS/TWR board
This patch adds QSPI boot support for LS1021AQDS/TWR board. The QSPI boot image need to be programmed into the QSPI flash first. Then the booting will start from QSPI memory space. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Alison Wang
York Sun
parent
4c59ab9cfb
commit
d612f0ab34
@ -98,6 +98,7 @@ struct ccsr_gur {
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#define SCFG_ETSECDMAMCR_LE_BD_FR 0xf8001a0f
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#define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
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#define SCFG_PIXCLKCR_PXCKEN 0x80000000
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#define SCFG_QSPI_CLKSEL 0xc0100000
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/* Supplemental Configuration Unit */
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struct ccsr_scfg {
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@ -7,3 +7,4 @@ F: configs/ls1021aqds_nor_defconfig
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F: configs/ls1021aqds_ddr4_nor_defconfig
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F: configs/ls1021aqds_nor_SECURE_BOOT_defconfig
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F: configs/ls1021aqds_sdcard_defconfig
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F: configs/ls1021aqds_qspi_defconfig
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@ -34,7 +34,9 @@ enum {
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int checkboard(void)
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{
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#ifndef CONFIG_QSPI_BOOT
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char buf[64];
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#endif
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#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
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u8 sw;
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#endif
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@ -61,12 +63,14 @@ int checkboard(void)
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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#endif
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#ifndef CONFIG_QSPI_BOOT
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printf("Sys ID:0x%02x, Sys Ver: 0x%02x\n",
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QIXIS_READ(id), QIXIS_READ(arch));
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printf("FPGA: v%d (%s), build %d\n",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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#endif
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return 0;
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}
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@ -164,6 +168,10 @@ int board_early_init_f(void)
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init_early_memctl_regs();
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#endif
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#ifdef CONFIG_FSL_QSPI
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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/* Workaround for the issue that DDR could not respond to
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* barrier transaction which is generated by executing DSB/ISB
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* instruction. Set CCI-400 control override register to
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@ -6,3 +6,4 @@ F: include/configs/ls1021atwr.h
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F: configs/ls1021atwr_nor_defconfig
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F: configs/ls1021atwr_nor_SECURE_BOOT_defconfig
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F: configs/ls1021atwr_sdcard_defconfig
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F: configs/ls1021atwr_qspi_defconfig
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@ -72,6 +72,7 @@ struct cpld_data {
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u8 rev2; /* Reserved */
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};
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#ifndef CONFIG_QSPI_BOOT
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static void convert_serdes_mux(int type, int need_reset);
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void cpld_show(void)
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@ -107,11 +108,14 @@ void cpld_show(void)
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in_8(&cpld_data->serdes_mux));
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#endif
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}
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#endif
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int checkboard(void)
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{
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puts("Board: LS1021ATWR\n");
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#ifndef CONFIG_QSPI_BOOT
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cpld_show();
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#endif
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return 0;
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}
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@ -220,6 +224,7 @@ int board_eth_init(bd_t *bis)
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}
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#endif
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#ifndef CONFIG_QSPI_BOOT
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int config_serdes_mux(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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@ -251,6 +256,7 @@ int config_serdes_mux(void)
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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@ -269,6 +275,10 @@ int board_early_init_f(void)
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out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
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#endif
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#ifdef CONFIG_FSL_QSPI
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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return 0;
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}
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@ -305,8 +315,10 @@ int board_init(void)
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#ifndef CONFIG_SYS_FSL_NO_SERDES
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fsl_serdes_init();
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#ifndef CONFIG_QSPI_BOOT
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config_serdes_mux();
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#endif
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#endif
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#ifdef CONFIG_U_QE
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u_qe_init();
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@ -354,6 +366,7 @@ u16 flash_read16(void *addr)
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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#ifndef CONFIG_QSPI_BOOT
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static void convert_flash_bank(char bank)
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{
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struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
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@ -536,3 +549,4 @@ U_BOOT_CMD(
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" -change lane C & lane D to PCIeX2\n"
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"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
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);
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#endif
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3
configs/ls1021aqds_qspi_defconfig
Normal file
3
configs/ls1021aqds_qspi_defconfig
Normal file
@ -0,0 +1,3 @@
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CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
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+S:CONFIG_ARM=y
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+S:CONFIG_TARGET_LS1021AQDS=y
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3
configs/ls1021atwr_qspi_defconfig
Normal file
3
configs/ls1021atwr_qspi_defconfig
Normal file
@ -0,0 +1,3 @@
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CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
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+S:CONFIG_ARM=y
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+S:CONFIG_TARGET_LS1021ATWR=y
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@ -37,8 +37,14 @@ unsigned long get_board_sys_clk(void);
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unsigned long get_board_ddr_clk(void);
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#endif
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define CONFIG_QIXIS_I2C_ACCESS
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#else
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#endif
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
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@ -73,6 +79,11 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#endif
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_SYS_TEXT_BASE 0x40010000
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#define CONFIG_SYS_NO_FLASH
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0x67f80000
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#endif
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@ -112,6 +123,7 @@ unsigned long get_board_ddr_clk(void);
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/*
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* IFC Definitions
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*/
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#ifndef CONFIG_QSPI_BOOT
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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@ -204,6 +216,7 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#endif
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/*
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* QIXIS Definitions
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@ -316,6 +329,18 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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/* QSPI */
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_FSL_QSPI
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#define QSPI0_AMBA_BASE 0x40000000
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_SPANSION
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#endif
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/*
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* USB
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*/
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@ -394,7 +419,11 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_EDITING
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#ifdef CONFIG_QSPI_BOOT
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#undef CONFIG_CMD_IMLS
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#else
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#define CONFIG_CMD_IMLS
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#endif
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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@ -458,6 +487,11 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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@ -67,6 +67,11 @@
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#endif
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_SYS_TEXT_BASE 0x40010000
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#define CONFIG_SYS_NO_FLASH
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#endif
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#ifndef CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_TEXT_BASE 0x67f80000
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#endif
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@ -90,6 +95,7 @@
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/*
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* IFC Definitions
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*/
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#ifndef CONFIG_QSPI_BOOT
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#define CONFIG_FSL_IFC
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
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@ -133,6 +139,7 @@
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#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
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#define CONFIG_SYS_WRITE_SWAPPED_DATA
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#endif
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/* CPLD */
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@ -216,6 +223,18 @@
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#define CONFIG_CMD_FAT
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#define CONFIG_DOS_PARTITION
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/* QSPI */
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_FSL_QSPI
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#define QSPI0_AMBA_BASE 0x40000000
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#define FSL_QSPI_FLASH_SIZE (1 << 24)
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#define FSL_QSPI_FLASH_NUM 2
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#define CONFIG_CMD_SF
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#define CONFIG_SPI_FLASH
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#define CONFIG_SPI_FLASH_STMICRO
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#endif
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/*
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* Video
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*/
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@ -287,7 +306,11 @@
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_CMDLINE_EDITING
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#ifdef CONFIG_QSPI_BOOT
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#undef CONFIG_CMD_IMLS
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#else
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#define CONFIG_CMD_IMLS
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#endif
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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@ -350,6 +373,11 @@
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#define CONFIG_ENV_IS_IN_MMC
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x20000
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#elif defined(CONFIG_QSPI_BOOT)
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#define CONFIG_ENV_IS_IN_SPI_FLASH
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_ENV_OFFSET 0x100000
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#define CONFIG_ENV_SECT_SIZE 0x10000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
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