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https://github.com/u-boot/u-boot.git
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hrcon: Use generic ioep-fpga support
The strider platform moved some generic code into ioep-fpga.c. Make use of that on hrcon platform. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
This commit is contained in:
Dirk Eibach
Tom Rini
parent
a3f9d6c779
commit
d4e5888801
@ -12,6 +12,6 @@ obj-$(CONFIG_IO64) += miiphybb.o
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obj-$(CONFIG_IOCON) += osd.o mclink.o dp501.o phy.o ch7301.o
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obj-$(CONFIG_DLVISION_10G) += osd.o dp501.o
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obj-$(CONFIG_CONTROLCENTERD) += dp501.o
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obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o
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obj-$(CONFIG_HRCON) += osd.o mclink.o dp501.o phy.o ioep-fpga.o
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obj-$(CONFIG_STRIDER) += mclink.o dp501.o phy.o ioep-fpga.o adv7611.o ch7301.o
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obj-$(CONFIG_STRIDER_CON) += osd.o
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@ -43,6 +43,7 @@ enum {
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enum {
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RAM_DDR2_32 = 0,
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RAM_DDR3_32 = 1,
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RAM_DDR3_48 = 2,
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};
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enum {
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@ -215,6 +216,10 @@ void ioep_fpga_print_info(unsigned int fpga)
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printf(", RAM 32 bit DDR3");
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break;
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case RAM_DDR3_48:
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printf(", RAM 48 bit DDR3");
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break;
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default:
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printf(", RAM %d(not supported)", feature_ramconfig);
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break;
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@ -22,6 +22,7 @@
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#include <gdsys_fpga.h>
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#include "../common/ioep-fpga.h"
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#include "../common/osd.h"
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#include "../common/mclink.h"
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#include "../common/phy.h"
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@ -35,57 +36,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define MAX_MUX_CHANNELS 2
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enum {
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UNITTYPE_MAIN_SERVER = 0,
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UNITTYPE_MAIN_USER = 1,
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UNITTYPE_VIDEO_SERVER = 2,
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UNITTYPE_VIDEO_USER = 3,
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};
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enum {
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UNITTYPEPCB_DVI = 0,
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UNITTYPEPCB_DP_165 = 1,
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UNITTYPEPCB_DP_300 = 2,
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UNITTYPEPCB_HDMI = 3,
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};
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enum {
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HWVER_100 = 0,
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HWVER_110 = 1,
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};
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enum {
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FPGA_HWVER_200 = 0,
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FPGA_HWVER_210 = 1,
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};
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enum {
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COMPRESSION_NONE = 0,
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COMPRESSION_TYPE1_DELTA = 1,
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COMPRESSION_TYPE1_TYPE2_DELTA = 3,
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};
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enum {
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AUDIO_NONE = 0,
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AUDIO_TX = 1,
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AUDIO_RX = 2,
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AUDIO_RXTX = 3,
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};
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enum {
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SYSCLK_147456 = 0,
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};
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enum {
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RAM_DDR2_32 = 0,
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RAM_DDR3_32 = 1,
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};
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enum {
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CARRIER_SPEED_1G = 0,
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CARRIER_SPEED_2_5G = 1,
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};
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enum {
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MCFPGA_DONE = 1 << 0,
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MCFPGA_INIT_N = 1 << 1,
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@ -164,191 +114,6 @@ int checkboard(void)
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return 0;
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}
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static void print_fpga_info(unsigned int fpga, bool rgmii2_present)
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{
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u16 versions;
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u16 fpga_version;
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u16 fpga_features;
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unsigned unit_type;
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unsigned unit_type_pcb_video;
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unsigned hardware_version;
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unsigned feature_compression;
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unsigned feature_osd;
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unsigned feature_audio;
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unsigned feature_sysclock;
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unsigned feature_ramconfig;
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unsigned feature_carrier_speed;
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unsigned feature_carriers;
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unsigned feature_video_channels;
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FPGA_GET_REG(fpga, versions, &versions);
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FPGA_GET_REG(fpga, fpga_version, &fpga_version);
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FPGA_GET_REG(fpga, fpga_features, &fpga_features);
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unit_type = (versions & 0xf000) >> 12;
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unit_type_pcb_video = (versions & 0x01c0) >> 6;
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feature_compression = (fpga_features & 0xe000) >> 13;
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feature_osd = fpga_features & (1<<11);
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feature_audio = (fpga_features & 0x0600) >> 9;
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feature_sysclock = (fpga_features & 0x0180) >> 7;
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feature_ramconfig = (fpga_features & 0x0060) >> 5;
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feature_carrier_speed = fpga_features & (1<<4);
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feature_carriers = (fpga_features & 0x000c) >> 2;
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feature_video_channels = fpga_features & 0x0003;
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switch (unit_type) {
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case UNITTYPE_MAIN_USER:
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printf("Mainchannel");
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break;
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case UNITTYPE_VIDEO_USER:
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printf("Videochannel");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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if (unit_type == UNITTYPE_MAIN_USER) {
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hardware_version =
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(!!pca9698_get_value(0x20, 24) << 0)
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| (!!pca9698_get_value(0x20, 25) << 1)
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| (!!pca9698_get_value(0x20, 26) << 2)
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| (!!pca9698_get_value(0x20, 27) << 3)
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| (!!pca9698_get_value(0x20, 28) << 4);
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switch (hardware_version) {
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case HWVER_100:
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printf(" HW-Ver 1.00,");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10,");
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break;
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default:
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printf(" HW-Ver %d(not supported),",
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hardware_version);
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break;
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}
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if (rgmii2_present)
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printf(" RGMII2,");
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}
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if (unit_type == UNITTYPE_VIDEO_USER) {
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hardware_version = versions & 0x000f;
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switch (hardware_version) {
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case FPGA_HWVER_200:
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printf(" HW-Ver 2.00,");
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break;
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case FPGA_HWVER_210:
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printf(" HW-Ver 2.10,");
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break;
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default:
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printf(" HW-Ver %d(not supported),",
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hardware_version);
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break;
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}
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}
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switch (unit_type_pcb_video) {
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case UNITTYPEPCB_DVI:
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printf(" DVI,");
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break;
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case UNITTYPEPCB_DP_165:
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printf(" DP 165MPix/s,");
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break;
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case UNITTYPEPCB_DP_300:
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printf(" DP 300MPix/s,");
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break;
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case UNITTYPEPCB_HDMI:
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printf(" HDMI,");
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break;
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}
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printf(" FPGA V %d.%02d\n features:",
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fpga_version / 100, fpga_version % 100);
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switch (feature_compression) {
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case COMPRESSION_NONE:
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printf(" no compression");
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break;
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case COMPRESSION_TYPE1_DELTA:
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printf(" type1-deltacompression");
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break;
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case COMPRESSION_TYPE1_TYPE2_DELTA:
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printf(" type1-deltacompression, type2-inlinecompression");
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break;
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default:
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printf(" compression %d(not supported)", feature_compression);
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break;
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}
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printf(", %sosd", feature_osd ? "" : "no ");
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switch (feature_audio) {
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case AUDIO_NONE:
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printf(", no audio");
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break;
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case AUDIO_TX:
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printf(", audio tx");
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break;
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case AUDIO_RX:
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printf(", audio rx");
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break;
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case AUDIO_RXTX:
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printf(", audio rx+tx");
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break;
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default:
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printf(", audio %d(not supported)", feature_audio);
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break;
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}
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puts(",\n ");
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switch (feature_sysclock) {
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case SYSCLK_147456:
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printf("clock 147.456 MHz");
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break;
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default:
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printf("clock %d(not supported)", feature_sysclock);
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break;
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}
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switch (feature_ramconfig) {
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case RAM_DDR2_32:
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printf(", RAM 32 bit DDR2");
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break;
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case RAM_DDR3_32:
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printf(", RAM 32 bit DDR3");
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break;
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default:
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printf(", RAM %d(not supported)", feature_ramconfig);
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break;
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}
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printf(", %d carrier(s) %s", feature_carriers,
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feature_carrier_speed ? "2.5Gbit/s" : "1Gbit/s");
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printf(", %d video channel(s)\n", feature_video_channels);
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}
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int last_stage_init(void)
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{
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int slaves;
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@ -401,7 +166,7 @@ int last_stage_init(void)
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slaves = mclink_probe();
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mclink_fpgacount = 0;
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print_fpga_info(0, ch0_rgmii2_present);
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ioep_fpga_print_info(0);
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osd_probe(0);
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if (slaves <= 0)
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@ -412,7 +177,7 @@ int last_stage_init(void)
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for (k = 1; k <= slaves; ++k) {
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FPGA_GET_REG(k, fpga_features, &fpga_features);
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print_fpga_info(k, false);
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ioep_fpga_print_info(k);
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osd_probe(k);
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if (hw_type_cat) {
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miiphy_register(bb_miiphy_buses[k].name,
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