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Use device tree for mpc85xx with binman. Enabled for T2080QDS.

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Merge tag 'mpc85xx-for-v2018.11-rc1' of git://git.denx.de/u-boot-mpc85xx

Use device tree for mpc85xx with binman. Enabled for T2080QDS.
This commit is contained in:
Tom Rini 2018-09-29 11:47:50 -04:00
commit d29a583161
25 changed files with 335 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
Makefile
View File

@ -861,6 +861,10 @@ ifneq ($(CONFIG_SYS_INIT_SP_BSS_OFFSET),)
ALL-y += init_sp_bss_offset_check
endif
ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
ALL-y += u-boot-with-dtb.bin
endif
LDFLAGS_u-boot += $(LDFLAGS_FINAL)
# Avoid 'Not enough room for program headers' error on binutils 2.28 onwards.
@ -983,7 +987,8 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE
$(call if_changed,objcopy)
OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)
$(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR),-R .bootpg -R .resetvec)
OBJCOPYFLAGS_u-boot-spl.hex = $(OBJCOPYFLAGS_u-boot.hex)
@ -1207,6 +1212,18 @@ u-boot-with-spl.sfp: spl/u-boot-spl.sfp u-boot.img FORCE
$(call if_changed,socboot)
endif
ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
u-boot-with-dtb.bin: u-boot.bin u-boot.dtb \
$(if $(CONFIG_MPC85XX_HAVE_RESET_VECTOR), u-boot-br.bin) FORCE
$(call if_changed,binman)
ifeq ($(CONFIG_MPC85XX_HAVE_RESET_VECTOR),y)
OBJCOPYFLAGS_u-boot-br.bin := -O binary -j .bootpg -j .resetvec
u-boot-br.bin: u-boot FORCE
$(call if_changed,objcopy)
endif
endif
# x86 uses a large ROM. We fill it with 0xff, put the 16-bit stuff (including
# reset vector) at the top, Intel ME descriptor at the bottom, and U-Boot in
# the middle. This is handled by binman based on an image description in the
@ -1301,8 +1318,12 @@ spl/u-boot-spl.pbl: spl/u-boot-spl.bin FORCE
ifeq ($(ARCH),arm)
UBOOT_BINLOAD := u-boot.img
else
ifeq ($(CONFIG_MPC85xx)$(CONFIG_OF_SEPARATE),yy)
UBOOT_BINLOAD := u-boot-with-dtb.bin
else
UBOOT_BINLOAD := u-boot.bin
endif
endif
OBJCOPYFLAGS_u-boot-with-spl-pbl.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \
--gap-fill=0xff

1
arch/powerpc/Kconfig
View File

@ -20,6 +20,7 @@ config MPC85xx
select CREATE_ARCH_SYMLINK
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select BINMAN
imply CMD_HASH
imply CMD_IRQ
imply USB_EHCI_HCD if USB

4
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -1143,6 +1143,10 @@ config ARCH_T4240
imply CMD_REGINFO
imply FSL_SATA
config MPC85XX_HAVE_RESET_VECTOR
bool "Indicate reset vector at CONFIG_RESET_VECTOR_ADDRESS - 0xffc"
depends on MPC85xx
config BOOKE
bool
default y

1
arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
View File

@ -74,6 +74,7 @@ SECTIONS
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
_end = .;
.bootpg ADDR(.text) - 0x1000 :
{

1
arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
View File

@ -42,6 +42,7 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
_end = .;
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{

1
arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
View File

@ -55,6 +55,7 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
_end = .;
#ifdef CONFIG_SPL_SKIP_RELOCATE
. = ALIGN(4);
__bss_start = .;

1
arch/powerpc/cpu/mpc85xx/u-boot.lds
View File

@ -81,6 +81,7 @@ SECTIONS
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
_end = .;
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
.bootpg ADDR(.text) - 0x1000 :

14
arch/powerpc/dts/Makefile Normal file
View File

@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0+
dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb
targets += $(dtb-y)
# Add any required device tree compiler flags here
DTC_FLAGS +=
PHONY += dtbs
dtbs: $(addprefix $(obj)/, $(dtb-y))
@:
clean-files := *.dtb

39
arch/powerpc/dts/e6500_power_isa.dtsi Normal file
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@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* e6500 Power ISA Device Tree Source (include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2018 NXP
*/
/ {
cpus {
power-isa-version = "2.06";
power-isa-b; // Base
power-isa-e; // Embedded
power-isa-atb; // Alternate Time Base
power-isa-cs; // Cache Specification
power-isa-ds; // Decorated Storage
power-isa-e.ed; // Embedded.Enhanced Debug
power-isa-e.pd; // Embedded.External PID
power-isa-e.hv; // Embedded.Hypervisor
power-isa-e.le; // Embedded.Little-Endian
power-isa-e.pm; // Embedded.Performance Monitor
power-isa-e.pc; // Embedded.Processor Control
power-isa-ecl; // Embedded Cache Locking
power-isa-exp; // External Proxy
power-isa-fp; // Floating Point
power-isa-fp.r; // Floating Point.Record
power-isa-mmc; // Memory Coherence
power-isa-scpm; // Store Conditional Page Mobility
power-isa-wt; // Wait
power-isa-64; // 64-bit
power-isa-e.pt; // Embedded.Page Table
power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT
power-isa-e.em; // Embedded Multi-Threading
power-isa-v; // Vector (AltiVec)
fsl,eref-er; // Enhanced Reservations
fsl,eref-deo; // Data Cache Extended Operations
mmu-type = "power-embedded";
};
};

62
arch/powerpc/dts/t2080.dtsi Normal file
View File

@ -0,0 +1,62 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* T2080/T2081 Silicon/SoC Device Tree Source (pre include)
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2018 NXP
*/
/dts-v1/;
/include/ "e6500_power_isa.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: PowerPC,e6500@0 {
device_type = "cpu";
reg = <0 1>;
fsl,portid-mapping = <0x80000000>;
};
cpu1: PowerPC,e6500@2 {
device_type = "cpu";
reg = <2 3>;
fsl,portid-mapping = <0x80000000>;
};
cpu2: PowerPC,e6500@4 {
device_type = "cpu";
reg = <4 5>;
fsl,portid-mapping = <0x80000000>;
};
cpu3: PowerPC,e6500@6 {
device_type = "cpu";
reg = <6 7>;
fsl,portid-mapping = <0x80000000>;
};
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
#address-cells = <1>;
#size-cells = <1>;
device_type = "soc";
compatible = "simple-bus";
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
};
};

17
arch/powerpc/dts/t2080qds.dts Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* T2080QDS Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2018 NXP
*/
/include/ "t2080.dtsi"
/ {
model = "fsl,T2080QDS";
compatible = "fsl,T2080QDS";
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
};

32
arch/powerpc/dts/u-boot.dtsi Normal file
View File

@ -0,0 +1,32 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
#include <config.h>
/ {
binman {
filename = "u-boot-with-dtb.bin";
skip-at-start = <CONFIG_SYS_TEXT_BASE>;
sort-by-offset;
pad-byte = <0xff>;
size = <CONFIG_SYS_MONITOR_LEN>;
u-boot-with-ucode-ptr {
offset = <CONFIG_SYS_TEXT_BASE>;
optional-ucode;
};
u-boot-dtb-with-ucode {
#ifdef CONFIG_MPC85xx
align = <256>;
#endif
};
#ifdef CONFIG_MPC85XX_HAVE_RESET_VECTOR
powerpc-mpc85xx-bootpg-resetvec {
offset = <(CONFIG_RESET_VECTOR_ADDRESS - 0xffc)>;
};
#endif
};
};

19
board/freescale/t208xqds/README
View File

@ -272,3 +272,22 @@ How to update the ucode of Freescale FMAN
For more details, please refer to T2080QDS User Guide and access
website www.freescale.com and Freescale QorIQ SDK Infocenter document.
Device tree support and how to enable it for different configs
--------------------------------------------------------------
Device tree support is available for t2080qds for below mentioned boot,
1. NOR Boot
2. NAND Boot
3. SD Boot
4. SPIFLASH Boot
To enable device tree support for other boot, below configs need to be
enabled in relative defconfig file,
1. CONFIG_DEFAULT_DEVICE_TREE="t2080qds" (Change default device tree name if required)
2. CONFIG_OF_CONTROL
3. CONFIG_MPC85XX_HAVE_RESET_VECTOR if reset vector is located at
CONFIG_RESET_VECTOR_ADDRESS - 0xffc
If device tree support is enabled in defconfig,
1. use 'u-boot-with-dtb.bin' for NOR boot.
2. use 'u-boot-with-spl-pbl.bin' for other boot.

3
configs/T2080QDS_NAND_defconfig
View File

@ -7,6 +7,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -35,6 +36,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_NAND=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
@ -54,4 +56,3 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

3
configs/T2080QDS_SDCARD_defconfig
View File

@ -8,6 +8,7 @@ CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
CONFIG_SPL=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -35,6 +36,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
@ -53,4 +55,3 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

3
configs/T2080QDS_SPIFLASH_defconfig
View File

@ -9,6 +9,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -36,6 +37,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
@ -54,4 +56,3 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

4
configs/T2080QDS_defconfig
View File

@ -2,6 +2,7 @@ CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xEFF40000
CONFIG_MPC85xx=y
CONFIG_TARGET_T2080QDS=y
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -24,6 +25,8 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t2080qds"
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_FSL_CAAM=y
CONFIG_FSL_ESDHC=y
@ -42,4 +45,3 @@ CONFIG_SPI=y
CONFIG_FSL_ESPI=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_OF_LIBFDT=y

2
dts/Makefile
View File

@ -61,4 +61,4 @@ dtbs: $(obj)/dt.dtb $(obj)/dt-spl.dtb
clean-files := dt.dtb.S dt-spl.dtb.S
# Let clean descend into dts directories
subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts
subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts

9
tools/binman/README
View File

@ -397,6 +397,15 @@ end-at-4gb:
8MB ROM, the offset of the first entry would be 0xfff80000 with
this option, instead of 0 without this option.
skip-at-start:
This property specifies the entry offset of the first entry.
For PowerPC mpc85xx based CPU, CONFIG_SYS_TEXT_BASE is the entry
offset of the first entry. It can be 0xeff40000 or 0xfff40000 for
nor flash boot, 0x201000 for sd boot etc.
'end-at-4gb' property is not applicable where CONFIG_SYS_TEXT_BASE +
Image size != 4gb.
Examples of the above options can be found in the tests. See the
tools/binman/test directory.

14
tools/binman/README.entries
View File

@ -221,6 +221,18 @@ See README.x86 for information about Intel binary blobs.
Entry: powerpc-mpc85xx-bootpg-resetvec: PowerPC mpc85xx bootpg + resetvec code for U-Boot
-----------------------------------------------------------------------------------------
Properties / Entry arguments:
- filename: Filename of u-boot-br.bin (default 'u-boot-br.bin')
This enrty is valid for PowerPC mpc85xx cpus. This entry holds
'bootpg + resetvec' code for PowerPC mpc85xx CPUs which needs to be
placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'.
Entry: section: Entry that contains other entries
-------------------------------------------------
@ -543,7 +555,7 @@ Properties / Entry arguments:
- kernelkey: Name of the kernel key to use (inside keydir)
- preamble-flags: Value of the vboot preamble flags (typically 0)
Chromium OS signs the read-write firmware and kernel, writing the signature
Chromium OS signs the read-write firmware and kernel, writing the signature
in this block. This allows U-Boot to verify that the next firmware stage
and kernel are genuine.

15
tools/binman/bsection.py
View File

@ -59,7 +59,7 @@ class Section(object):
self._pad_after = 0
self._pad_byte = 0
self._sort = False
self._skip_at_start = 0
self._skip_at_start = None
self._end_4gb = False
self._name_prefix = ''
self._entries = OrderedDict()
@ -79,10 +79,17 @@ class Section(object):
self._pad_byte = fdt_util.GetInt(self._node, 'pad-byte', 0)
self._sort = fdt_util.GetBool(self._node, 'sort-by-offset')
self._end_4gb = fdt_util.GetBool(self._node, 'end-at-4gb')
if self._end_4gb and not self._size:
self._Raise("Section size must be provided when using end-at-4gb")
self._skip_at_start = fdt_util.GetInt(self._node, 'skip-at-start')
if self._end_4gb:
self._skip_at_start = 0x100000000 - self._size
if not self._size:
self._Raise("Section size must be provided when using end-at-4gb")
if self._skip_at_start is not None:
self._Raise("Provide either 'end-at-4gb' or 'skip-at-start'")
else:
self._skip_at_start = 0x100000000 - self._size
else:
if self._skip_at_start is None:
self._skip_at_start = 0
self._name_prefix = fdt_util.GetString(self._node, 'name-prefix')
def _ReadEntries(self):

25
tools/binman/etype/powerpc_mpc85xx_bootpg_resetvec.py Normal file
View File

@ -0,0 +1,25 @@
# SPDX-License-Identifier: GPL-2.0+
# Copyright 2018 NXP
#
# Entry-type module for the PowerPC mpc85xx bootpg and resetvec code for U-Boot
#
from entry import Entry
from blob import Entry_blob
class Entry_powerpc_mpc85xx_bootpg_resetvec(Entry_blob):
"""PowerPC mpc85xx bootpg + resetvec code for U-Boot
Properties / Entry arguments:
- filename: Filename of u-boot-br.bin (default 'u-boot-br.bin')
This enrty is valid for PowerPC mpc85xx cpus. This entry holds
'bootpg + resetvec' code for PowerPC mpc85xx CPUs which needs to be
placed at offset 'RESET_VECTOR_ADDRESS - 0xffc'.
"""
def __init__(self, section, etype, node):
Entry_blob.__init__(self, section, etype, node)
def GetDefaultFilename(self):
return 'u-boot-br.bin'

16
tools/binman/ftest.py
View File

@ -39,6 +39,7 @@ U_BOOT_SPL_DTB_DATA = 'spldtb'
U_BOOT_TPL_DTB_DATA = 'tpldtb'
X86_START16_DATA = 'start16'
X86_START16_SPL_DATA = 'start16spl'
PPC_MPC85XX_BR_DATA = 'ppcmpc85xxbr'
U_BOOT_NODTB_DATA = 'nodtb with microcode pointer somewhere in here'
U_BOOT_SPL_NODTB_DATA = 'splnodtb with microcode pointer somewhere in here'
FSP_DATA = 'fsp'
@ -90,6 +91,7 @@ class TestFunctional(unittest.TestCase):
TestFunctional._MakeInputFile('vga.bin', VGA_DATA)
self._ResetDtbs()
TestFunctional._MakeInputFile('u-boot-x86-16bit.bin', X86_START16_DATA)
TestFunctional._MakeInputFile('u-boot-br.bin', PPC_MPC85XX_BR_DATA)
TestFunctional._MakeInputFile('spl/u-boot-x86-16bit-spl.bin',
X86_START16_SPL_DATA)
TestFunctional._MakeInputFile('u-boot-nodtb.bin', U_BOOT_NODTB_DATA)
@ -711,6 +713,14 @@ class TestFunctional(unittest.TestCase):
self.assertIn("Section '/binman': Section size must be provided when "
"using end-at-4gb", str(e.exception))
def test4gbAndSkipAtStartTogether(self):
"""Test that the end-at-4gb and skip-at-size property can't be used
together"""
with self.assertRaises(ValueError) as e:
self._DoTestFile('80_4gb_and_skip_at_start_together.dts')
self.assertIn("Section '/binman': Provide either 'end-at-4gb' or "
"'skip-at-start'", str(e.exception))
def testPackX86RomOutside(self):
"""Test that the end-at-4gb property checks for offset boundaries"""
with self.assertRaises(ValueError) as e:
@ -756,6 +766,12 @@ class TestFunctional(unittest.TestCase):
data = self._DoReadFile('33_x86-start16.dts')
self.assertEqual(X86_START16_DATA, data[:len(X86_START16_DATA)])
def testPackPowerpcMpc85xxBootpgResetvec(self):
"""Test that an image with powerpc-mpc85xx-bootpg-resetvec can be
created"""
data = self._DoReadFile('81_powerpc_mpc85xx_bootpg_resetvec.dts')
self.assertEqual(PPC_MPC85XX_BR_DATA, data[:len(PPC_MPC85XX_BR_DATA)])
def _RunMicrocodeTest(self, dts_fname, nodtb_data, ucode_second=False):
"""Handle running a test for insertion of microcode

21
tools/binman/test/80_4gb_and_skip_at_start_together.dts Normal file
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@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
binman {
size = <32>;
sort-by-offset;
end-at-4gb;
skip-at-start = <0xffffffe0>;
u-boot {
offset = <0xffffffe0>;
};
};
};

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tools/binman/test/81_powerpc_mpc85xx_bootpg_resetvec.dts Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
binman {
powerpc-mpc85xx-bootpg-resetvec {
};
};
};