mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-24 04:34:22 +08:00
- Add a new SMBIOS parser and enable it when booting from coreboot - Fix up various driver names to avoid dtoc warnings - Fully enable ACPI support on Google Chromebook Coral - Add a way to set SMBIOS properties using the devicetree - Update existing boards to use devicetree for SMBIOS using a new default sysinfo driver
This commit is contained in:
commit
d062c1344c
@ -198,6 +198,8 @@ config X86
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imply RTC_MC146818
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imply IRQ
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imply ACPIGEN if !QEMU
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imply SYSINFO if GENERATE_SMBIOS_TABLE
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imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
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# Thing to enable for when SPL/TPL are enabled: SPL
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imply SPL_DM
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|
@ -1,5 +1,25 @@
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// SPDX-License-Identifier: GPL-2.0+
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/ {
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smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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product = "uDPU";
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};
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baseboard {
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product = "uDPU";
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};
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chassis {
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product = "uDPU";
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};
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};
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};
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};
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&spi0 {
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u-boot,dm-pre-reloc;
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|
25
arch/arm/dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts
Normal file
25
arch/arm/dts/imx6ull-myir-mys-6ulx-eval-u-boot.dts
Normal file
@ -0,0 +1,25 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Linumiz
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* Author: Parthiban Nallathambi <parthiban@linumiz.com>
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*/
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/ {
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smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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manufacturer = "MYiR";
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};
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baseboard {
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manufacturer = "MYiR";
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};
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chassis {
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manufacturer = "MYiR";
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};
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};
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};
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};
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@ -6,6 +6,29 @@
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#include "meson-gx-u-boot.dtsi"
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/ {
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smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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manufacturer = "Hardkernel Co., Ltd.";
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product = "ODROID-C2";
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};
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baseboard {
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manufacturer = "Hardkernel Co., Ltd.";
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product = "ODROID-C2";
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};
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chassis {
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manufacturer = "Hardkernel Co., Ltd.";
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product = "ODROID-C2";
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};
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};
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};
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};
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&usb0 {
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status = "disabled";
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};
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|
@ -9,6 +9,27 @@
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
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};
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smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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manufacturer = "firefly";
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product = "roc-rk3328-cc";
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};
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baseboard {
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manufacturer = "firefly";
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product = "roc-rk3328-cc";
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};
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chassis {
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manufacturer = "firefly";
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product = "roc-rk3328-cc";
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};
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};
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};
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};
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&gpio0 {
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|
@ -6,6 +6,29 @@
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#include "rk3328-u-boot.dtsi"
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#include "rk3328-sdram-ddr3-666.dtsi"
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/ {
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smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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manufacturer = "radxa";
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product = "rock-pi-e_rk3328";
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};
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baseboard {
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manufacturer = "radxa";
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product = "rock-pi-e_rk3328";
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};
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chassis {
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manufacturer = "radxa";
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product = "rock-pi-e_rk3328";
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};
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};
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};
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};
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&gpio0 {
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u-boot,dm-spl;
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};
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|
@ -9,6 +9,27 @@
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chosen {
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u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
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};
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smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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manufacturer = "pine64";
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product = "rock64_rk3328";
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};
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baseboard {
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manufacturer = "pine64";
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product = "rock64_rk3328";
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};
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chassis {
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manufacturer = "pine64";
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product = "rock64_rk3328";
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};
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};
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};
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};
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&gpio0 {
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|
@ -14,6 +14,26 @@
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u-boot,spl-boot-order = &emmc, &sdmmc;
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};
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smbios {
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compatible = "u-boot,sysinfo-smbios";
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smbios {
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system {
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manufacturer = "rockchip";
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product = "sheep_rk3368";
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};
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baseboard {
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manufacturer = "rockchip";
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product = "sheep_rk3368";
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};
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chassis {
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manufacturer = "rockchip";
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product = "sheep_rk3368";
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};
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};
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};
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};
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&pinctrl {
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|
@ -32,7 +32,7 @@
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};
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board {
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compatible = "gdsys,board_gazerbeam";
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compatible = "gdsys,sysinfo-gazerbeam";
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csb = <&board_soc>;
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serdes = <&SERDES>;
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rxaui0 = <&RXAUI0_0>;
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|
@ -1103,10 +1103,6 @@
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compatible = "sandbox,sandbox_osd";
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};
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board {
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compatible = "sandbox,board_sandbox";
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};
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sandbox_tee {
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compatible = "sandbox,tee";
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};
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@ -1242,6 +1238,10 @@
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reset-names = "valid", "no_mask", "out_of_range";
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};
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sysinfo {
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compatible = "sandbox,sysinfo-sandbox";
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};
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some_regmapped-bus {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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@ -65,6 +65,21 @@ int arch_write_sci_irq_select(uint scis)
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return 0;
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}
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/**
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* chromeos_init_acpi() - Initialise basic data to boot Chrome OS
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*
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* This tells Chrome OS to boot in developer mode
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*
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* @cros: Structure to initialise
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*/
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static void chromeos_init_acpi(struct chromeos_acpi_gnvs *cros)
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{
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cros->active_main_fw = 1;
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cros->active_main_fw = 1; /* A */
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cros->switches = CHSW_DEVELOPER_SWITCH;
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cros->main_fw_type = 2; /* Developer */
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}
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int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
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{
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struct udevice *cpu;
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@ -75,11 +90,9 @@ int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
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/* TODO(sjg@chromium.org): Add the console log to gnvs->cbmc */
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#ifdef CONFIG_CHROMEOS
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/* Initialise Verified Boot data */
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chromeos_init_acpi(&gnvs->chromeos);
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gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
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#endif
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if (IS_ENABLED(CONFIG_CHROMEOS))
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chromeos_init_acpi(&gnvs->chromeos);
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/* Set unknown wake source */
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gnvs->pm1i = ~0ULL;
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@ -92,6 +105,8 @@ int acpi_create_gnvs(struct acpi_global_nvs *gnvs)
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gnvs->pcnt = ret;
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}
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gnvs->dpte = 1;
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return 0;
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}
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@ -13,6 +13,9 @@
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#include <asm/cpu_x86.h>
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#include <asm/intel_acpi.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/iomap.h>
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#include <dm/acpi.h>
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#define CSTATE_RES(address_space, width, offset, address) \
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@ -86,6 +89,86 @@ static int acpi_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
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return 0;
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}
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static void update_fixed_mtrrs(void)
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{
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native_write_msr(MTRR_FIX_64K_00000_MSR,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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native_write_msr(MTRR_FIX_16K_80000_MSR,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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native_write_msr(MTRR_FIX_4K_E0000_MSR,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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native_write_msr(MTRR_FIX_4K_E8000_MSR,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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native_write_msr(MTRR_FIX_4K_F0000_MSR,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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native_write_msr(MTRR_FIX_4K_F8000_MSR,
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
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MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
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}
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static void setup_core_msrs(void)
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{
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wrmsrl(MSR_PMG_CST_CONFIG_CONTROL,
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PKG_C_STATE_LIMIT_C2_MASK | CORE_C_STATE_LIMIT_C10_MASK |
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IO_MWAIT_REDIRECT_MASK | CST_CFG_LOCK_MASK);
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||||
/* Power Management I/O base address for I/O trapping to C-states */
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||||
wrmsrl(MSR_PMG_IO_CAPTURE_ADR, ACPI_PMIO_CST_REG |
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(PMG_IO_BASE_CST_RNG_BLK_SIZE << 16));
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||||
/* Disable C1E */
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msr_clrsetbits_64(MSR_POWER_CTL, 0x2, 0);
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/* Disable support for MONITOR and MWAIT instructions */
|
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msr_clrsetbits_64(MSR_IA32_MISC_ENABLE, MISC_ENABLE_MWAIT, 0);
|
||||
/*
|
||||
* Enable and Lock the Advanced Encryption Standard (AES-NI)
|
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* feature register
|
||||
*/
|
||||
msr_clrsetbits_64(MSR_FEATURE_CONFIG, FEATURE_CONFIG_RESERVED_MASK,
|
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FEATURE_CONFIG_LOCK);
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|
||||
update_fixed_mtrrs();
|
||||
}
|
||||
|
||||
static int soc_core_init(void)
|
||||
{
|
||||
struct udevice *pmc;
|
||||
int ret;
|
||||
|
||||
/* Clear out pending MCEs */
|
||||
cpu_mca_configure();
|
||||
|
||||
/* Set core MSRs */
|
||||
setup_core_msrs();
|
||||
/*
|
||||
* Enable ACPI PM timer emulation, which also lets microcode know
|
||||
* location of ACPI_BASE_ADDRESS. This also enables other features
|
||||
* implemented in microcode.
|
||||
*/
|
||||
ret = uclass_first_device_err(UCLASS_ACPI_PMC, &pmc);
|
||||
if (ret)
|
||||
return log_msg_ret("PMC", ret);
|
||||
enable_pm_timer_emulation(pmc);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int cpu_apl_probe(struct udevice *dev)
|
||||
{
|
||||
if (gd->flags & GD_FLG_RELOC) {
|
||||
int ret;
|
||||
|
||||
ret = soc_core_init();
|
||||
if (ret)
|
||||
return log_ret(ret);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct acpi_ops apl_cpu_acpi_ops = {
|
||||
.fill_ssdt = acpi_cpu_fill_ssdt,
|
||||
};
|
||||
@ -102,11 +185,12 @@ static const struct udevice_id cpu_x86_apl_ids[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(cpu_x86_apl_drv) = {
|
||||
.name = "cpu_x86_apl",
|
||||
U_BOOT_DRIVER(intel_apl_cpu) = {
|
||||
.name = "intel_apl_cpu",
|
||||
.id = UCLASS_CPU,
|
||||
.of_match = cpu_x86_apl_ids,
|
||||
.bind = cpu_x86_bind,
|
||||
.probe = cpu_apl_probe,
|
||||
.ops = &cpu_x86_apl_ops,
|
||||
ACPI_OPS_PTR(&apl_cpu_acpi_ops)
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
|
@ -4,8 +4,13 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <dm.h>
|
||||
#include <log.h>
|
||||
#include <asm/cpu_common.h>
|
||||
#include <asm/msr.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/iomap.h>
|
||||
#include <power/acpi_pmc.h>
|
||||
|
||||
void cpu_flush_l1d_to_l2(void)
|
||||
{
|
||||
@ -15,3 +20,23 @@ void cpu_flush_l1d_to_l2(void)
|
||||
msr.lo |= FLUSH_DL1_L2;
|
||||
msr_write(MSR_POWER_MISC, msr);
|
||||
}
|
||||
|
||||
void enable_pm_timer_emulation(const struct udevice *pmc)
|
||||
{
|
||||
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc);
|
||||
msr_t msr;
|
||||
|
||||
/*
|
||||
* The derived frequency is calculated as follows:
|
||||
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
|
||||
*
|
||||
* Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
|
||||
* used.
|
||||
*/
|
||||
msr.hi = (3579545ULL << 32) / CTC_FREQ;
|
||||
|
||||
/* Set PM1 timer IO port and enable */
|
||||
msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
|
||||
debug("PM timer %x %x\n", msr.hi, msr.lo);
|
||||
msr_write(MSR_EMULATE_PM_TIMER, msr);
|
||||
}
|
||||
|
@ -114,26 +114,6 @@ static int fast_spi_cache_bios_region(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void enable_pm_timer_emulation(struct udevice *pmc)
|
||||
{
|
||||
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc);
|
||||
msr_t msr;
|
||||
|
||||
/*
|
||||
* The derived frequency is calculated as follows:
|
||||
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
|
||||
*
|
||||
* Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
|
||||
* used.
|
||||
*/
|
||||
msr.hi = (3579545ULL << 32) / CTC_FREQ;
|
||||
|
||||
/* Set PM1 timer IO port and enable */
|
||||
msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
|
||||
debug("PM timer %x %x\n", msr.hi, msr.lo);
|
||||
msr_write(MSR_EMULATE_PM_TIMER, msr);
|
||||
}
|
||||
|
||||
static void google_chromeec_ioport_range(uint *out_basep, uint *out_sizep)
|
||||
{
|
||||
uint base;
|
||||
|
@ -116,10 +116,10 @@ static int set_power_limits(struct udevice *dev)
|
||||
|
||||
/* Program package power limits in RAPL MSR */
|
||||
msr_write(MSR_PKG_POWER_LIMIT, limit);
|
||||
log_info("RAPL PL1 %d.%dW\n", tdp / power_unit,
|
||||
100 * (tdp % power_unit) / power_unit);
|
||||
log_info("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
|
||||
100 * (pl2_val % power_unit) / power_unit);
|
||||
log_debug("RAPL PL1 %d.%dW\n", tdp / power_unit,
|
||||
100 * (tdp % power_unit) / power_unit);
|
||||
log_debug("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
|
||||
100 * (pl2_val % power_unit) / power_unit);
|
||||
|
||||
/*
|
||||
* Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
|
||||
|
@ -396,7 +396,7 @@ static const struct udevice_id apl_hostbridge_ids[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(apl_hostbridge_drv) = {
|
||||
U_BOOT_DRIVER(intel_apl_hostbridge) = {
|
||||
.name = "intel_apl_hostbridge",
|
||||
.id = UCLASS_NORTHBRIDGE,
|
||||
.of_match = apl_hostbridge_ids,
|
||||
|
@ -133,7 +133,7 @@ static const struct udevice_id apl_lpc_ids[] = {
|
||||
};
|
||||
|
||||
/* All pads are LPC already configured by the hostbridge, so no probing here */
|
||||
U_BOOT_DRIVER(apl_lpc_drv) = {
|
||||
U_BOOT_DRIVER(intel_apl_lpc) = {
|
||||
.name = "intel_apl_lpc",
|
||||
.id = UCLASS_LPC,
|
||||
.of_match = apl_lpc_ids,
|
||||
|
@ -28,8 +28,8 @@ static const struct udevice_id apl_pch_ids[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(apl_pch) = {
|
||||
.name = "apl_pch",
|
||||
U_BOOT_DRIVER(intel_apl_pch) = {
|
||||
.name = "intel_apl_pch",
|
||||
.id = UCLASS_PCH,
|
||||
.of_match = apl_pch_ids,
|
||||
.ops = &apl_pch_ops,
|
||||
|
@ -217,7 +217,7 @@ static const struct udevice_id apl_pmc_ids[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(apl_pmc) = {
|
||||
U_BOOT_DRIVER(intel_apl_pmc) = {
|
||||
.name = "intel_apl_pmc",
|
||||
.id = UCLASS_ACPI_PMC,
|
||||
.of_match = apl_pmc_ids,
|
||||
|
@ -88,8 +88,8 @@ static const struct udevice_id apl_syscon_ids[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(syscon_intel_punit) = {
|
||||
.name = "intel_punit_syscon",
|
||||
U_BOOT_DRIVER(intel_apl_punit) = {
|
||||
.name = "intel_apl_punit",
|
||||
.id = UCLASS_SYSCON,
|
||||
.of_match = apl_syscon_ids,
|
||||
.probe = apl_punit_probe,
|
||||
|
@ -122,7 +122,7 @@ static const struct udevice_id apl_ns16550_serial_ids[] = {
|
||||
{ },
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(apl_ns16550) = {
|
||||
U_BOOT_DRIVER(intel_apl_ns16550) = {
|
||||
.name = "intel_apl_ns16550",
|
||||
.id = UCLASS_SERIAL,
|
||||
.of_match = apl_ns16550_serial_ids,
|
||||
|
@ -18,6 +18,8 @@
|
||||
* src/arch/x86/lib/cpu.c
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY UCLASS_CPU
|
||||
|
||||
#include <common.h>
|
||||
#include <bootstage.h>
|
||||
#include <command.h>
|
||||
@ -200,6 +202,7 @@ __weak void board_final_cleanup(void)
|
||||
int last_stage_init(void)
|
||||
{
|
||||
struct acpi_fadt __maybe_unused *fadt;
|
||||
int ret;
|
||||
|
||||
board_final_init();
|
||||
|
||||
@ -210,7 +213,11 @@ int last_stage_init(void)
|
||||
acpi_resume(fadt);
|
||||
}
|
||||
|
||||
write_tables();
|
||||
ret = write_tables();
|
||||
if (ret) {
|
||||
log_err("Failed to write tables\n");
|
||||
return log_msg_ret("table", ret);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
|
||||
fadt = acpi_find_fadt();
|
||||
|
@ -180,16 +180,11 @@ struct idt_entry {
|
||||
u16 base_high;
|
||||
} __packed;
|
||||
|
||||
struct desc_ptr {
|
||||
unsigned short size;
|
||||
unsigned long address;
|
||||
} __packed;
|
||||
|
||||
struct idt_entry idt[256] __aligned(16);
|
||||
|
||||
struct desc_ptr idt_ptr;
|
||||
struct idt_ptr idt_ptr;
|
||||
|
||||
static inline void load_idt(const struct desc_ptr *dtr)
|
||||
static inline void load_idt(const struct idt_ptr *dtr)
|
||||
{
|
||||
asm volatile("cs lidt %0" : : "m" (*dtr));
|
||||
}
|
||||
@ -232,6 +227,11 @@ int cpu_init_interrupts(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void interrupt_read_idt(struct idt_ptr *ptr)
|
||||
{
|
||||
asm volatile("sidt %0" : : "m" (*ptr));
|
||||
}
|
||||
|
||||
void *x86_get_idt(void)
|
||||
{
|
||||
return &idt_ptr;
|
||||
|
@ -202,7 +202,6 @@ int southbridge_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx)
|
||||
(void **)&gnvs);
|
||||
if (ret)
|
||||
return log_msg_ret("bloblist", ret);
|
||||
memset(gnvs, '\0', sizeof(*gnvs));
|
||||
|
||||
ret = acpi_create_gnvs(gnvs);
|
||||
if (ret)
|
||||
|
@ -306,3 +306,22 @@ int cpu_get_cores_per_package(void)
|
||||
|
||||
return cores;
|
||||
}
|
||||
|
||||
void cpu_mca_configure(void)
|
||||
{
|
||||
msr_t msr;
|
||||
int i;
|
||||
int num_banks;
|
||||
|
||||
msr = msr_read(MSR_IA32_MCG_CAP);
|
||||
num_banks = msr.lo & 0xff;
|
||||
msr.lo = 0;
|
||||
msr.hi = 0;
|
||||
for (i = 0; i < num_banks; i++) {
|
||||
/* Clear the machine check status */
|
||||
msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
|
||||
/* Initialise machine checks */
|
||||
msr_write(MSR_IA32_MC0_CTL + i * 4,
|
||||
(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
|
||||
}
|
||||
}
|
||||
|
@ -42,7 +42,7 @@ static int locate_vbt(char **vbtp, int *sizep)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
log_info("Found a VBT of %u bytes\n", size);
|
||||
log_debug("Found a VBT of %u bytes\n", size);
|
||||
*sizep = size;
|
||||
*vbtp = vbt_data;
|
||||
|
||||
|
@ -67,7 +67,7 @@ static int snapshot_polarities(struct udevice *dev)
|
||||
reg_start = start / IRQS_PER_IPC;
|
||||
reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
|
||||
|
||||
log_info("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot);
|
||||
log_debug("ITSS IRQ Polarities snapshot %p\n", priv->irq_snapshot);
|
||||
for (i = reg_start; i < reg_end; i++) {
|
||||
uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
|
||||
|
||||
@ -89,11 +89,11 @@ static void show_polarities(struct udevice *dev, const char *msg)
|
||||
{
|
||||
int i;
|
||||
|
||||
log_info("ITSS IRQ Polarities %s:\n", msg);
|
||||
log_debug("ITSS IRQ Polarities %s:\n", msg);
|
||||
for (i = 0; i < NUM_IPC_REGS; i++) {
|
||||
uint reg = PCR_ITSS_IPC0_CONF + sizeof(u32) * i;
|
||||
|
||||
log_info("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg));
|
||||
log_debug("IPC%d: 0x%08x\n", i, pcr_read32(dev, reg));
|
||||
}
|
||||
}
|
||||
|
||||
@ -115,7 +115,7 @@ static int restore_polarities(struct udevice *dev)
|
||||
sizeof(priv->irq_snapshot));
|
||||
|
||||
show_polarities(dev, "Before");
|
||||
log_info("priv->irq_snapshot %p\n", priv->irq_snapshot);
|
||||
log_debug("priv->irq_snapshot %p\n", priv->irq_snapshot);
|
||||
|
||||
reg_start = start / IRQS_PER_IPC;
|
||||
reg_end = DIV_ROUND_UP(end, IRQS_PER_IPC);
|
||||
@ -235,7 +235,7 @@ static const struct udevice_id itss_ids[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(itss_drv) = {
|
||||
U_BOOT_DRIVER(intel_itss) = {
|
||||
.name = "intel_itss",
|
||||
.id = UCLASS_IRQ,
|
||||
.of_match = itss_ids,
|
||||
|
@ -189,7 +189,7 @@ static const struct udevice_id p2sb_ids[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(p2sb_drv) = {
|
||||
U_BOOT_DRIVER(intel_p2sb) = {
|
||||
.name = "intel_p2sb",
|
||||
.id = UCLASS_P2SB,
|
||||
.of_match = p2sb_ids,
|
||||
|
@ -16,6 +16,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Intel Bayley Bay";
|
||||
compatible = "intel,bayleybay", "intel,baytrail";
|
||||
|
@ -16,6 +16,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Advantech SOM-DB5800-SOM-6867";
|
||||
compatible = "advantech,som-db5800-som-6867", "intel,baytrail";
|
||||
|
@ -14,6 +14,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Intel Cherry Hill";
|
||||
compatible = "intel,cherryhill", "intel,braswell";
|
||||
|
@ -9,7 +9,7 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#ifdef CONFIG_CHROMEOS
|
||||
#ifdef CONFIG_CHROMEOS_VBOOT
|
||||
#include "chromeos-x86.dtsi"
|
||||
#include "flashmap-x86-ro.dtsi"
|
||||
#include "flashmap-16mb-rw.dtsi"
|
||||
@ -54,6 +54,14 @@
|
||||
recovery-gpios = <&gpio_nw (-1) GPIO_ACTIVE_LOW>;
|
||||
write-protect-gpios = <&gpio_nw GPIO_75 GPIO_ACTIVE_HIGH>;
|
||||
phase-enforce-gpios = <&gpio_n GPIO_10 GPIO_ACTIVE_HIGH>;
|
||||
smbios {
|
||||
manufacturer = "Google";
|
||||
product = "Coral";
|
||||
version = "rev2";
|
||||
serial = "123456789";
|
||||
sku = "sku3";
|
||||
family = "Google_Coral";
|
||||
};
|
||||
};
|
||||
|
||||
config {
|
||||
@ -718,8 +726,6 @@
|
||||
|
||||
fsps,ish-enable = <0>;
|
||||
fsps,enable-sata = <0>;
|
||||
fsps,pcie-root-port-en = [00 00 00 00 00 01];
|
||||
fsps,pcie-rp-hot-plug = [00 00 00 00 00 01];
|
||||
fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>;
|
||||
fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>;
|
||||
fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>;
|
||||
|
@ -11,6 +11,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Link";
|
||||
compatible = "google,link", "intel,celeron-ivybridge";
|
||||
|
@ -9,7 +9,9 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#ifdef CONFIG_CHROMEOS
|
||||
#include "smbios.dtsi"
|
||||
|
||||
#ifdef CONFIG_CHROMEOS_VBOOT
|
||||
#include "chromeos-x86.dtsi"
|
||||
#include "flashmap-x86-ro.dtsi"
|
||||
#include "flashmap-8mb-rw.dtsi"
|
||||
|
@ -6,6 +6,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Google Panther";
|
||||
compatible = "google,panther", "intel,haswell";
|
||||
|
@ -16,6 +16,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "congatec-QEVAL20-QA3-E3845";
|
||||
compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";
|
||||
|
@ -14,6 +14,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Intel Cougar Canyon 2";
|
||||
compatible = "intel,cougarcanyon2", "intel,chiefriver";
|
||||
|
@ -15,6 +15,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Intel Crown Bay";
|
||||
compatible = "intel,crownbay", "intel,queensbay";
|
||||
|
@ -13,6 +13,8 @@
|
||||
#include "rtc.dtsi"
|
||||
#include "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
config {
|
||||
silent_console = <0>;
|
||||
|
@ -12,6 +12,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Intel Edison";
|
||||
compatible = "intel,edison";
|
||||
|
@ -164,4 +164,32 @@
|
||||
};
|
||||
};
|
||||
|
||||
smbios {
|
||||
compatible = "u-boot,sysinfo-smbios";
|
||||
|
||||
/*
|
||||
* Override the default product name U-Boot reports in the
|
||||
* SMBIOS table, to be compatible with the Intel provided UEFI
|
||||
* BIOS, as Linux kernel drivers
|
||||
* (drivers/mfd/intel_quark_i2c_gpio.c and
|
||||
* drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
|
||||
* it to do different board level configuration.
|
||||
*
|
||||
* This can be "Galileo" for GEN1 Galileo board.
|
||||
*/
|
||||
smbios {
|
||||
system {
|
||||
product = "GalileoGen2";
|
||||
};
|
||||
|
||||
baseboard {
|
||||
product = "GalileoGen2";
|
||||
};
|
||||
|
||||
chassis {
|
||||
product = "GalileoGen2";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
@ -15,6 +15,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Intel Minnowboard Max";
|
||||
compatible = "intel,minnowmax", "intel,baytrail";
|
||||
|
@ -14,6 +14,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "QEMU x86 (I440FX)";
|
||||
compatible = "qemu,x86";
|
||||
|
@ -24,6 +24,8 @@
|
||||
/include/ "rtc.dtsi"
|
||||
/include/ "tsc_timer.dtsi"
|
||||
|
||||
#include "smbios.dtsi"
|
||||
|
||||
/ {
|
||||
model = "QEMU x86 (Q35)";
|
||||
compatible = "qemu,x86";
|
||||
|
32
arch/x86/dts/smbios.dtsi
Normal file
32
arch/x86/dts/smbios.dtsi
Normal file
@ -0,0 +1,32 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Default SMBIOS information. Include this in your board .dts file if you want
|
||||
* these defaults.
|
||||
*
|
||||
* Copyright 2020 Google LLC
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
|
||||
/ {
|
||||
smbios: smbios {
|
||||
compatible = "u-boot,sysinfo-smbios";
|
||||
|
||||
smbios {
|
||||
system {
|
||||
manufacturer = CONFIG_SYS_VENDOR;
|
||||
product = CONFIG_SYS_BOARD;
|
||||
};
|
||||
|
||||
baseboard {
|
||||
manufacturer = CONFIG_SYS_VENDOR;
|
||||
product = CONFIG_SYS_BOARD;
|
||||
};
|
||||
|
||||
chassis {
|
||||
manufacturer = CONFIG_SYS_VENDOR;
|
||||
/* chassis product is not set by default */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
@ -138,6 +138,10 @@
|
||||
filename = CONFIG_FSP_FILE_S;
|
||||
};
|
||||
#endif
|
||||
private_files: private-files {
|
||||
type = "files";
|
||||
pattern = "*.dat";
|
||||
};
|
||||
#ifdef CONFIG_HAVE_CMC
|
||||
intel-cmc {
|
||||
filename = CONFIG_CMC_FILE;
|
||||
|
38
arch/x86/include/asm/acpi/vbnv_layout.h
Normal file
38
arch/x86/include/asm/acpi/vbnv_layout.h
Normal file
@ -0,0 +1,38 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2020 Google LLC
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ACPI_VBNV_LAYOUT_H__
|
||||
#define __ASM_ACPI_VBNV_LAYOUT_H__
|
||||
|
||||
#define VBOOT_VBNV_BLOCK_SIZE 16 /* Size of NV storage block in bytes */
|
||||
|
||||
/* Constants for NV storage, for use with ACPI */
|
||||
#define HEADER_OFFSET 0
|
||||
#define HEADER_MASK 0xc0
|
||||
#define HEADER_SIGNATURE 0x40
|
||||
#define HEADER_FIRMWARE_SETTINGS_RESET 0x20
|
||||
#define HEADER_KERNEL_SETTINGS_RESET 0x10
|
||||
|
||||
#define BOOT_OFFSET 1
|
||||
#define BOOT_DEBUG_RESET_MODE 0x80
|
||||
#define BOOT_DISABLE_DEV_REQUEST 0x40
|
||||
#define BOOT_DISPLAY_REQUEST 0x20
|
||||
#define BOOT_TRY_B_COUNT_MASK 0x0f
|
||||
|
||||
#define RECOVERY_OFFSET 2
|
||||
#define LOCALIZATION_OFFSET 3
|
||||
|
||||
#define DEV_FLAGS_OFFSET 4
|
||||
#define DEV_BOOT_USB_MASK 0x01
|
||||
#define DEV_BOOT_SIGNED_ONLY_MASK 0x02
|
||||
#define DEV_ENABLE_UDC 0x40
|
||||
|
||||
#define MISC_FLAGS_OFFSET 8
|
||||
#define MISC_FLAGS_BATTERY_CUTOFF_MASK 0x08
|
||||
|
||||
#define KERNEL_FIELD_OFFSET 11
|
||||
#define CRC_OFFSET 15
|
||||
|
||||
#endif /* __ASM_ACPI_VBNV_LAYOUT_H__ */
|
@ -15,6 +15,20 @@
|
||||
#ifndef __ASSEMBLY__
|
||||
/* Flush L1D to L2 */
|
||||
void cpu_flush_l1d_to_l2(void);
|
||||
|
||||
/**
|
||||
* Enable emulation of the PM timer
|
||||
*
|
||||
* Some legacy OSes cannot tolerate the ACPI timer stoping during idle states,
|
||||
* and this results in higher power consumption. ACPI timer emulation allows
|
||||
* disabling of the ACPI Timer (PM1_TMR) to have no impact on the system, with
|
||||
* the exception that TMR_STS will not be set on an overflow condition. All
|
||||
* aligned 32-bit reads from the ACPI Timer port are valid and will behave as if
|
||||
* the ACPI timer remains enabled.
|
||||
*
|
||||
* @pmc: PMC device
|
||||
*/
|
||||
void enable_pm_timer_emulation(const struct udevice *pmc);
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_ARCH_CPU_H */
|
||||
|
@ -184,4 +184,13 @@ int cpu_get_max_turbo_ratio(void);
|
||||
*/
|
||||
int cpu_get_cores_per_package(void);
|
||||
|
||||
/**
|
||||
* cpu_mca_configure() - Set up machine-check exceptions ready for use
|
||||
*
|
||||
* These allow the SoC to report errors while running. See here for details:
|
||||
*
|
||||
* https://www.intel.com/content/dam/www/public/us/en/documents/white-papers/machine-check-exceptions-debug-paper.pdf
|
||||
*/
|
||||
void cpu_mca_configure(void);
|
||||
|
||||
#endif
|
||||
|
@ -9,6 +9,55 @@
|
||||
#ifndef _INTEL_GNVS_H_
|
||||
#define _INTEL_GNVS_H_
|
||||
|
||||
/*
|
||||
* The chromeos_acpi portion of ACPI GNVS is assumed to live from offset
|
||||
* 0x100 - 0x1000. When defining acpi_global_nvs, use check_member
|
||||
* to ensure that it is properly aligned:
|
||||
*
|
||||
* check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
|
||||
*/
|
||||
#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
|
||||
|
||||
enum {
|
||||
CHSW_RECOVERY_X86 = BIT(1),
|
||||
CHSW_RECOVERY_EC = BIT(2),
|
||||
CHSW_DEVELOPER_SWITCH = BIT(5),
|
||||
CHSW_FIRMWARE_WP = BIT(9),
|
||||
};
|
||||
|
||||
enum {
|
||||
FIRMWARE_TYPE_AUTO_DETECT = -1,
|
||||
FIRMWARE_TYPE_RECOVERY = 0,
|
||||
FIRMWARE_TYPE_NORMAL = 1,
|
||||
FIRMWARE_TYPE_DEVELOPER = 2,
|
||||
FIRMWARE_TYPE_NETBOOT = 3,
|
||||
FIRMWARE_TYPE_LEGACY = 4,
|
||||
};
|
||||
|
||||
struct __packed chromeos_acpi_gnvs {
|
||||
/* ChromeOS-specific */
|
||||
u32 boot_reason; /* 00 boot reason */
|
||||
u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */
|
||||
u32 activeec_fw; /* 08 (0=RO, 1=RW) */
|
||||
u16 switches; /* 0c CHSW */
|
||||
u8 vbt4[256]; /* 0e HWID */
|
||||
u8 vbt5[64]; /* 10e FWID */
|
||||
u8 vbt6[64]; /* 14e FRID - 275 */
|
||||
u32 main_fw_type; /* 18e (2 = developer mode) */
|
||||
u32 vbt8; /* 192 recovery reason */
|
||||
u32 vbt9; /* 196 fmap base address */
|
||||
u8 vdat[3072]; /* 19a VDAT space filled by verified boot */
|
||||
u32 vbt10; /* d9a smbios bios version */
|
||||
u32 mehh[8]; /* d9e management engine hash */
|
||||
u32 ramoops_base; /* dbe ramoops base address */
|
||||
u32 ramoops_len; /* dc2 ramoops length */
|
||||
u32 vpd_ro_base; /* dc6 pointer to RO_VPD */
|
||||
u32 vpd_ro_size; /* dca size of RO_VPD */
|
||||
u32 vpd_rw_base; /* dce pointer to RW_VPD */
|
||||
u32 vpd_rw_size; /* dd2 size of RW_VPD */
|
||||
u8 pad[298]; /* dd6-eff */
|
||||
};
|
||||
|
||||
struct __packed acpi_global_nvs {
|
||||
/* Miscellaneous */
|
||||
u8 pcnt; /* 0x00 - Processor Count */
|
||||
@ -31,14 +80,11 @@ struct __packed acpi_global_nvs {
|
||||
u8 unused1[0x100 - 0x3d]; /* Pad out to 256 bytes */
|
||||
#ifdef CONFIG_CHROMEOS
|
||||
/* ChromeOS-specific (0x100 - 0xfff) */
|
||||
struct chromeos_acpi chromeos;
|
||||
struct chromeos_acpi_gnvs chromeos;
|
||||
#else
|
||||
u8 unused2[0x1000 - 0x100]; /* Pad out to 4096 bytes */
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef CONFIG_CHROMEOS
|
||||
check_member(acpi_global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
|
||||
#endif
|
||||
|
||||
#endif /* _INTEL_GNVS_H_ */
|
||||
|
@ -38,6 +38,16 @@ enum x86_exception {
|
||||
EXC_VE
|
||||
};
|
||||
|
||||
/**
|
||||
* struct idt_ptr - Holds the IDT (Interrupt Descriptor Table)
|
||||
*
|
||||
* @size: Size of IDT in bytes
|
||||
*/
|
||||
struct idt_ptr {
|
||||
unsigned short size;
|
||||
unsigned long address;
|
||||
} __packed;
|
||||
|
||||
/* arch/x86/cpu/interrupts.c */
|
||||
void set_vector(u8 intnum, void *routine);
|
||||
|
||||
@ -61,4 +71,11 @@ void configure_irq_trigger(int int_num, bool is_level_triggered);
|
||||
|
||||
void *x86_get_idt(void);
|
||||
|
||||
/**
|
||||
* interrupt_read_idt() - Read the IDT
|
||||
*
|
||||
* @ptr: Place to put IDT contents
|
||||
*/
|
||||
void interrupt_read_idt(struct idt_ptr *ptr);
|
||||
|
||||
#endif
|
||||
|
@ -68,7 +68,18 @@
|
||||
#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0x000000cd
|
||||
#define MSR_PLATFORM_INFO 0x000000ce
|
||||
#define MSR_PMG_CST_CONFIG_CONTROL 0x000000e2
|
||||
#define SINGLE_PCTL (1 << 11)
|
||||
/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
|
||||
#define PKG_C_STATE_LIMIT_C2_MASK BIT(1)
|
||||
/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/
|
||||
#define CORE_C_STATE_LIMIT_C10_MASK 0x70
|
||||
/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */
|
||||
#define IO_MWAIT_REDIRECT_MASK BIT(10)
|
||||
/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */
|
||||
#define CST_CFG_LOCK_MASK BIT(15)
|
||||
#define SINGLE_PCTL BIT(11)
|
||||
|
||||
/* ACPI PMIO Offset to C-state register */
|
||||
#define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14)
|
||||
|
||||
#define MSR_MTRRcap 0x000000fe
|
||||
#define MSR_IA32_BBL_CR_CTL 0x00000119
|
||||
@ -83,6 +94,10 @@
|
||||
#define EMULATE_PM_TMR_EN (1 << 16)
|
||||
#define EMULATE_DELAY_VALUE 0x13
|
||||
|
||||
#define MSR_FEATURE_CONFIG 0x13c
|
||||
#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
|
||||
#define FEATURE_CONFIG_LOCK (1 << 0)
|
||||
|
||||
#define MSR_IA32_SYSENTER_CS 0x00000174
|
||||
#define MSR_IA32_SYSENTER_ESP 0x00000175
|
||||
#define MSR_IA32_SYSENTER_EIP 0x00000176
|
||||
@ -453,6 +468,9 @@
|
||||
#define MSR_AMD_PERF_CTL 0xc0010062
|
||||
|
||||
#define MSR_PMG_CST_CONFIG_CTL 0x000000e2
|
||||
/* CST Range (R/W) IO port block size */
|
||||
#define PMG_IO_BASE_CST_RNG_BLK_SIZE 0x5
|
||||
|
||||
#define MSR_PMG_IO_CAPTURE_ADR 0x000000e4
|
||||
#define MSR_IA32_MPERF 0x000000e7
|
||||
#define MSR_IA32_APERF 0x000000e8
|
||||
|
@ -49,8 +49,10 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad);
|
||||
* This writes x86 configuration tables, including PIRQ routing table,
|
||||
* Multi-Processor table and ACPI table. Whether a specific type of
|
||||
* configuration table is written is controlled by a Kconfig option.
|
||||
*
|
||||
* @return 0 if OK, -ENOSPC if table too large
|
||||
*/
|
||||
void write_tables(void);
|
||||
int write_tables(void);
|
||||
|
||||
/**
|
||||
* write_pirq_routing_table() - Write PIRQ routing table
|
||||
|
@ -68,6 +68,7 @@ struct nhlt_endpoint *nhlt_add_endpoint(struct nhlt *nhlt, int link_type,
|
||||
endp->device_type = device_type;
|
||||
endp->direction = dir;
|
||||
endp->virtual_bus_id = DEFAULT_VIRTUAL_BUS_ID;
|
||||
endp->num_formats = 0;
|
||||
|
||||
nhlt->num_endpoints++;
|
||||
|
||||
@ -285,25 +286,26 @@ static void nhlt_free_resources(struct nhlt *nhlt)
|
||||
}
|
||||
|
||||
struct cursor {
|
||||
u8 *start;
|
||||
u8 *buf;
|
||||
};
|
||||
|
||||
static void ser8(struct cursor *cur, uint val)
|
||||
{
|
||||
*cur->buf = val;
|
||||
cur->buf += sizeof(val);
|
||||
cur->buf += sizeof(u8);
|
||||
}
|
||||
|
||||
static void ser16(struct cursor *cur, uint val)
|
||||
{
|
||||
put_unaligned_le16(val, cur->buf);
|
||||
cur->buf += sizeof(val);
|
||||
cur->buf += sizeof(u16);
|
||||
}
|
||||
|
||||
static void ser32(struct cursor *cur, uint val)
|
||||
{
|
||||
put_unaligned_le32(val, cur->buf);
|
||||
cur->buf += sizeof(val);
|
||||
cur->buf += sizeof(u32);
|
||||
}
|
||||
|
||||
static void serblob(struct cursor *cur, void *from, size_t sz)
|
||||
@ -315,12 +317,14 @@ static void serblob(struct cursor *cur, void *from, size_t sz)
|
||||
static void serialise_specific_config(struct nhlt_specific_config *cfg,
|
||||
struct cursor *cur)
|
||||
{
|
||||
log_debug("%zx\n", cur->buf - cur->start);
|
||||
ser32(cur, cfg->size);
|
||||
serblob(cur, cfg->capabilities, cfg->size);
|
||||
}
|
||||
|
||||
static void serialise_waveform(struct nhlt_waveform *wave, struct cursor *cur)
|
||||
{
|
||||
log_debug("%zx\n", cur->buf - cur->start);
|
||||
ser16(cur, wave->tag);
|
||||
ser16(cur, wave->num_channels);
|
||||
ser32(cur, wave->samples_per_second);
|
||||
@ -338,6 +342,7 @@ static void serialise_waveform(struct nhlt_waveform *wave, struct cursor *cur)
|
||||
|
||||
static void serialise_format(struct nhlt_format *fmt, struct cursor *cur)
|
||||
{
|
||||
log_debug("%zx\n", cur->buf - cur->start);
|
||||
serialise_waveform(&fmt->waveform, cur);
|
||||
serialise_specific_config(&fmt->config, cur);
|
||||
}
|
||||
@ -346,6 +351,7 @@ static void serialise_endpoint(struct nhlt_endpoint *endp, struct cursor *cur)
|
||||
{
|
||||
int i;
|
||||
|
||||
log_debug("%zx\n", cur->buf - cur->start);
|
||||
ser32(cur, endp->length);
|
||||
ser8(cur, endp->link_type);
|
||||
ser8(cur, endp->instance_id);
|
||||
@ -384,13 +390,13 @@ int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt,
|
||||
size_t oem_table_id_len;
|
||||
int ret;
|
||||
|
||||
log_info("ACPI: * NHLT\n");
|
||||
log_debug("ACPI: * NHLT\n");
|
||||
sz = nhlt_current_size(nhlt);
|
||||
|
||||
/* Create header */
|
||||
header = (void *)ctx->current;
|
||||
memset(header, '\0', sizeof(struct acpi_table_header));
|
||||
acpi_fill_header(header, "NHLT");
|
||||
memcpy(header->signature, "NHLT", 4);
|
||||
header->length = sz;
|
||||
header->revision = acpi_get_table_revision(ACPITAB_NHLT);
|
||||
|
||||
@ -403,12 +409,15 @@ int nhlt_serialise_oem_overrides(struct acpi_ctx *ctx, struct nhlt *nhlt,
|
||||
memcpy(header->oem_table_id, oem_table_id, oem_table_id_len);
|
||||
}
|
||||
header->oem_revision = oem_revision;
|
||||
memcpy(header->aslc_id, ASLC_ID, 4);
|
||||
|
||||
cur.buf = (void *)(header + 1);
|
||||
cur.start = (void *)header;
|
||||
nhlt_serialise_endpoints(nhlt, &cur);
|
||||
|
||||
header->checksum = table_compute_checksum(header, sz);
|
||||
nhlt_free_resources(nhlt);
|
||||
assert(cur.buf - cur.start == sz);
|
||||
|
||||
ret = acpi_add_table(ctx, ctx->current);
|
||||
if (ret)
|
||||
|
@ -470,8 +470,9 @@ static void acpi_create_spcr(struct acpi_spcr *spcr)
|
||||
header->checksum = table_compute_checksum((void *)spcr, header->length);
|
||||
}
|
||||
|
||||
void acpi_create_ssdt(struct acpi_ctx *ctx, struct acpi_table_header *ssdt,
|
||||
const char *oem_table_id)
|
||||
static int acpi_create_ssdt(struct acpi_ctx *ctx,
|
||||
struct acpi_table_header *ssdt,
|
||||
const char *oem_table_id)
|
||||
{
|
||||
memset((void *)ssdt, '\0', sizeof(struct acpi_table_header));
|
||||
|
||||
@ -484,9 +485,19 @@ void acpi_create_ssdt(struct acpi_ctx *ctx, struct acpi_table_header *ssdt,
|
||||
|
||||
acpi_fill_ssdt(ctx);
|
||||
|
||||
/* (Re)calculate length and checksum. */
|
||||
/* (Re)calculate length and checksum */
|
||||
ssdt->length = ctx->current - (void *)ssdt;
|
||||
ssdt->checksum = table_compute_checksum((void *)ssdt, ssdt->length);
|
||||
log_debug("SSDT at %p, length %x\n", ssdt, ssdt->length);
|
||||
|
||||
/* Drop the table if it is empty */
|
||||
if (ssdt->length == sizeof(struct acpi_table_header)) {
|
||||
ctx->current = ssdt;
|
||||
return -ENOENT;
|
||||
}
|
||||
acpi_align(ctx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -494,7 +505,8 @@ void acpi_create_ssdt(struct acpi_ctx *ctx, struct acpi_table_header *ssdt,
|
||||
*/
|
||||
ulong write_acpi_tables(ulong start_addr)
|
||||
{
|
||||
struct acpi_ctx sctx, *ctx = &sctx;
|
||||
const int thl = sizeof(struct acpi_table_header);
|
||||
struct acpi_ctx *ctx;
|
||||
struct acpi_facs *facs;
|
||||
struct acpi_table_header *dsdt;
|
||||
struct acpi_fadt *fadt;
|
||||
@ -505,14 +517,21 @@ ulong write_acpi_tables(ulong start_addr)
|
||||
struct acpi_csrt *csrt;
|
||||
struct acpi_spcr *spcr;
|
||||
void *start;
|
||||
int aml_len;
|
||||
ulong addr;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
ctx = calloc(1, sizeof(*ctx));
|
||||
if (!ctx)
|
||||
return log_msg_ret("mem", -ENOMEM);
|
||||
gd->acpi_ctx = ctx;
|
||||
|
||||
start = map_sysmem(start_addr, 0);
|
||||
|
||||
debug("ACPI: Writing ACPI tables at %lx\n", start_addr);
|
||||
|
||||
acpi_reset_items();
|
||||
acpi_setup_base_tables(ctx, start);
|
||||
|
||||
debug("ACPI: * FACS\n");
|
||||
@ -525,21 +544,28 @@ ulong write_acpi_tables(ulong start_addr)
|
||||
dsdt = ctx->current;
|
||||
|
||||
/* Put the table header first */
|
||||
memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header));
|
||||
acpi_inc(ctx, sizeof(struct acpi_table_header));
|
||||
memcpy(dsdt, &AmlCode, thl);
|
||||
acpi_inc(ctx, thl);
|
||||
log_debug("DSDT starts at %p, hdr ends at %p\n", dsdt, ctx->current);
|
||||
|
||||
/* If the table is not empty, allow devices to inject things */
|
||||
if (dsdt->length >= sizeof(struct acpi_table_header))
|
||||
aml_len = dsdt->length - thl;
|
||||
if (aml_len) {
|
||||
void *base = ctx->current;
|
||||
|
||||
acpi_inject_dsdt(ctx);
|
||||
log_debug("Added %x bytes from inject_dsdt, now at %p\n",
|
||||
ctx->current - base, ctx->current);
|
||||
log_debug("Copy AML code size %x to %p\n", aml_len,
|
||||
ctx->current);
|
||||
memcpy(ctx->current, AmlCode + thl, aml_len);
|
||||
acpi_inc(ctx, aml_len);
|
||||
}
|
||||
|
||||
/* Copy in the AML code itself if any (after the header) */
|
||||
memcpy(ctx->current,
|
||||
(char *)&AmlCode + sizeof(struct acpi_table_header),
|
||||
dsdt->length - sizeof(struct acpi_table_header));
|
||||
|
||||
acpi_inc(ctx, dsdt->length - sizeof(struct acpi_table_header));
|
||||
dsdt->length = ctx->current - (void *)dsdt;
|
||||
acpi_align(ctx);
|
||||
log_debug("Updated DSDT length to %x, total %x\n", dsdt->length,
|
||||
ctx->current - (void *)dsdt);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_ACPI_GNVS_EXTERNAL)) {
|
||||
/* Pack GNVS into the ACPI table area */
|
||||
@ -591,11 +617,8 @@ ulong write_acpi_tables(ulong start_addr)
|
||||
|
||||
debug("ACPI: * SSDT\n");
|
||||
ssdt = (struct acpi_table_header *)ctx->current;
|
||||
acpi_create_ssdt(ctx, ssdt, OEM_TABLE_ID);
|
||||
if (ssdt->length > sizeof(struct acpi_table_header)) {
|
||||
acpi_inc_align(ctx, ssdt->length);
|
||||
if (!acpi_create_ssdt(ctx, ssdt, OEM_TABLE_ID))
|
||||
acpi_add_table(ctx, ssdt);
|
||||
}
|
||||
|
||||
debug("ACPI: * MCFG\n");
|
||||
mcfg = ctx->current;
|
||||
@ -623,14 +646,17 @@ ulong write_acpi_tables(ulong start_addr)
|
||||
acpi_inc_align(ctx, madt->header.length);
|
||||
acpi_add_table(ctx, madt);
|
||||
|
||||
debug("ACPI: * TCPA\n");
|
||||
tcpa = (struct acpi_tcpa *)ctx->current;
|
||||
ret = acpi_create_tcpa(tcpa);
|
||||
if (ret) {
|
||||
log_warning("Failed to create TCPA table (err=%d)\n", ret);
|
||||
} else {
|
||||
acpi_inc_align(ctx, tcpa->header.length);
|
||||
acpi_add_table(ctx, tcpa);
|
||||
if (IS_ENABLED(CONFIG_TPM_V1)) {
|
||||
debug("ACPI: * TCPA\n");
|
||||
tcpa = (struct acpi_tcpa *)ctx->current;
|
||||
ret = acpi_create_tcpa(tcpa);
|
||||
if (ret) {
|
||||
log_warning("Failed to create TCPA table (err=%d)\n",
|
||||
ret);
|
||||
} else {
|
||||
acpi_inc_align(ctx, tcpa->header.length);
|
||||
acpi_add_table(ctx, tcpa);
|
||||
}
|
||||
}
|
||||
|
||||
debug("ACPI: * CSRT\n");
|
||||
@ -741,7 +767,7 @@ int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev,
|
||||
* 32-bits each. This is only for debugging so it is not a big deal.
|
||||
*/
|
||||
addr = dm_pci_read_bar32(dev, 0);
|
||||
printf("UART addr %lx\n", (ulong)addr);
|
||||
log_debug("UART addr %lx\n", (ulong)addr);
|
||||
|
||||
memset(&address, '\0', sizeof(address));
|
||||
address.space_id = ACPI_ADDRESS_SPACE_MEMORY;
|
||||
|
@ -41,8 +41,10 @@ int fsp_scan_for_ram_size(void)
|
||||
|
||||
int dram_init_banksize(void)
|
||||
{
|
||||
efi_guid_t fsp = FSP_HOB_RESOURCE_OWNER_FSP_GUID;
|
||||
const struct hob_header *hdr;
|
||||
struct hob_res_desc *res_desc;
|
||||
phys_addr_t mtrr_top;
|
||||
phys_addr_t low_end;
|
||||
uint bank;
|
||||
|
||||
@ -54,35 +56,42 @@ int dram_init_banksize(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
low_end = 0;
|
||||
low_end = 0; /* top of low memory usable by U-Boot */
|
||||
mtrr_top = 0; /* top of low memory (even if reserved) */
|
||||
for (bank = 1, hdr = gd->arch.hob_list;
|
||||
bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr);
|
||||
hdr = get_next_hob(hdr)) {
|
||||
if (hdr->type != HOB_TYPE_RES_DESC)
|
||||
continue;
|
||||
res_desc = (struct hob_res_desc *)hdr;
|
||||
if (!guidcmp(&res_desc->owner, &fsp))
|
||||
low_end = res_desc->phys_start;
|
||||
if (res_desc->type != RES_SYS_MEM &&
|
||||
res_desc->type != RES_MEM_RESERVED)
|
||||
continue;
|
||||
if (res_desc->phys_start < (1ULL << 32)) {
|
||||
low_end = max(low_end,
|
||||
res_desc->phys_start + res_desc->len);
|
||||
continue;
|
||||
mtrr_top = max(mtrr_top,
|
||||
res_desc->phys_start + res_desc->len);
|
||||
} else {
|
||||
gd->bd->bi_dram[bank].start = res_desc->phys_start;
|
||||
gd->bd->bi_dram[bank].size = res_desc->len;
|
||||
mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
|
||||
res_desc->len);
|
||||
log_debug("ram %llx %llx\n",
|
||||
gd->bd->bi_dram[bank].start,
|
||||
gd->bd->bi_dram[bank].size);
|
||||
}
|
||||
|
||||
gd->bd->bi_dram[bank].start = res_desc->phys_start;
|
||||
gd->bd->bi_dram[bank].size = res_desc->len;
|
||||
mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start,
|
||||
res_desc->len);
|
||||
log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start,
|
||||
gd->bd->bi_dram[bank].size);
|
||||
}
|
||||
|
||||
/* Add the memory below 4GB */
|
||||
gd->bd->bi_dram[0].start = 0;
|
||||
gd->bd->bi_dram[0].size = low_end;
|
||||
|
||||
mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end);
|
||||
/*
|
||||
* Set up an MTRR to the top of low, reserved memory. This is necessary
|
||||
* for graphics to run at full speed in U-Boot.
|
||||
*/
|
||||
mtrr_add_request(MTRR_TYPE_WRBACK, 0, mtrr_top);
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -156,7 +165,7 @@ unsigned int install_e820_map(unsigned int max_entries,
|
||||
#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB)
|
||||
int handoff_arch_save(struct spl_handoff *ho)
|
||||
{
|
||||
ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list);
|
||||
ho->arch.usable_ram_top = gd->bd->bi_dram[0].size;
|
||||
ho->arch.hob_list = gd->arch.hob_list;
|
||||
|
||||
return 0;
|
||||
|
@ -139,7 +139,7 @@ static int fsp_video_acpi_write_tables(const struct udevice *dev,
|
||||
struct igd_opregion *opregion;
|
||||
int ret;
|
||||
|
||||
printf("ACPI: * IGD OpRegion\n");
|
||||
log_debug("ACPI: * IGD OpRegion\n");
|
||||
opregion = (struct igd_opregion *)ctx->current;
|
||||
|
||||
ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion);
|
||||
|
@ -4,6 +4,8 @@
|
||||
* Written by Simon Glass <sjg@chromium.org>
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_ARCH
|
||||
|
||||
#include <common.h>
|
||||
#include <handoff.h>
|
||||
#include <init.h>
|
||||
@ -35,7 +37,7 @@ int dram_init(void)
|
||||
ret = fsp_memory_init(s3wake,
|
||||
IS_ENABLED(CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH));
|
||||
if (ret) {
|
||||
debug("Memory init failed (err=%x)\n", ret);
|
||||
log_debug("Memory init failed (err=%x)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -60,7 +62,7 @@ int dram_init(void)
|
||||
struct spl_handoff *ho = gd->spl_handoff;
|
||||
|
||||
if (!ho) {
|
||||
debug("No SPL handoff found\n");
|
||||
log_debug("No SPL handoff found\n");
|
||||
return -ESTRPIPE;
|
||||
}
|
||||
gd->ram_size = ho->ram_size;
|
||||
@ -82,6 +84,8 @@ ulong board_get_usable_ram_top(ulong total_size)
|
||||
#if CONFIG_IS_ENABLED(HANDOFF)
|
||||
struct spl_handoff *ho = gd->spl_handoff;
|
||||
|
||||
log_debug("usable_ram_top = %lx\n", ho->arch.usable_ram_top);
|
||||
|
||||
return ho->arch.usable_ram_top;
|
||||
#endif
|
||||
|
||||
|
@ -131,8 +131,11 @@ void do_irq(int hw_irq)
|
||||
int do_irqinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
{
|
||||
#if !CONFIG_IS_ENABLED(X86_64)
|
||||
struct idt_ptr ptr;
|
||||
int irq;
|
||||
|
||||
interrupt_read_idt(&ptr);
|
||||
printf("IDT at %lx, size %x\n", ptr.address, ptr.size);
|
||||
printf("Spurious IRQ: %u, last unknown IRQ: %d\n",
|
||||
spurious_irq_cnt, spurious_irq);
|
||||
|
||||
|
@ -4,6 +4,7 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <bloblist.h>
|
||||
#include <log.h>
|
||||
#include <malloc.h>
|
||||
#include <smbios.h>
|
||||
@ -13,6 +14,8 @@
|
||||
#include <asm/tables.h>
|
||||
#include <asm/coreboot_tables.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/**
|
||||
* Function prototype to write a specific configuration table
|
||||
*
|
||||
@ -26,10 +29,16 @@ typedef ulong (*table_write)(ulong addr);
|
||||
*
|
||||
* @name: Name of table (for debugging)
|
||||
* @write: Function to call to write this table
|
||||
* @tag: Bloblist tag if using CONFIG_BLOBLIST_TABLES
|
||||
* @size: Maximum table size
|
||||
* @align: Table alignment in bytes
|
||||
*/
|
||||
struct table_info {
|
||||
const char *name;
|
||||
table_write write;
|
||||
enum bloblist_tag_t tag;
|
||||
int size;
|
||||
int align;
|
||||
};
|
||||
|
||||
static struct table_info table_list[] = {
|
||||
@ -43,10 +52,10 @@ static struct table_info table_list[] = {
|
||||
{ "mp", write_mp_table, },
|
||||
#endif
|
||||
#ifdef CONFIG_GENERATE_ACPI_TABLE
|
||||
{ "acpi", write_acpi_tables, },
|
||||
{ "acpi", write_acpi_tables, BLOBLISTT_ACPI_TABLES, 0x10000, 0x1000},
|
||||
#endif
|
||||
#ifdef CONFIG_GENERATE_SMBIOS_TABLE
|
||||
{ "smbios", write_smbios_table, },
|
||||
{ "smbios", write_smbios_table, BLOBLISTT_SMBIOS_TABLES, 0x1000, 0x100},
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -64,45 +73,82 @@ void table_fill_string(char *dest, const char *src, size_t n, char pad)
|
||||
dest[i] = pad;
|
||||
}
|
||||
|
||||
void write_tables(void)
|
||||
int write_tables(void)
|
||||
{
|
||||
u32 rom_table_start = ROM_TABLE_ADDR;
|
||||
u32 rom_table_start;
|
||||
u32 rom_table_end;
|
||||
#ifdef CONFIG_SEABIOS
|
||||
u32 high_table, table_size;
|
||||
struct memory_area cfg_tables[ARRAY_SIZE(table_list) + 1];
|
||||
#endif
|
||||
int i;
|
||||
|
||||
rom_table_start = ROM_TABLE_ADDR;
|
||||
|
||||
debug("Writing tables to %x:\n", rom_table_start);
|
||||
for (i = 0; i < ARRAY_SIZE(table_list); i++) {
|
||||
const struct table_info *table = &table_list[i];
|
||||
int size = table->size ? : CONFIG_ROM_TABLE_SIZE;
|
||||
|
||||
if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) {
|
||||
rom_table_start = (ulong)bloblist_add(table->tag, size,
|
||||
table->align);
|
||||
if (!rom_table_start)
|
||||
return log_msg_ret("bloblist", -ENOBUFS);
|
||||
}
|
||||
rom_table_end = table->write(rom_table_start);
|
||||
rom_table_end = ALIGN(rom_table_end, ROM_TABLE_ALIGN);
|
||||
|
||||
#ifdef CONFIG_SEABIOS
|
||||
table_size = rom_table_end - rom_table_start;
|
||||
high_table = (u32)high_table_malloc(table_size);
|
||||
if (high_table) {
|
||||
table->write(high_table);
|
||||
if (IS_ENABLED(CONFIG_SEABIOS)) {
|
||||
table_size = rom_table_end - rom_table_start;
|
||||
high_table = (u32)(ulong)high_table_malloc(table_size);
|
||||
if (high_table) {
|
||||
table->write(high_table);
|
||||
|
||||
cfg_tables[i].start = high_table;
|
||||
cfg_tables[i].size = table_size;
|
||||
} else {
|
||||
printf("%d: no memory for configuration tables\n", i);
|
||||
cfg_tables[i].start = high_table;
|
||||
cfg_tables[i].size = table_size;
|
||||
} else {
|
||||
printf("%d: no memory for configuration tables\n",
|
||||
i);
|
||||
return -ENOSPC;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
debug("- wrote '%s' to %x, end %x\n", table->name,
|
||||
rom_table_start, rom_table_end);
|
||||
if (rom_table_end - rom_table_start > size) {
|
||||
log_err("Out of space for configuration tables: need %x, have %x\n",
|
||||
rom_table_end - rom_table_start, size);
|
||||
return log_msg_ret("bloblist", -ENOSPC);
|
||||
}
|
||||
rom_table_start = rom_table_end;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SEABIOS
|
||||
/* make sure the last item is zero */
|
||||
cfg_tables[i].size = 0;
|
||||
write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
|
||||
#endif
|
||||
if (IS_ENABLED(CONFIG_SEABIOS)) {
|
||||
/* make sure the last item is zero */
|
||||
cfg_tables[i].size = 0;
|
||||
write_coreboot_table(CB_TABLE_ADDR, cfg_tables);
|
||||
}
|
||||
|
||||
if (IS_ENABLED(CONFIG_BLOBLIST_TABLES)) {
|
||||
void *ptr = (void *)CONFIG_ROM_TABLE_ADDR;
|
||||
|
||||
/* Write an RSDP pointing to the tables */
|
||||
if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE)) {
|
||||
struct acpi_ctx *ctx = gd_acpi_ctx();
|
||||
|
||||
acpi_write_rsdp(ptr, ctx->rsdt, ctx->xsdt);
|
||||
ptr += ALIGN(sizeof(struct acpi_rsdp), 16);
|
||||
}
|
||||
if (IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE)) {
|
||||
void *smbios;
|
||||
|
||||
smbios = bloblist_find(BLOBLISTT_SMBIOS_TABLES, 0);
|
||||
if (!smbios)
|
||||
return log_msg_ret("smbios", -ENOENT);
|
||||
memcpy(ptr, smbios, sizeof(struct smbios_entry));
|
||||
}
|
||||
}
|
||||
|
||||
debug("- done writing tables\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -75,7 +75,7 @@ void board_init_f_r(void)
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
return IS_ENABLED(CONFIG_CHROMEOS) ? BOOT_DEVICE_CROS_VBOOT :
|
||||
return IS_ENABLED(CONFIG_CHROMEOS_VBOOT) ? BOOT_DEVICE_CROS_VBOOT :
|
||||
BOOT_DEVICE_SPI_MMAP;
|
||||
}
|
||||
|
||||
|
@ -12,10 +12,13 @@
|
||||
* linux/Documentation/i386/boot.txt
|
||||
*/
|
||||
|
||||
#define LOG_CATEGORY LOGC_BOOT
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <env.h>
|
||||
#include <irq_func.h>
|
||||
#include <log.h>
|
||||
#include <malloc.h>
|
||||
#include <acpi/acpi_table.h>
|
||||
#include <asm/io.h>
|
||||
@ -28,6 +31,7 @@
|
||||
#include <asm/arch/timestamp.h>
|
||||
#endif
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
/*
|
||||
@ -172,11 +176,19 @@ static const char *get_kernel_version(struct boot_params *params,
|
||||
{
|
||||
struct setup_header *hdr = ¶ms->hdr;
|
||||
int bootproto;
|
||||
const char *s, *end;
|
||||
|
||||
bootproto = get_boot_protocol(hdr, false);
|
||||
if (bootproto < 0x0200 || hdr->setup_sects < 15)
|
||||
return NULL;
|
||||
|
||||
/* sanity-check the kernel version in case it is missing */
|
||||
for (s = kernel_base + hdr->kernel_version + 0x200, end = s + 0x100; *s;
|
||||
s++) {
|
||||
if (!isprint(*s))
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return kernel_base + hdr->kernel_version + 0x200;
|
||||
}
|
||||
|
||||
@ -200,13 +212,13 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
|
||||
|
||||
/* determine size of setup */
|
||||
if (0 == hdr->setup_sects) {
|
||||
printf("Setup Sectors = 0 (defaulting to 4)\n");
|
||||
log_warning("Setup Sectors = 0 (defaulting to 4)\n");
|
||||
setup_size = 5 * 512;
|
||||
} else {
|
||||
setup_size = (hdr->setup_sects + 1) * 512;
|
||||
}
|
||||
|
||||
printf("Setup Size = 0x%8.8lx\n", (ulong)setup_size);
|
||||
log_debug("Setup Size = 0x%8.8lx\n", (ulong)setup_size);
|
||||
|
||||
if (setup_size > SETUP_MAX_SIZE)
|
||||
printf("Error: Setup is too large (%d bytes)\n", setup_size);
|
||||
@ -214,8 +226,8 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
|
||||
/* determine boot protocol version */
|
||||
bootproto = get_boot_protocol(hdr, true);
|
||||
|
||||
printf("Using boot protocol version %x.%02x\n",
|
||||
(bootproto & 0xff00) >> 8, bootproto & 0xff);
|
||||
log_debug("Using boot protocol version %x.%02x\n",
|
||||
(bootproto & 0xff00) >> 8, bootproto & 0xff);
|
||||
|
||||
version = get_kernel_version(params, image);
|
||||
if (version)
|
||||
@ -292,6 +304,7 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
|
||||
struct setup_header *hdr = &setup_base->hdr;
|
||||
int bootproto = get_boot_protocol(hdr, false);
|
||||
|
||||
log_debug("Setup E820 entries\n");
|
||||
setup_base->e820_entries = install_e820_map(
|
||||
ARRAY_SIZE(setup_base->e820_map), setup_base->e820_map);
|
||||
|
||||
@ -317,6 +330,7 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
|
||||
}
|
||||
|
||||
if (cmd_line) {
|
||||
log_debug("Setup cmdline\n");
|
||||
if (bootproto >= 0x0202) {
|
||||
hdr->cmd_line_ptr = (uintptr_t)cmd_line;
|
||||
} else if (bootproto >= 0x0200) {
|
||||
@ -340,6 +354,7 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
|
||||
if (IS_ENABLED(CONFIG_GENERATE_ACPI_TABLE))
|
||||
setup_base->acpi_rsdp_addr = acpi_get_rsdp_addr();
|
||||
|
||||
log_debug("Setup devicetree\n");
|
||||
setup_device_tree(hdr, (const void *)env_get_hex("fdtaddr", 0));
|
||||
setup_video(&setup_base->screen_info);
|
||||
|
||||
@ -405,7 +420,8 @@ static int do_zboot_load(struct cmd_tbl *cmdtp, int flag, int argc,
|
||||
struct boot_params *from = (struct boot_params *)state.base_ptr;
|
||||
|
||||
base_ptr = (struct boot_params *)DEFAULT_SETUP_BASE;
|
||||
printf("Building boot_params at 0x%8.8lx\n", (ulong)base_ptr);
|
||||
log_debug("Building boot_params at 0x%8.8lx\n",
|
||||
(ulong)base_ptr);
|
||||
memset(base_ptr, '\0', sizeof(*base_ptr));
|
||||
base_ptr->hdr = from->hdr;
|
||||
} else {
|
||||
|
@ -4,7 +4,9 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/sysinfo.h>
|
||||
#include <init.h>
|
||||
#include <smbios.h>
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
@ -16,3 +18,46 @@ int board_early_init_r(void)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMBIOS_PARSER
|
||||
int show_board_info(void)
|
||||
{
|
||||
const struct smbios_entry *smbios = smbios_entry(lib_sysinfo.smbios_start, lib_sysinfo.smbios_size);
|
||||
|
||||
if (!smbios)
|
||||
goto fallback;
|
||||
|
||||
const struct smbios_header *bios = smbios_header(smbios, SMBIOS_BIOS_INFORMATION);
|
||||
const struct smbios_header *system = smbios_header(smbios, SMBIOS_SYSTEM_INFORMATION);
|
||||
const struct smbios_type0 *t0 = (struct smbios_type0 *)bios;
|
||||
const struct smbios_type1 *t1 = (struct smbios_type1 *)system;
|
||||
|
||||
if (!t0 || !t1)
|
||||
goto fallback;
|
||||
|
||||
const char *bios_ver = smbios_string(bios, t0->bios_ver);
|
||||
const char *model = smbios_string(system, t1->product_name);
|
||||
const char *manufacturer = smbios_string(system, t1->manufacturer);
|
||||
|
||||
if (!model || !manufacturer || !bios_ver)
|
||||
goto fallback;
|
||||
|
||||
printf("Vendor: %s\n", manufacturer);
|
||||
printf("Model: %s\n", model);
|
||||
printf("BIOS Version: %s\n", bios_ver);
|
||||
|
||||
return 0;
|
||||
|
||||
fallback:
|
||||
#ifdef CONFIG_OF_CONTROL
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
model = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
|
||||
|
||||
if (model)
|
||||
printf("Model: %s\n", model);
|
||||
#endif
|
||||
|
||||
return checkboard();
|
||||
}
|
||||
#endif
|
||||
|
@ -16,7 +16,7 @@
|
||||
#include <dm.h>
|
||||
#include <misc.h>
|
||||
#include <regmap.h>
|
||||
#include <board.h>
|
||||
#include <sysinfo.h>
|
||||
|
||||
#include "../../../drivers/misc/gdsys_soc.h"
|
||||
#include "../../../drivers/misc/gdsys_ioep.h"
|
||||
@ -506,11 +506,11 @@ int do_ioloop(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
int do_iodev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
{
|
||||
struct udevice *ioep = NULL;
|
||||
struct udevice *board;
|
||||
struct udevice *sysinfo;
|
||||
char name[8];
|
||||
int ret;
|
||||
|
||||
if (board_get(&board))
|
||||
if (sysinfo_get(&sysinfo))
|
||||
return CMD_RET_FAILURE;
|
||||
|
||||
if (argc > 1) {
|
||||
@ -518,7 +518,8 @@ int do_iodev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
|
||||
snprintf(name, sizeof(name), "ioep%d", i);
|
||||
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo, name,
|
||||
&ioep);
|
||||
|
||||
if (ret || !ioep) {
|
||||
printf("Invalid IOEP %d\n", i);
|
||||
@ -532,7 +533,8 @@ int do_iodev(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
while (1) {
|
||||
snprintf(name, sizeof(name), "ioep%d", i);
|
||||
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &ioep);
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo,
|
||||
name, &ioep);
|
||||
|
||||
if (ret || !ioep)
|
||||
break;
|
||||
|
@ -6,7 +6,6 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <board.h>
|
||||
#include <command.h>
|
||||
#include <dm.h>
|
||||
#include <env.h>
|
||||
@ -15,11 +14,12 @@
|
||||
#include <init.h>
|
||||
#include <miiphy.h>
|
||||
#include <misc.h>
|
||||
#include <sysinfo.h>
|
||||
#include <tpm-v1.h>
|
||||
#include <video_osd.h>
|
||||
|
||||
#include "../common/ihs_mdio.h"
|
||||
#include "../../../drivers/board/gazerbeam.h"
|
||||
#include "../../../drivers/sysinfo/gazerbeam.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
@ -43,22 +43,22 @@ static int get_tpm(struct udevice **devp)
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
struct udevice *board;
|
||||
struct udevice *sysinfo;
|
||||
struct udevice *serdes;
|
||||
int mc = 0;
|
||||
int con = 0;
|
||||
|
||||
if (board_get(&board))
|
||||
puts("Could not find board information device.\n");
|
||||
if (sysinfo_get(&sysinfo))
|
||||
puts("Could not find sysinfo information device.\n");
|
||||
|
||||
/* Initialize serdes */
|
||||
uclass_get_device_by_phandle(UCLASS_MISC, board, "serdes", &serdes);
|
||||
uclass_get_device_by_phandle(UCLASS_MISC, sysinfo, "serdes", &serdes);
|
||||
|
||||
if (board_detect(board))
|
||||
if (sysinfo_detect(sysinfo))
|
||||
puts("Device information detection failed.\n");
|
||||
|
||||
board_get_int(board, BOARD_MULTICHANNEL, &mc);
|
||||
board_get_int(board, BOARD_VARIANT, &con);
|
||||
sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc);
|
||||
sysinfo_get_int(sysinfo, BOARD_VARIANT, &con);
|
||||
|
||||
if (mc == 2 || mc == 1)
|
||||
dev_disable_by_path("/immr@e0000000/i2c@3100/pca9698@22");
|
||||
@ -84,18 +84,18 @@ int board_early_init_r(void)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
int checksysinfo(void)
|
||||
{
|
||||
struct udevice *board;
|
||||
struct udevice *sysinfo;
|
||||
char *s = env_get("serial#");
|
||||
int mc = 0;
|
||||
int con = 0;
|
||||
|
||||
if (board_get(&board))
|
||||
puts("Could not find board information device.\n");
|
||||
if (sysinfo_get(&sysinfo))
|
||||
puts("Could not find sysinfo information device.\n");
|
||||
|
||||
board_get_int(board, BOARD_MULTICHANNEL, &mc);
|
||||
board_get_int(board, BOARD_VARIANT, &con);
|
||||
sysinfo_get_int(sysinfo, BOARD_MULTICHANNEL, &mc);
|
||||
sysinfo_get_int(sysinfo, BOARD_VARIANT, &con);
|
||||
|
||||
puts("Board: Gazerbeam ");
|
||||
printf("%s ", mc == 4 ? "MC4" : mc == 2 ? "MC2" : "SC");
|
||||
@ -123,20 +123,22 @@ int last_stage_init(void)
|
||||
{
|
||||
int fpga_hw_rev = 0;
|
||||
int i;
|
||||
struct udevice *board;
|
||||
struct udevice *sysinfo;
|
||||
struct udevice *osd;
|
||||
struct video_osd_info osd_info;
|
||||
struct udevice *tpm;
|
||||
int ret;
|
||||
|
||||
if (board_get(&board))
|
||||
puts("Could not find board information device.\n");
|
||||
if (sysinfo_get(&sysinfo))
|
||||
puts("Could not find sysinfo information device.\n");
|
||||
|
||||
if (board) {
|
||||
int res = board_get_int(board, BOARD_HWVERSION, &fpga_hw_rev);
|
||||
if (sysinfo) {
|
||||
int res = sysinfo_get_int(sysinfo, BOARD_HWVERSION,
|
||||
&fpga_hw_rev);
|
||||
|
||||
if (res)
|
||||
printf("Could not determind FPGA HW revision (res = %d)\n", res);
|
||||
printf("Could not determind FPGA HW revision (res = %d)\n",
|
||||
res);
|
||||
}
|
||||
|
||||
env_set_ulong("fpga_hw_rev", fpga_hw_rev);
|
||||
@ -154,7 +156,8 @@ int last_stage_init(void)
|
||||
|
||||
snprintf(name, sizeof(name), "rxaui%d", i);
|
||||
/* Disable RXAUI polarity inversion */
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, board, name, &rxaui);
|
||||
ret = uclass_get_device_by_phandle(UCLASS_MISC, sysinfo,
|
||||
name, &rxaui);
|
||||
if (!ret)
|
||||
misc_set_enabled(rxaui, false);
|
||||
}
|
||||
|
@ -150,7 +150,7 @@ static const struct udevice_id coral_ids[] = {
|
||||
|
||||
U_BOOT_DRIVER(coral_drv) = {
|
||||
.name = "coral",
|
||||
.id = UCLASS_BOARD,
|
||||
.id = UCLASS_SYSINFO,
|
||||
.of_match = coral_ids,
|
||||
ACPI_OPS_PTR(&coral_acpi_ops)
|
||||
};
|
||||
|
@ -22,15 +22,4 @@ config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
select BOARD_ROMSIZE_KB_1024
|
||||
select SPI_FLASH_WINBOND
|
||||
|
||||
config SMBIOS_PRODUCT_NAME
|
||||
default "GalileoGen2"
|
||||
help
|
||||
Override the default product name U-Boot reports in the SMBIOS
|
||||
table, to be compatible with the Intel provided UEFI BIOS, as
|
||||
Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
|
||||
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
|
||||
it to do different board level configuration.
|
||||
|
||||
This can be "Galileo" for GEN1 Galileo board.
|
||||
|
||||
endif
|
||||
|
@ -343,6 +343,23 @@ config ARCH_FIXUP_FDT_MEMORY
|
||||
used for booting OS with different memory setup where the part of
|
||||
the memory location should be used for different purpose.
|
||||
|
||||
config CHROMEOS
|
||||
bool "Support booting Chrome OS"
|
||||
help
|
||||
Chrome OS requires U-Boot to set up a table indicating the boot mode
|
||||
(e.g. Developer mode) and a few other things. Enable this if you are
|
||||
booting on a Chromebook to avoid getting an error about an invalid
|
||||
firmware ID.
|
||||
|
||||
config CHROMEOS_VBOOT
|
||||
bool "Support Chrome OS verified boot"
|
||||
help
|
||||
This is intended to enable the full Chrome OS verified boot support
|
||||
in U-Boot. It is not actually implemented in the U-Boot source code
|
||||
at present, so this option is always set to 'n'. It allows
|
||||
distinguishing between booting Chrome OS in a basic way (developer
|
||||
mode) and a full boot.
|
||||
|
||||
endmenu # Boot images
|
||||
|
||||
menu "Boot timing"
|
||||
|
@ -26,6 +26,7 @@ static const char *const log_cat_name[] = {
|
||||
"bloblist",
|
||||
"devres",
|
||||
"acpi",
|
||||
"boot",
|
||||
};
|
||||
|
||||
_Static_assert(ARRAY_SIZE(log_cat_name) == LOGC_COUNT - LOGC_NONE,
|
||||
|
@ -6,13 +6,13 @@
|
||||
|
||||
#include <common.h>
|
||||
#include <errno.h>
|
||||
#include <board.h>
|
||||
#include <fpga.h>
|
||||
#include <gzip.h>
|
||||
#include <image.h>
|
||||
#include <log.h>
|
||||
#include <malloc.h>
|
||||
#include <spl.h>
|
||||
#include <sysinfo.h>
|
||||
#include <asm/cache.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
@ -74,7 +74,7 @@ static int spl_fit_get_image_name(const void *fit, int images,
|
||||
const char *type, int index,
|
||||
const char **outname)
|
||||
{
|
||||
struct udevice *board;
|
||||
struct udevice *sysinfo;
|
||||
const char *name, *str;
|
||||
__maybe_unused int node;
|
||||
int conf_node;
|
||||
@ -110,19 +110,20 @@ static int spl_fit_get_image_name(const void *fit, int images,
|
||||
}
|
||||
}
|
||||
|
||||
if (!found && !board_get(&board)) {
|
||||
if (!found && CONFIG_IS_ENABLED(SYSINFO) && !sysinfo_get(&sysinfo)) {
|
||||
int rc;
|
||||
/*
|
||||
* no string in the property for this index. Check if the board
|
||||
* level code can supply one.
|
||||
* no string in the property for this index. Check if the
|
||||
* sysinfo-level code can supply one.
|
||||
*/
|
||||
rc = board_get_fit_loadable(board, index - i - 1, type, &str);
|
||||
rc = sysinfo_get_fit_loadable(sysinfo, index - i - 1, type,
|
||||
&str);
|
||||
if (rc && rc != -ENOENT)
|
||||
return rc;
|
||||
|
||||
if (!rc) {
|
||||
/*
|
||||
* The board provided a name for a loadable.
|
||||
* The sysinfo provided a name for a loadable.
|
||||
* Try to match it against the description properties
|
||||
* first. If no matching node is found, use it as a
|
||||
* node name.
|
||||
|
@ -21,6 +21,7 @@ CONFIG_INTEL_CAR_CQOS=y
|
||||
CONFIG_X86_OFFSET_U_BOOT=0xffd00000
|
||||
CONFIG_X86_OFFSET_SPL=0xffe80000
|
||||
CONFIG_INTEL_GENERIC_WIFI=y
|
||||
CONFIG_CHROMEOS=y
|
||||
CONFIG_BOOTSTAGE=y
|
||||
CONFIG_SPL_BOOTSTAGE=y
|
||||
CONFIG_TPL_BOOTSTAGE=y
|
||||
@ -28,8 +29,10 @@ CONFIG_BOOTSTAGE_REPORT=y
|
||||
CONFIG_SPL_BOOTSTAGE_RECORD_COUNT=10
|
||||
CONFIG_BOOTSTAGE_STASH=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
CONFIG_BOOTARGS="console=ttyS2,115200n8 cros_legacy loglevel=9 init=/sbin/init oops=panic panic=-1 root=PARTUUID=35c775e7-3735-d745-93e5-d9e0238f7ed0/PARTNROFF=1 rootwait rw noinitrd vt.global_cursor_default=0 add_efi_memmap boot=local noresume noswap i915.modeset=1 nmi_watchdog=panic,lapic disablevmx=off"
|
||||
CONFIG_BOOTARGS=""
|
||||
CONFIG_BOOTARGS_SUBST=y
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
CONFIG_LOGF_FUNC=y
|
||||
CONFIG_SPL_LOG=y
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_LAST_STAGE_INIT=y
|
||||
@ -54,11 +57,11 @@ CONFIG_CMD_READ=y
|
||||
CONFIG_CMD_SATA=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_SOUND=y
|
||||
CONFIG_CMD_BOOTSTAGE=y
|
||||
CONFIG_CMD_TPM=y
|
||||
CONFIG_CMD_CBFS=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_EXT4=y
|
||||
CONFIG_CMD_EXT4_WRITE=y
|
||||
@ -71,13 +74,11 @@ CONFIG_ISO_PARTITION=y
|
||||
CONFIG_EFI_PARTITION=y
|
||||
# CONFIG_SPL_EFI_PARTITION is not set
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
# CONFIG_NET is not set
|
||||
CONFIG_REGMAP=y
|
||||
CONFIG_SYSCON=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_INTEL_ACPIGEN=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_BOARD=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_DW=y
|
||||
CONFIG_MISC=y
|
||||
@ -98,6 +99,7 @@ CONFIG_SOUND_MAX98357A=y
|
||||
CONFIG_SOUND_RT5677=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_ICH_SPI=y
|
||||
# CONFIG_SYSINFO_SMBIOS is not set
|
||||
CONFIG_TPL_SYSRESET=y
|
||||
# CONFIG_TPM_V1 is not set
|
||||
CONFIG_TPM2_CR50_I2C=y
|
||||
@ -105,10 +107,13 @@ CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_KEYBOARD=y
|
||||
CONFIG_VIDEO_COPY=y
|
||||
CONFIG_FS_CBFS=y
|
||||
CONFIG_SPL_FS_CBFS=y
|
||||
CONFIG_FAT_WRITE=y
|
||||
# CONFIG_SPL_USE_TINY_PRINTF is not set
|
||||
CONFIG_TPL_USE_TINY_PRINTF=y
|
||||
CONFIG_CMD_DHRYSTONE=y
|
||||
CONFIG_TPM=y
|
||||
# CONFIG_GZIP is not set
|
||||
CONFIG_BLOBLIST_TABLES=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
|
@ -12,7 +12,6 @@ CONFIG_DM_GPIO=y
|
||||
CONFIG_DEBUG_UART_BASE=0xf0512000
|
||||
CONFIG_DEBUG_UART_CLOCK=200000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-clearfog-gt-8k"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
@ -78,4 +77,3 @@ CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -43,3 +43,4 @@ CONFIG_SOUND=y
|
||||
CONFIG_SOUND_I8254=y
|
||||
CONFIG_CONSOLE_SCROLL_LINES=5
|
||||
# CONFIG_GZIP is not set
|
||||
CONFIG_SMBIOS_PARSER=y
|
||||
|
@ -157,8 +157,6 @@ CONFIG_CLK=y
|
||||
CONFIG_ICS8N3QV01=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_CPU_MPC83XX=y
|
||||
CONFIG_BOARD=y
|
||||
CONFIG_BOARD_GAZERBEAM=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_MPC8XXX_GPIO=y
|
||||
CONFIG_DM_I2C=y
|
||||
@ -197,6 +195,8 @@ CONFIG_MPC83XX_SDRAM=y
|
||||
CONFIG_DM_RESET=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_GAZERBEAM=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SYSRESET_MPC83XX=y
|
||||
CONFIG_TIMER=y
|
||||
|
@ -16,7 +16,6 @@ CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_SPL_SPI_FLASH_SUPPORT=y
|
||||
CONFIG_SPL_SPI_SUPPORT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3368-lion"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME="sheep_rk3368"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_ANDROID_BOOT_IMAGE=y
|
||||
CONFIG_FIT=y
|
||||
@ -89,4 +88,5 @@ CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
CONFIG_SMBIOS_MANUFACTURER="rockchip"
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SMBIOS=y
|
||||
|
@ -5,7 +5,6 @@ CONFIG_SYS_TEXT_BASE=0x41e00000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_NR_DRAM_BANKS=1
|
||||
CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_DEFAULT_FDT_FILE="mt7622-rfb"
|
||||
CONFIG_LOGLEVEL=7
|
||||
|
@ -11,7 +11,6 @@ CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DEBUG_UART_BASE=0xf0512000
|
||||
CONFIG_DEBUG_UART_CLOCK=200000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-8040-db"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
@ -72,4 +71,3 @@ CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_USB_ETHER_MCS7830=y
|
||||
CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -67,4 +67,5 @@ CONFIG_MXC_UART=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_SMBIOS_MANUFACTURER="MYiR"
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SMBIOS=y
|
||||
|
@ -8,7 +8,6 @@ CONFIG_DEBUG_UART_BASE=0xc81004c0
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_IDENT_STRING=" odroid-c2"
|
||||
CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-odroidc2"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME="ODROID-C2"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
# CONFIG_DISPLAY_CPUINFO is not set
|
||||
@ -64,4 +63,5 @@ CONFIG_BMP_16BPP=y
|
||||
CONFIG_BMP_24BPP=y
|
||||
CONFIG_BMP_32BPP=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER="Hardkernel Co., Ltd."
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SMBIOS=y
|
||||
|
@ -8,7 +8,6 @@ CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_BEACON_RZG2M=y
|
||||
# CONFIG_SPL is not set
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a774a1-beacon-rzg2m-kit"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
|
||||
@ -64,4 +63,3 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -11,7 +11,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_EAGLE=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77970-eagle-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
@ -74,4 +73,3 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -11,7 +11,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_CONDOR=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77980-condor-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
@ -75,4 +74,3 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -10,7 +10,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_EBISU=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77990-ebisu-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
@ -84,4 +83,3 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -10,7 +10,6 @@ CONFIG_SPL_TEXT_BASE=0xe6318000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_DRAAK=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77995-draak-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
@ -85,4 +84,3 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -9,7 +9,6 @@ CONFIG_SPL_TEXT_BASE=0xe6338000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_SALVATOR_X=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77950-salvator-x-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
@ -89,4 +88,3 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -10,7 +10,6 @@ CONFIG_SPL_TEXT_BASE=0xe6338000
|
||||
CONFIG_RCAR_GEN3=y
|
||||
CONFIG_TARGET_ULCB=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="r8a77950-ulcb-u-boot"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME=""
|
||||
CONFIG_FIT=y
|
||||
CONFIG_SUPPORT_RAW_INITRD=y
|
||||
CONFIG_USE_BOOTARGS=y
|
||||
@ -87,4 +86,3 @@ CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_GENERIC=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_SMBIOS_MANUFACTURER=""
|
||||
|
@ -13,7 +13,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3328-roc-cc"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME="roc-rk3328-cc"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
@ -100,4 +99,5 @@ CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_TPL_TINY_MEMSET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
CONFIG_SMBIOS_MANUFACTURER="firefly"
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SMBIOS=y
|
||||
|
@ -14,7 +14,6 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x4000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock-pi-e"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME="rock-pi-e_rk3328"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
@ -102,4 +101,5 @@ CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_TPL_TINY_MEMSET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
CONFIG_SMBIOS_MANUFACTURER="radxa"
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SMBIOS=y
|
||||
|
@ -13,7 +13,6 @@ CONFIG_SPL_STACK_R_ADDR=0x600000
|
||||
CONFIG_DEBUG_UART_BASE=0xFF130000
|
||||
CONFIG_DEBUG_UART_CLOCK=24000000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
|
||||
# CONFIG_ANDROID_BOOT_IMAGE is not set
|
||||
@ -99,4 +98,5 @@ CONFIG_USB_GADGET_DWC2_OTG=y
|
||||
CONFIG_SPL_TINY_MEMSET=y
|
||||
CONFIG_TPL_TINY_MEMSET=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
CONFIG_SMBIOS_MANUFACTURER="pine64"
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SMBIOS=y
|
||||
|
@ -109,8 +109,6 @@ CONFIG_CPU=y
|
||||
CONFIG_DM_DEMO=y
|
||||
CONFIG_DM_DEMO_SIMPLE=y
|
||||
CONFIG_DM_DEMO_SHAPE=y
|
||||
CONFIG_BOARD=y
|
||||
CONFIG_BOARD_SANDBOX=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_DM_GPIO_LOOKUP_LABEL=y
|
||||
CONFIG_PM8916_GPIO=y
|
||||
@ -201,6 +199,8 @@ CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SANDBOX_SPI=y
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_SPMI_SANDBOX=y
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SANDBOX=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_TIMER_EARLY=y
|
||||
|
@ -131,8 +131,6 @@ CONFIG_CPU=y
|
||||
CONFIG_DM_DEMO=y
|
||||
CONFIG_DM_DEMO_SIMPLE=y
|
||||
CONFIG_DM_DEMO_SHAPE=y
|
||||
CONFIG_BOARD=y
|
||||
CONFIG_BOARD_SANDBOX=y
|
||||
CONFIG_DMA=y
|
||||
CONFIG_DMA_CHANNELS=y
|
||||
CONFIG_SANDBOX_DMA=y
|
||||
@ -238,6 +236,8 @@ CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SANDBOX_SPI=y
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_SPMI_SANDBOX=y
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SANDBOX=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_TIMER_EARLY=y
|
||||
|
@ -90,8 +90,6 @@ CONFIG_CPU=y
|
||||
CONFIG_DM_DEMO=y
|
||||
CONFIG_DM_DEMO_SIMPLE=y
|
||||
CONFIG_DM_DEMO_SHAPE=y
|
||||
CONFIG_BOARD=y
|
||||
CONFIG_BOARD_SANDBOX=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_DM_GPIO_LOOKUP_LABEL=y
|
||||
CONFIG_PM8916_GPIO=y
|
||||
@ -177,6 +175,8 @@ CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SANDBOX_SPI=y
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_SPMI_SANDBOX=y
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SANDBOX=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_TIMER=y
|
||||
CONFIG_TIMER_EARLY=y
|
||||
|
@ -111,8 +111,6 @@ CONFIG_CPU=y
|
||||
CONFIG_DM_DEMO=y
|
||||
CONFIG_DM_DEMO_SIMPLE=y
|
||||
CONFIG_DM_DEMO_SHAPE=y
|
||||
CONFIG_BOARD=y
|
||||
CONFIG_BOARD_SANDBOX=y
|
||||
CONFIG_SPL_FIRMWARE=y
|
||||
CONFIG_GPIO_HOG=y
|
||||
CONFIG_PM8916_GPIO=y
|
||||
@ -196,6 +194,8 @@ CONFIG_SOC_DEVICE=y
|
||||
CONFIG_SANDBOX_SPI=y
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_SPMI_SANDBOX=y
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SANDBOX=y
|
||||
CONFIG_SYSRESET=y
|
||||
CONFIG_SPL_SYSRESET=y
|
||||
CONFIG_TIMER=y
|
||||
|
@ -11,7 +11,6 @@ CONFIG_DM_GPIO=y
|
||||
CONFIG_DEBUG_UART_BASE=0xd0012000
|
||||
CONFIG_DEBUG_UART_CLOCK=25804800
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-3720-uDPU"
|
||||
CONFIG_SMBIOS_PRODUCT_NAME="uDPU"
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
@ -97,3 +96,5 @@ CONFIG_USB_ETHER_RTL8152=y
|
||||
CONFIG_USB_ETHER_SMSC95XX=y
|
||||
CONFIG_LZO=y
|
||||
CONFIG_SPL_LZO=y
|
||||
CONFIG_SYSINFO=y
|
||||
CONFIG_SYSINFO_SMBIOS=y
|
||||
|
@ -740,6 +740,14 @@ Note that this is a development feature only. It is not intended for use in
|
||||
production environments. Also it is not currently part of the automated tests
|
||||
so may break in the future.
|
||||
|
||||
SMBIOS tables
|
||||
-------------
|
||||
|
||||
To generate SMBIOS tables in U-Boot, for use by the OS, enable the
|
||||
CONFIG_GENERATE_SMBIOS_TABLE option. The easiest way to provide the values to
|
||||
use is via the device tree. For details see
|
||||
device-tree-bindings/sysinfo/smbios.txt
|
||||
|
||||
TODO List
|
||||
---------
|
||||
- Audio
|
||||
|
@ -1,11 +1,11 @@
|
||||
gdsys Gazerbeam board driver
|
||||
gdsys Gazerbeam sysinfo driver
|
||||
|
||||
This driver provides capabilities to access the gdsys Gazerbeam board's device
|
||||
information. Furthermore, phandles to some internal devices are provided for
|
||||
the board files.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be "gdsys,board_gazerbeam"
|
||||
- compatible: should be "gdsys,sysinfo-gazerbeam"
|
||||
- csb: phandle to the board's coherent system bus (CSB) device node
|
||||
- rxaui[0-3]: phandles to the rxaui control device nodes
|
||||
- fpga[0-1]: phandles to the board's gdsys FPGA device nodes
|
||||
@ -17,8 +17,8 @@ Required properties:
|
||||
Example:
|
||||
|
||||
|
||||
board {
|
||||
compatible = "gdsys,board_gazerbeam";
|
||||
sysinfo {
|
||||
compatible = "gdsys,sysinfo-gazerbeam";
|
||||
csb = <&board_soc>;
|
||||
serdes = <&SERDES>;
|
||||
rxaui0 = <&RXAUI0>;
|
77
doc/device-tree-bindings/sysinfo/smbios.txt
Normal file
77
doc/device-tree-bindings/sysinfo/smbios.txt
Normal file
@ -0,0 +1,77 @@
|
||||
SMBIOS sysinfo information
|
||||
==========================
|
||||
|
||||
This binding allows the values for the SMBIOS tables to be specified in the
|
||||
devicetree, as below.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: "u-boot,smbios" or any other string depending on your board
|
||||
|
||||
This driver allows providing board-specific features such as power control
|
||||
GPIOs. In addition, the SMBIOS values can be specified in the device tree,
|
||||
as below:
|
||||
|
||||
An optional 'smbios' subnode can be used to provide these properties. Within
|
||||
that, the properties are broken down by table type, as in the System Management
|
||||
BIOS (Basic Input/Output System) Specification.
|
||||
|
||||
Available subnodes for each table type are:
|
||||
|
||||
- 1 : system
|
||||
- 2 : baseboard
|
||||
- 3 : chassis
|
||||
|
||||
Within each subnode the following tables are recognised:
|
||||
|
||||
"system" subnode optional properties:
|
||||
|
||||
- manufacturer: Product manufacturer for system
|
||||
- product: Product name
|
||||
- version: Product version string
|
||||
- serial: Serial number for system (note that this can be overridden by
|
||||
the serial# environment variable)
|
||||
- sku: Product SKU (Stock-Keeping Unit)
|
||||
- family: Product family
|
||||
|
||||
"baseboard" subnode optional properties:
|
||||
|
||||
- manufacturer: Product manufacturer for baseboard
|
||||
- product: Product name
|
||||
- asset-tag: Asset tag for the motherboard, sometimes used in organisations
|
||||
to track devices
|
||||
|
||||
"chassis" subnode optional properties:
|
||||
|
||||
- manufacturer: Product manufacturer for chassis
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
sysinfo {
|
||||
compatible = "sandbox,sysinfo-sandbox";
|
||||
|
||||
smbios {
|
||||
/* Type 1 table */
|
||||
system {
|
||||
manufacturer = "Google";
|
||||
product = "Coral";
|
||||
version = "rev2";
|
||||
serial = "123456789";
|
||||
sku = "sku3";
|
||||
family = "Google_Coral";
|
||||
};
|
||||
|
||||
/* Type 2 table */
|
||||
baseboard {
|
||||
manufacturer = "Google";
|
||||
product = "Coral";
|
||||
asset-tag = "ABC123";
|
||||
};
|
||||
|
||||
/* Type 3 table */
|
||||
chassis {
|
||||
manufacturer = "Google";
|
||||
};
|
||||
};
|
||||
};
|
19
doc/device-tree-bindings/sysinfo/sysinfo.txt
Normal file
19
doc/device-tree-bindings/sysinfo/sysinfo.txt
Normal file
@ -0,0 +1,19 @@
|
||||
Sysinfo
|
||||
=======
|
||||
|
||||
This provides capabilities to access information about a board/system, for
|
||||
use by drivers.
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: any suitable string where the driver is in the UCLASS_SYSINFO
|
||||
class
|
||||
|
||||
See also smbios.txt
|
||||
|
||||
|
||||
Example
|
||||
|
||||
sysinfo {
|
||||
compatible = "sandbox,sysinfo-sandbox";
|
||||
};
|
@ -30,8 +30,6 @@ source "drivers/ddr/Kconfig"
|
||||
|
||||
source "drivers/demo/Kconfig"
|
||||
|
||||
source "drivers/board/Kconfig"
|
||||
|
||||
source "drivers/ddr/fsl/Kconfig"
|
||||
|
||||
source "drivers/dfu/Kconfig"
|
||||
@ -114,6 +112,8 @@ source "drivers/spi/Kconfig"
|
||||
|
||||
source "drivers/spmi/Kconfig"
|
||||
|
||||
source "drivers/sysinfo/Kconfig"
|
||||
|
||||
source "drivers/sysreset/Kconfig"
|
||||
|
||||
source "drivers/tee/Kconfig"
|
||||
|
@ -27,9 +27,9 @@ obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/
|
||||
obj-$(CONFIG_$(SPL_TPL_)VIRTIO) += virtio/
|
||||
obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/
|
||||
obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
|
||||
obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/
|
||||
obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
|
||||
obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/
|
||||
obj-$(CONFIG_$(SPL_)BOARD) += board/
|
||||
obj-$(CONFIG_XEN) += xen/
|
||||
obj-$(CONFIG_$(SPL_)FPGA) += fpga/
|
||||
|
||||
|
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Reference in New Issue
Block a user