mirror of
https://github.com/u-boot/u-boot.git
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eNET: General code cleanup
This commit is contained in:
Graeme Russ
parent
c083e4bab1
commit
cfbe861506
@ -35,16 +35,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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#undef SC520_CDP_DEBUG
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#ifdef SC520_CDP_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
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static void enet_timer_isr(void);
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static void enet_toggle_run_led(void);
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static void enet_setup_pars(void);
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@ -199,22 +189,23 @@ int last_stage_init(void)
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outb(0x00, LED_LATCH_ADDRESS);
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register_timer_isr (enet_timer_isr);
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register_timer_isr(enet_timer_isr);
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printf("Serck Controls eNET\n");
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return 0;
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}
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ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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if (banknum == 0) { /* non-CFI boot flash */
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info->portwidth = FLASH_CFI_8BIT;
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info->chipwidth = FLASH_CFI_BY8;
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info->interface = FLASH_CFI_X8;
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return 1;
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} else
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} else {
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return 0;
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}
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}
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int board_eth_init(bd_t *bis)
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@ -29,10 +29,3 @@ early_board_init:
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/* No 32-bit board specific initialisation */
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jmp early_board_init_ret
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.globl cpu_halt_asm
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cpu_halt_asm:
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movb $0x0f, %al
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movw $LED_LATCH_ADDRESS, %dx
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outb %al, %dx
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hlt
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jmp cpu_halt_asm
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@ -29,124 +29,114 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Stuff still to be dealt with -
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*/
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#define CONFIG_RTC_MC146818
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define DEBUG_PARSER
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#define CONFIG_X86 1 /* Intel X86 CPU */
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#define CONFIG_SYS_SC520 1 /* AMD SC520 */
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#define CONFIG_X86
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#define CONFIG_SYS_SC520
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#define CONFIG_SYS_SC520_SSI
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#define CONFIG_SHOW_BOOT_PROGRESS 1
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#define CONFIG_LAST_STAGE_INIT 1
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#define CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_LAST_STAGE_INIT
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/*
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* If CONFIG_HW_WATCHDOG is not defined, the watchdog jumper on the
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/*-----------------------------------------------------------------------
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* Watchdog Configuration
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* NOTE: If CONFIG_HW_WATCHDOG is NOT defined, the watchdog jumper on the
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* bottom (processor) board MUST be removed!
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*/
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#undef CONFIG_WATCHDOG
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#define CONFIG_HW_WATCHDOG
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/*-----------------------------------------------------------------------
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* Serial Configuration
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*/
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/*-----------------------------------------------------------------------
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* Real Time Clock Configuration
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*/
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#define CONFIG_RTC_MC146818
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#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
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/*-----------------------------------------------------------------------
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* Serial Configuration
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*/
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#define CONFIG_SERIAL_MULTI
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 1843200
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CONFIG_SYS_NS16550_COM1 UART0_BASE
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#define CONFIG_SYS_NS16550_COM2 UART1_BASE
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#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
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#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK 1843200
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, \
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9600, 19200, 38400, 115200}
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#define CONFIG_SYS_NS16550_COM1 UART0_BASE
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#define CONFIG_SYS_NS16550_COM2 UART1_BASE
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#define CONFIG_SYS_NS16550_COM3 (0x1000 + UART0_BASE)
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#define CONFIG_SYS_NS16550_COM4 (0x1000 + UART1_BASE)
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#define CONFIG_SYS_NS16550_PORT_MAPPED
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/*-----------------------------------------------------------------------
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* Video Configuration
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*/
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#undef CONFIG_VIDEO /* No Video Hardware */
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#undef CONFIG_CFB_CONSOLE
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/*
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* Size of malloc() pool
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/*-----------------------------------------------------------------------
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* Video Configuration
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#undef CONFIG_VIDEO
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#undef CONFIG_CFB_CONSOLE
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/*-----------------------------------------------------------------------
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BDI /* bdinfo */
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#define CONFIG_CMD_BOOTD /* bootd */
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#define CONFIG_CMD_CONSOLE /* coninfo */
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_BOOTD
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#define CONFIG_CMD_CONSOLE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_ECHO /* echo arguments */
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#define CONFIG_CMD_FLASH /* flinfo, erase, protect */
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#define CONFIG_CMD_FPGA /* FPGA configuration Support */
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#define CONFIG_CMD_IMI /* iminfo */
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#define CONFIG_CMD_IMLS /* List all found images */
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#define CONFIG_CMD_IRQ /* IRQ Information */
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#define CONFIG_CMD_ITEST /* Integer (and string) test */
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#define CONFIG_CMD_LOADB /* loadb */
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#define CONFIG_CMD_LOADS /* loads */
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#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */
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#define CONFIG_CMD_MISC /* Misc functions like sleep etc*/
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#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
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#undef CONFIG_CMD_NFS /* NFS support */
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#define CONFIG_CMD_PCI /* PCI support */
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#define CONFIG_CMD_PING /* ICMP echo support */
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#define CONFIG_CMD_RUN /* run command in env variable */
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#define CONFIG_CMD_SAVEENV /* saveenv */
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#define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */
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#define CONFIG_CMD_SOURCE /* "source" command Support */
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#define CONFIG_CMD_XIMG /* Load part of Multi Image */
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_FPGA
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_IMLS
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#define CONFIG_CMD_IRQ
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#define CONFIG_CMD_ITEST
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#define CONFIG_CMD_LOADB
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#define CONFIG_CMD_LOADS
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_MISC
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#define CONFIG_CMD_NET
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#undef CONFIG_CMD_NFS
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_SAVEENV
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#define CONFIG_CMD_SETGETDCR
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#define CONFIG_CMD_SOURCE
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#define CONFIG_CMD_XIMG
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#define CONFIG_BOOTDELAY 15
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
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/* #define CONFIG_BOOTCOMMAND "bootm 38000000" */
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#define CONFIG_BOOTDELAY 15
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyS0,9600"
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#define CONFIG_KGDB_BAUDRATE 115200
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#define CONFIG_KGDB_SER_INDEX 2
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + \
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16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_SYS_PROMPT "boot > "
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#define CONFIG_SYS_CBSIZE 256
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + \
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16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 1 ... 16 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_HZ 1000 /* incrementer freq: 1kHz */
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#define CONFIG_SYS_MEMTEST_START 0x00100000
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#define CONFIG_SYS_MEMTEST_END 0x01000000
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#define CONFIG_SYS_LOAD_ADDR 0x100000
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#define CONFIG_SYS_HZ 1000
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/*-----------------------------------------------------------------------
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* SDRAM Configuration
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*/
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#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
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#define CONFIG_NR_DRAM_BANKS 4
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#define CONFIG_SYS_SDRAM_DRCTMCTL 0x18
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#define CONFIG_NR_DRAM_BANKS 4
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/* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
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#undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
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@ -158,95 +148,77 @@
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/*-----------------------------------------------------------------------
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* CPU Features
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*/
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#define CONFIG_SYS_SC520_HIGH_SPEED 0 /* 100 or 133MHz */
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#define CONFIG_SYS_SC520_RESET /* use SC520 MMCR's to reset cpu */
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#define CONFIG_SYS_SC520_TIMER /* use SC520 swtimers */
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#undef CONFIG_SYS_GENERIC_TIMER /* use the i8254 PIT timers */
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#undef CONFIG_SYS_TSC_TIMER /* use the Pentium TSC timers */
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#define CONFIG_SYS_USE_SIO_UART 0 /* prefer the uarts on the SIO to those
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* in the SC520 on the CDP */
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#define CONFIG_SYS_SC520_HIGH_SPEED 0
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#define CONFIG_SYS_SC520_RESET
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#define CONFIG_SYS_SC520_TIMER
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#undef CONFIG_SYS_GENERIC_TIMER
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#define CONFIG_SYS_PCAT_INTERRUPTS
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#define CONFIG_SYS_NUM_IRQS 16
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#define CONFIG_SYS_NUM_IRQS 16
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/*-----------------------------------------------------------------------
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* Memory organization
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* Memory organization:
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* 32kB Stack
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* 256kB Monitor
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*/
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#define CONFIG_SYS_STACK_SIZE 0x8000 /* Size of bootloader stack */
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#define CONFIG_SYS_BL_START_FLASH 0x38040000 /* Address of relocated code */
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#define CONFIG_SYS_BL_START_RAM 0x03fd0000 /* Address of relocated code */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CONFIG_SYS_FLASH_BASE 0x38000000 /* Boot Flash */
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#define CONFIG_SYS_FLASH_BASE_1 0x10000000 /* StrataFlash 1 */
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#define CONFIG_SYS_FLASH_BASE_2 0x11000000 /* StrataFlash 2 */
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/* timeout values are in ticks */
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#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
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#define CONFIG_SYS_STACK_SIZE 0x8000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*-----------------------------------------------------------------------
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* FLASH configuration
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*/
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#define CONFIG_FLASH_CFI_DRIVER /* Use the common driver */
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/*-----------------------------------------------------------------------
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* FLASH configuration
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* 512kB Boot Flash @ 0x38000000 (Monitor @ 38040000)
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* 16MB StrataFlash #1 @ 0x10000000
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* 16MB StrataFlash #2 @ 0x11000000
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*/
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_FLASH_CFI_LEGACY
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#define CONFIG_SYS_FLASH_CFI /* Flash is CFI conformant */
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#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max number of memory banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE_1, \
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CONFIG_SYS_FLASH_BASE_2}
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_MAX_FLASH_BANKS 3
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#define CONFIG_SYS_FLASH_BASE 0x38000000
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#define CONFIG_SYS_FLASH_BASE_1 0x10000000
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#define CONFIG_SYS_FLASH_BASE_2 0x11000000
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
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CONFIG_SYS_FLASH_BASE_1, \
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CONFIG_SYS_FLASH_BASE_2}
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CONFIG_SYS_FLASH_LEGACY_512Kx8
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/*-----------------------------------------------------------------------
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* Environment configuration
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*/
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
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#define CONFIG_SYS_FLASH_ERASE_TOUT 2000 /* ms */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 2000 /* ms */
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/*-----------------------------------------------------------------------
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* Environment configuration
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*/
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE_1
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/* Redundant Copy */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE_1 + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SECT_SIZE
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/*-----------------------------------------------------------------------
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* PCI configuration
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*/
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#define CONFIG_PCI
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#define CONFIG_PCI_PNP
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#define CONFIG_SYS_FIRST_PCI_IRQ 10
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#define CONFIG_SYS_SECOND_PCI_IRQ 9
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#define CONFIG_SYS_THIRD_PCI_IRQ 11
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#define CONFIG_SYS_FORTH_PCI_IRQ 15
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/*-----------------------------------------------------------------------
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* PCI configuration
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*/
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* pci plug-and-play */
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#define CONFIG_SYS_FIRST_PCI_IRQ 10
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#define CONFIG_SYS_SECOND_PCI_IRQ 9
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#define CONFIG_SYS_THIRD_PCI_IRQ 11
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#define CONFIG_SYS_FORTH_PCI_IRQ 15
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/*
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/*-----------------------------------------------------------------------
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* Network device (TRL8100B) support
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*/
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#define CONFIG_NET_MULTI
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#define CONFIG_RTL8139
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/*-----------------------------------------------------------------------
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* FPGA configuration
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*/
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#define CONFIG_SYS_FPGA_PROGRAM_PIO_BIT 0x2000
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#define CONFIG_SYS_FPGA_INIT_PIO_BIT 0x4000
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#define CONFIG_SYS_FPGA_DONE_PIO_BIT 0x8000
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#define CONFIG_SYS_FPGA_PIO_DATA SC520_PIODATA31_16
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#define CONFIG_SYS_FPGA_PIO_DIRECTION SC520_PIODIR31_16
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#define CONFIG_SYS_FPGA_PIO_CLR SC520_PIOCLR31_16
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#define CONFIG_SYS_FPGA_PIO_SET SC520_PIOSET31_16
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#define CONFIG_SYS_FPGA_PROGRAM_BIT_DROP_TIME 1 /* milliseconds */
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#define CONFIG_SYS_FPGA_MAX_INIT_TIME 10 /* milliseconds */
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#define CONFIG_SYS_FPGA_MAX_FINALISE_TIME 10 /* milliseconds */
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#define CONFIG_SYS_FPGA_SSI_DATA_RATE 8333 /* kHz (33.3333MHz xtal) */
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/*-----------------------------------------------------------------------
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* BOOTCS Control (for AM29LV040B-120JC)
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*
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@ -614,17 +586,4 @@
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*/
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#define CONFIG_SYS_SC520_DPRAM_PAR 0x50018100
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#ifndef __ASSEMBLER__
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extern unsigned long ip;
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#define PRINTIP asm ("call 0\n" \
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"0:\n" \
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"pop %%eax\n" \
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"movl %%eax, %0\n" \
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:"=r"(ip) \
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: /* No Input Registers */ \
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:"%eax"); \
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printf("IP: 0x%08lx (File: %s, Line: %d)\n", ip, __FILE__, __LINE__);
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#endif
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#endif /* __CONFIG_H */
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