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ppc4xx: t3corp: Add support for the Xilinx DS617 flash chip

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The t3corp board has an Xilinx DS617 flash chip connected to the
onboard FPGA. This patch adds support for these chips. Board
specific flash accessor functions are needed, since the chips
can only be read correctly in 16bit mode.

Additionally the FPGA chip-selects are configured for device-paced
transfers (ready is enabled).

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2010-10-25 18:32:08 +02:00
parent 97a85b223a
commit cf1971c1c0
2 changed files with 50 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
board/t3corp/t3corp.c
View File

@ -23,6 +23,7 @@
#include <libfdt.h>
#include <fdt_support.h>
#include <i2c.h>
#include <mtd/cfi_flash.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
@ -191,3 +192,40 @@ struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
{
return board_scan_options;
}
/*
* Accessor functions replacing the "weak" functions in
* drivers/mtd/cfi_flash.c
*
* The NOR flash devices "behind" the FPGA's (Xilinx DS617)
* can only be read correctly in 16bit mode. We need to emulate
* 8bit and 32bit reads here in the board specific code.
*/
u8 flash_read8(void *addr)
{
u16 val = __raw_readw((void *)((u32)addr & ~1));
if ((u32)addr & 1)
return val;
return val >> 8;
}
u32 flash_read32(void *addr)
{
return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
}
void flash_cmd_reset(flash_info_t *info)
{
/*
* FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
* needs the Spansion type reset commands. The other flash chip
* is located behind a FPGA (Xilinx DS617) and needs the Intel type
* reset command.
*/
if (info->start[0] == CONFIG_SYS_FLASH_BASE)
flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
else
flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
}

18
include/configs/t3corp.h
View File

@ -120,11 +120,16 @@
*/
#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD reset cmd */
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* use status poll method */
#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \
(CONFIG_SYS_FPGA1_BASE + 0x01000000) }
#define CONFIG_SYS_CFI_FLASH_CONFIG_REGS { 0xffff, /* don't set */ \
0xbddf } /* set async read mode */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors p. chip*/
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms*/
@ -355,6 +360,7 @@
"ramdisk_addr=fc200000\0" \
"pciconfighost=1\0" \
"pcie_mode=RP:RP\0" \
"unlock=yes\0" \
""
/*
@ -423,7 +429,7 @@
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
EBC_BXAP_RE_DISABLED | \
EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
@ -440,7 +446,7 @@
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
EBC_BXAP_RE_DISABLED | \
EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)
@ -457,7 +463,7 @@
EBC_BXAP_WBN_ENCODE(0) | \
EBC_BXAP_WBF_ENCODE(0) | \
EBC_BXAP_TH_ENCODE(1) | \
EBC_BXAP_RE_DISABLED | \
EBC_BXAP_RE_ENABLED | \
EBC_BXAP_SOR_DELAYED | \
EBC_BXAP_BEM_RW | \
EBC_BXAP_PEN_DISABLED)