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drivers: fsl-mc: Update qbman driver
Update qbman driver - As per latest available qbman driver - Use of atomic APIs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Geoff Thorpe <Geoff.Thorpe@freescale.com> CC: Haiying Wang <Haiying.Wang@freescale.com> CC: Roy Pledge <Roy.Pledge@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Prabhakar Kushwaha
York Sun
parent
1f1c25c745
commit
cd8aefc076
@ -64,7 +64,7 @@ enum qbman_sdqcr_fc {
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struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
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{
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int ret;
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struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
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struct qbman_swp *p = malloc(sizeof(struct qbman_swp));
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if (!p)
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return NULL;
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@ -77,7 +77,7 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
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qb_attr_code_encode(&code_sdqcr_dct, &p->sdq, qbman_sdqcr_dct_prio_ics);
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qb_attr_code_encode(&code_sdqcr_fc, &p->sdq, qbman_sdqcr_fc_up_to_3);
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qb_attr_code_encode(&code_sdqcr_tok, &p->sdq, 0xbb);
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p->vdq.busy = 0; /* TODO: convert to atomic_t */
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atomic_set(&p->vdq.busy, 1);
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p->vdq.valid_bit = QB_VALID_BIT;
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p->dqrr.next_idx = 0;
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p->dqrr.valid_bit = QB_VALID_BIT;
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@ -165,7 +165,6 @@ static struct qb_attr_code code_eq_qd_bin = QB_CODE(4, 0, 16);
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static struct qb_attr_code code_eq_qd_pri = QB_CODE(4, 16, 4);
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static struct qb_attr_code code_eq_rsp_stash = QB_CODE(5, 16, 1);
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static struct qb_attr_code code_eq_rsp_lo = QB_CODE(6, 0, 32);
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static struct qb_attr_code code_eq_rsp_hi = QB_CODE(7, 0, 32);
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enum qbman_eq_cmd_e {
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/* No enqueue, primarily for plugging ORP gaps for dropped frames */
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@ -197,8 +196,7 @@ void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
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{
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uint32_t *cl = qb_cl(d);
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qb_attr_code_encode(&code_eq_rsp_lo, cl, lower32(storage_phys));
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qb_attr_code_encode(&code_eq_rsp_hi, cl, upper32(storage_phys));
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qb_attr_code_encode_64(&code_eq_rsp_lo, (uint64_t *)cl, storage_phys);
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qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash);
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}
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@ -253,7 +251,6 @@ static struct qb_attr_code code_pull_numframes = QB_CODE(0, 8, 4);
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static struct qb_attr_code code_pull_token = QB_CODE(0, 16, 8);
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static struct qb_attr_code code_pull_dqsource = QB_CODE(1, 0, 24);
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static struct qb_attr_code code_pull_rsp_lo = QB_CODE(2, 0, 32);
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static struct qb_attr_code code_pull_rsp_hi = QB_CODE(3, 0, 32);
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enum qb_pull_dt_e {
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qb_pull_dt_channel,
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@ -282,8 +279,7 @@ void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
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}
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qb_attr_code_encode(&code_pull_rls, cl, 1);
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qb_attr_code_encode(&code_pull_stash, cl, !!stash);
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qb_attr_code_encode(&code_pull_rsp_lo, cl, lower32(storage_phys));
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qb_attr_code_encode(&code_pull_rsp_hi, cl, upper32(storage_phys));
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qb_attr_code_encode_64(&code_pull_rsp_lo, (uint64_t *)cl, storage_phys);
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}
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void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes)
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@ -316,10 +312,10 @@ int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
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uint32_t *p;
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uint32_t *cl = qb_cl(d);
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/* TODO: convert to atomic_t */
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if (s->vdq.busy)
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if (!atomic_dec_and_test(&s->vdq.busy)) {
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atomic_inc(&s->vdq.busy);
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return -EBUSY;
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s->vdq.busy = 1;
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}
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s->vdq.storage = *(void **)&cl[4];
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s->vdq.token = qb_attr_code_decode(&code_pull_token, cl);
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p = qbman_cena_write_start(&s->sys, QBMAN_CENA_SWP_VDQCR);
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@ -359,36 +355,44 @@ const struct ldpaa_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
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{
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uint32_t verb;
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uint32_t response_verb;
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const struct ldpaa_dq *dq = qbman_cena_read(&s->sys,
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QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
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const uint32_t *p = qb_cl(dq);
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uint32_t flags;
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const struct ldpaa_dq *dq;
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const uint32_t *p;
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dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
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p = qb_cl(dq);
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verb = qb_attr_code_decode(&code_dqrr_verb, p);
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/* If the valid-bit isn't of the expected polarity, nothing there */
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/* If the valid-bit isn't of the expected polarity, nothing there. Note,
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* in the DQRR reset bug workaround, we shouldn't need to skip these
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* check, because we've already determined that a new entry is available
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* and we've invalidated the cacheline before reading it, so the
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* valid-bit behaviour is repaired and should tell us what we already
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* knew from reading PI.
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*/
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if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
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qbman_cena_invalidate_prefetch(&s->sys,
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QBMAN_CENA_SWP_DQRR(
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s->dqrr.next_idx));
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QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
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return NULL;
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}
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/* There's something there. Move "next_idx" attention to the next ring
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* entry (and prefetch it) before returning what we found. */
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s->dqrr.next_idx++;
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s->dqrr.next_idx &= 3; /* Wrap around at 4 */
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s->dqrr.next_idx &= QBMAN_DQRR_SIZE - 1; /* Wrap around at 4 */
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/* TODO: it's possible to do all this without conditionals, optimise it
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* later. */
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if (!s->dqrr.next_idx)
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s->dqrr.valid_bit ^= QB_VALID_BIT;
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/* VDQCR "no longer busy" hook - if VDQCR shows "busy" and this is a
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* VDQCR result, mark it as non-busy. */
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if (s->vdq.busy) {
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uint32_t flags = ldpaa_dq_flags(dq);
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response_verb = qb_attr_code_decode(&code_dqrr_response, &verb);
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if ((response_verb == QBMAN_DQRR_RESPONSE_DQ) &&
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(flags & LDPAA_DQ_STAT_VOLATILE))
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s->vdq.busy = 0;
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}
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/* If this is the final response to a volatile dequeue command
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indicate that the vdq is no longer busy */
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flags = ldpaa_dq_flags(dq);
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response_verb = qb_attr_code_decode(&code_dqrr_response, &verb);
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if ((response_verb == QBMAN_DQRR_RESPONSE_DQ) &&
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(flags & LDPAA_DQ_STAT_VOLATILE) &&
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(flags & LDPAA_DQ_STAT_EXPIRED))
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atomic_inc(&s->vdq.busy);
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qbman_cena_invalidate_prefetch(&s->sys,
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QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
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return dq;
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@ -448,8 +452,10 @@ int qbman_dq_entry_has_newtoken(struct qbman_swp *s,
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* reset "busy". We instead base the decision on whether the current
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* result is sitting at the first 'storage' location of the busy
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* command. */
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if (s->vdq.busy && (s->vdq.storage == dq))
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s->vdq.busy = 0;
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if (s->vdq.storage == dq) {
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s->vdq.storage = NULL;
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atomic_inc(&s->vdq.busy);
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}
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return 1;
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}
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@ -14,6 +14,10 @@
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/* Management command result codes */
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#define QBMAN_MC_RSLT_OK 0xf0
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/* TBD: as of QBMan 4.1, DQRR will be 8 rather than 4! */
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#define QBMAN_DQRR_SIZE 4
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/* --------------------- */
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/* portal data structure */
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/* --------------------- */
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@ -48,14 +52,13 @@ struct qbman_swp {
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* to whether or not a command can be submitted, not whether or
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* not a previously-submitted command is still executing. In
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* other words, once proof is seen that the previously-submitted
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* command is executing, "vdq" is no longer "busy". TODO:
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* convert this to "atomic_t" so that it is thread-safe (without
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* locking). */
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int busy;
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* command is executing, "vdq" is no longer "busy".
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*/
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atomic_t busy;
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uint32_t valid_bit; /* 0x00 or 0x80 */
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/* We need to determine when vdq is no longer busy. This depends
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* on whether the "busy" (last-submitted) dequeue command is
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* targetting DQRR or main-memory, and detected is based on the
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* targeting DQRR or main-memory, and detected is based on the
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* presence of the dequeue command's "token" showing up in
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* dequeue entries in DQRR or main-memory (respectively). Debug
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* builds will, when submitting vdq commands, verify that the
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@ -127,6 +130,7 @@ static inline uint32_t qb_attr_code_decode(const struct qb_attr_code *code,
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return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
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}
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/* encode a field to a cacheline */
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static inline void qb_attr_code_encode(const struct qb_attr_code *code,
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uint32_t *cacheline, uint32_t val)
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@ -136,6 +140,12 @@ static inline void qb_attr_code_encode(const struct qb_attr_code *code,
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| e32_uint32_t(code->lsoffset, code->width, val);
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}
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static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
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uint64_t *cacheline, uint64_t val)
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{
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cacheline[code->word / 2] = val;
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}
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/* ---------------------- */
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/* Descriptors/cachelines */
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/* ---------------------- */
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@ -144,7 +154,7 @@ static inline void qb_attr_code_encode(const struct qb_attr_code *code,
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* a "descriptor" type that the caller can instantiate however they like.
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* Ultimately though, it is just a cacheline of binary storage (or something
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* smaller when it is known that the descriptor doesn't need all 64 bytes) for
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* holding pre-formatted pieces of harware commands. The performance-critical
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* holding pre-formatted pieces of hardware commands. The performance-critical
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* code can then copy these descriptors directly into hardware command
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* registers more efficiently than trying to construct/format commands
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* on-the-fly. The API user sees the descriptor as an array of 32-bit words in
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@ -9,7 +9,7 @@
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#include <errno.h>
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#include <asm/io.h>
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#include <linux/types.h>
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#include <linux/compat.h>
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#include <asm/atomic.h>
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#include <malloc.h>
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#include <fsl-mc/fsl_qbman_base.h>
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