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serial: pxa: integrate optional driver model handling
Optional driver model handling integration. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marcel Ziswiler
Marek Vasut
parent
d804a5e1c3
commit
cbfa67a16b
@ -14,6 +14,9 @@
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
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*
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* Modified to add driver model (DM) support
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* (C) Copyright 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -21,73 +24,17 @@
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/regs-uart.h>
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#include <asm/io.h>
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#include <dm.h>
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#include <dm/platform_data/serial_pxa.h>
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#include <linux/compiler.h>
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#include <serial.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
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* easily handle enabling of clock.
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*/
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#ifdef CONFIG_CPU_MONAHANS
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#define UART_CLK_BASE CKENA_21_BTUART
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#define UART_CLK_REG CKENA
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#define BTUART_INDEX 0
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#define FFUART_INDEX 1
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#define STUART_INDEX 2
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#elif CONFIG_CPU_PXA25X
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#define UART_CLK_BASE (1 << 4) /* HWUART */
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#define UART_CLK_REG CKEN
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#define HWUART_INDEX 0
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#define STUART_INDEX 1
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#define FFUART_INDEX 2
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#define BTUART_INDEX 3
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#else /* PXA27x */
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#define UART_CLK_BASE CKEN5_STUART
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#define UART_CLK_REG CKEN
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#define STUART_INDEX 0
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#define FFUART_INDEX 1
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#define BTUART_INDEX 2
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#endif
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/*
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* Only PXA250 has HWUART, to avoid poluting the code with more macros,
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* artificially introduce this.
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*/
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#ifndef CONFIG_CPU_PXA25X
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#define HWUART_INDEX 0xff
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#endif
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static uint32_t pxa_uart_get_baud_divider(void)
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static uint32_t pxa_uart_get_baud_divider(int baudrate)
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{
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if (gd->baudrate == 1200)
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return 768;
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else if (gd->baudrate == 9600)
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return 96;
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else if (gd->baudrate == 19200)
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return 48;
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else if (gd->baudrate == 38400)
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return 24;
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else if (gd->baudrate == 57600)
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return 16;
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else if (gd->baudrate == 115200)
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return 8;
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else /* Unsupported baudrate */
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return 0;
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}
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static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
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{
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switch (uart_index) {
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case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
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case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
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case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
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case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
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default:
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return NULL;
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}
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return 921600 / baudrate;
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}
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static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
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@ -110,20 +57,14 @@ static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
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/*
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* Enable clock and set baud rate, parity etc.
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*/
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void pxa_setbrg_dev(uint32_t uart_index)
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void pxa_setbrg_common(struct pxa_uart_regs *uart_regs, int port, int baudrate)
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{
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uint32_t divider = 0;
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struct pxa_uart_regs *uart_regs;
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divider = pxa_uart_get_baud_divider();
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uint32_t divider = pxa_uart_get_baud_divider(baudrate);
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if (!divider)
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hang();
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uart_regs = pxa_uart_index_to_regs(uart_index);
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if (!uart_regs)
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hang();
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pxa_uart_toggle_clock(uart_index, 1);
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pxa_uart_toggle_clock(port, 1);
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/* Disable interrupts and FIFOs */
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writel(0, &uart_regs->ier);
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@ -139,13 +80,38 @@ void pxa_setbrg_dev(uint32_t uart_index)
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writel(IER_UUE, &uart_regs->ier);
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}
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#ifndef CONFIG_DM_SERIAL
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static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
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{
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switch (uart_index) {
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case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
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case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
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case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
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case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
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default:
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return NULL;
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}
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}
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/*
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* Enable clock and set baud rate, parity etc.
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*/
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void pxa_setbrg_dev(uint32_t uart_index)
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{
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struct pxa_uart_regs *uart_regs = pxa_uart_index_to_regs(uart_index);
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if (!uart_regs)
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panic("Failed getting UART registers\n");
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pxa_setbrg_common(uart_regs, uart_index, gd->baudrate);
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}
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*/
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int pxa_init_dev(unsigned int uart_index)
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{
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pxa_setbrg_dev (uart_index);
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pxa_setbrg_dev(uart_index);
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return 0;
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}
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@ -297,3 +263,80 @@ void pxa_serial_initialize(void)
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serial_register(&serial_stuart_device);
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#endif
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}
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#endif /* CONFIG_DM_SERIAL */
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#ifdef CONFIG_DM_SERIAL
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static int pxa_serial_probe(struct udevice *dev)
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{
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struct pxa_serial_platdata *plat = dev->platdata;
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pxa_setbrg_common((struct pxa_uart_regs *)plat->base, plat->port,
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plat->baudrate);
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return 0;
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}
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static int pxa_serial_putc(struct udevice *dev, const char ch)
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{
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struct pxa_serial_platdata *plat = dev->platdata;
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struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
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/* Wait for last character to go. */
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if (!(readl(&uart_regs->lsr) & LSR_TEMT))
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return -EAGAIN;
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writel(ch, &uart_regs->thr);
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return 0;
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}
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static int pxa_serial_getc(struct udevice *dev)
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{
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struct pxa_serial_platdata *plat = dev->platdata;
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struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
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/* Wait for a character to arrive. */
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if (!(readl(&uart_regs->lsr) & LSR_DR))
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return -EAGAIN;
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return readl(&uart_regs->rbr) & 0xff;
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}
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int pxa_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct pxa_serial_platdata *plat = dev->platdata;
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struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
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int port = plat->port;
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pxa_setbrg_common(uart_regs, port, baudrate);
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return 0;
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}
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static int pxa_serial_pending(struct udevice *dev, bool input)
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{
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struct pxa_serial_platdata *plat = dev->platdata;
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struct pxa_uart_regs *uart_regs = (struct pxa_uart_regs *)plat->base;
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if (input)
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return readl(&uart_regs->lsr) & LSR_DR ? 1 : 0;
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else
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return readl(&uart_regs->lsr) & LSR_TEMT ? 0 : 1;
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return 0;
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}
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static const struct dm_serial_ops pxa_serial_ops = {
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.putc = pxa_serial_putc,
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.pending = pxa_serial_pending,
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.getc = pxa_serial_getc,
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.setbrg = pxa_serial_setbrg,
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};
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U_BOOT_DRIVER(serial_pxa) = {
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.name = "serial_pxa",
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.id = UCLASS_SERIAL,
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.probe = pxa_serial_probe,
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.ops = &pxa_serial_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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#endif /* CONFIG_DM_SERIAL */
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56
include/dm/platform_data/serial_pxa.h
Normal file
56
include/dm/platform_data/serial_pxa.h
Normal file
@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SERIAL_PXA_H
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#define __SERIAL_PXA_H
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/*
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* The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
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* easily handle enabling of clock.
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*/
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#ifdef CONFIG_CPU_MONAHANS
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#define UART_CLK_BASE CKENA_21_BTUART
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#define UART_CLK_REG CKENA
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#define BTUART_INDEX 0
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#define FFUART_INDEX 1
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#define STUART_INDEX 2
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#elif CONFIG_CPU_PXA25X
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#define UART_CLK_BASE (1 << 4) /* HWUART */
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#define UART_CLK_REG CKEN
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#define HWUART_INDEX 0
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#define STUART_INDEX 1
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#define FFUART_INDEX 2
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#define BTUART_INDEX 3
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#else /* PXA27x */
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#define UART_CLK_BASE CKEN5_STUART
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#define UART_CLK_REG CKEN
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#define STUART_INDEX 0
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#define FFUART_INDEX 1
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#define BTUART_INDEX 2
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#endif
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/*
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* Only PXA250 has HWUART, to avoid poluting the code with more macros,
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* artificially introduce this.
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*/
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#ifndef CONFIG_CPU_PXA25X
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#define HWUART_INDEX 0xff
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#endif
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/*
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* struct pxa_serial_platdata - information about a PXA port
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*
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* @base: Uart port base register address
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* @port: Uart port index, for cpu with pinmux for uart / gpio
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* baudrtatre: Uart port baudrate
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*/
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struct pxa_serial_platdata {
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struct pxa_uart_regs *base;
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int port;
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int baudrate;
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};
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#endif /* __SERIAL_PXA_H */
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