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clk: nuvoton: Add support for NPCM750
Add clock controller driver for NPCM750 Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Jim Liu
Tom Rini
parent
84335544ea
commit
c7554574ff
@ -20,6 +20,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
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obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
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obj-$(CONFIG_ARCH_MESON) += meson/
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obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
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obj-$(CONFIG_ARCH_NPCM) += nuvoton/
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obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
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obj-$(CONFIG_ARCH_SOCFPGA) += altera/
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obj-$(CONFIG_ARCH_SUNXI) += sunxi/
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2
drivers/clk/nuvoton/Makefile
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2
drivers/clk/nuvoton/Makefile
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@ -0,0 +1,2 @@
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obj-$(CONFIG_ARCH_NPCM) += clk_npcm.o
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obj-$(CONFIG_ARCH_NPCM7xx) += clk_npcm7xx.o
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299
drivers/clk/nuvoton/clk_npcm.c
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299
drivers/clk/nuvoton/clk_npcm.c
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@ -0,0 +1,299 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2022 Nuvoton Technology Corp.
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*
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* Formula for calculating clock rate:
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* Fout = ((Fin / PRE_DIV) / div) / POST_DIV
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*/
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#include <div64.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#include <linux/log2.h>
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#include "clk_npcm.h"
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static int clkid_to_clksel(struct npcm_clk_select *selector, int id)
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{
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int i;
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for (i = 0; i < selector->num_parents; i++) {
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if (selector->parents[i].id == id)
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return selector->parents[i].clksel;
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}
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return -EINVAL;
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}
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static int clksel_to_clkid(struct npcm_clk_select *selector, int clksel)
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{
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int i;
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for (i = 0; i < selector->num_parents; i++) {
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if (selector->parents[i].clksel == clksel)
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return selector->parents[i].id;
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}
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return -EINVAL;
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}
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static struct npcm_clk_pll *npcm_clk_pll_get(struct npcm_clk_data *clk_data, int id)
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{
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struct npcm_clk_pll *pll = clk_data->clk_plls;
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int i;
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for (i = 0; i < clk_data->num_plls; i++) {
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if (pll->id == id)
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return pll;
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pll++;
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}
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return NULL;
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}
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static struct npcm_clk_select *npcm_clk_selector_get(struct npcm_clk_data *clk_data,
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int id)
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{
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struct npcm_clk_select *selector = clk_data->clk_selectors;
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int i;
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for (i = 0; i < clk_data->num_selectors; i++) {
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if (selector->id == id)
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return selector;
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selector++;
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}
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return NULL;
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}
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static struct npcm_clk_div *npcm_clk_divider_get(struct npcm_clk_data *clk_data,
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int id)
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{
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struct npcm_clk_div *divider = clk_data->clk_dividers;
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int i;
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for (i = 0; i < clk_data->num_dividers; i++) {
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if (divider->id == id)
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return divider;
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divider++;
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}
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return NULL;
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}
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static ulong npcm_clk_get_fin(struct clk *clk)
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{
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struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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struct npcm_clk_select *selector;
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struct clk parent;
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ulong parent_rate;
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u32 val, clksel;
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int ret;
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selector = npcm_clk_selector_get(priv->clk_data, clk->id);
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if (!selector)
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return 0;
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if (selector->flags & FIXED_PARENT) {
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clksel = 0;
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} else {
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val = readl(priv->base + selector->reg);
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clksel = (val & selector->mask) >> (ffs(selector->mask) - 1);
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}
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parent.id = clksel_to_clkid(selector, clksel);
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ret = clk_request(clk->dev, &parent);
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if (ret)
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return 0;
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parent_rate = clk_get_rate(&parent);
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debug("fin of clk%lu = %lu\n", clk->id, parent_rate);
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return parent_rate;
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}
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static u32 npcm_clk_get_div(struct clk *clk)
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{
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struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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struct npcm_clk_div *divider;
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u32 val, div;
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divider = npcm_clk_divider_get(priv->clk_data, clk->id);
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if (!divider)
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return 0;
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val = readl(priv->base + divider->reg);
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div = (val & divider->mask) >> (ffs(divider->mask) - 1);
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if (divider->flags & DIV_TYPE1)
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div = div + 1;
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else
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div = 1 << div;
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if (divider->flags & PRE_DIV2)
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div = div << 1;
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return div;
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}
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static u32 npcm_clk_set_div(struct clk *clk, u32 div)
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{
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struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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struct npcm_clk_div *divider;
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u32 val, clkdiv;
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divider = npcm_clk_divider_get(priv->clk_data, clk->id);
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if (!divider)
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return -EINVAL;
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if (divider->flags & PRE_DIV2)
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div = div >> 1;
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if (divider->flags & DIV_TYPE1)
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clkdiv = div - 1;
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else
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clkdiv = ilog2(div);
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val = readl(priv->base + divider->reg);
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val &= ~divider->mask;
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val |= (clkdiv << (ffs(divider->mask) - 1)) & divider->mask;
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writel(val, priv->base + divider->reg);
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return 0;
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}
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static ulong npcm_clk_get_fout(struct clk *clk)
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{
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ulong parent_rate;
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u32 div;
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parent_rate = npcm_clk_get_fin(clk);
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if (!parent_rate)
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return -EINVAL;
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div = npcm_clk_get_div(clk);
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if (!div)
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return -EINVAL;
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debug("fout of clk%lu = (%lu / %u)\n", clk->id, parent_rate, div);
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return (parent_rate / div);
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}
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static ulong npcm_clk_get_pll_fout(struct clk *clk)
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{
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struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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struct npcm_clk_pll *pll;
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struct clk parent;
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ulong parent_rate;
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ulong fbdv, indv, otdv1, otdv2;
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u32 val;
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u64 ret;
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pll = npcm_clk_pll_get(priv->clk_data, clk->id);
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if (!pll)
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return -ENODEV;
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parent.id = pll->parent_id;
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ret = clk_request(clk->dev, &parent);
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if (ret)
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return ret;
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parent_rate = clk_get_rate(&parent);
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val = readl(priv->base + pll->reg);
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indv = FIELD_GET(PLLCON_INDV, val);
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fbdv = FIELD_GET(PLLCON_FBDV, val);
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otdv1 = FIELD_GET(PLLCON_OTDV1, val);
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otdv2 = FIELD_GET(PLLCON_OTDV2, val);
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ret = (u64)parent_rate * fbdv;
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do_div(ret, indv * otdv1 * otdv2);
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if (pll->flags & POST_DIV2)
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do_div(ret, 2);
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debug("fout of pll(id %lu) = %llu\n", clk->id, ret);
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return ret;
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}
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static ulong npcm_clk_get_rate(struct clk *clk)
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{
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struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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struct npcm_clk_data *clk_data = priv->clk_data;
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struct clk refclk;
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int ret;
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debug("%s: id %lu\n", __func__, clk->id);
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if (clk->id == clk_data->refclk_id) {
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ret = clk_get_by_name(clk->dev, "refclk", &refclk);
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if (!ret)
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return clk_get_rate(&refclk);
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else
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return ret;
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}
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if (clk->id >= clk_data->pll0_id &&
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clk->id < clk_data->pll0_id + clk_data->num_plls)
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return npcm_clk_get_pll_fout(clk);
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else
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return npcm_clk_get_fout(clk);
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}
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static ulong npcm_clk_set_rate(struct clk *clk, ulong rate)
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{
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ulong parent_rate;
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u32 div;
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int ret;
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debug("%s: id %lu, rate %lu\n", __func__, clk->id, rate);
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parent_rate = npcm_clk_get_fin(clk);
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if (!parent_rate)
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return -EINVAL;
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div = DIV_ROUND_UP(parent_rate, rate);
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ret = npcm_clk_set_div(clk, div);
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if (ret)
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return ret;
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debug("%s: rate %lu, new rate (%lu / %u)\n", __func__, rate, parent_rate, div);
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return (parent_rate / div);
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}
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static int npcm_clk_set_parent(struct clk *clk, struct clk *parent)
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{
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struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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struct npcm_clk_select *selector;
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int clksel;
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u32 val;
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debug("%s: id %lu, parent %lu\n", __func__, clk->id, parent->id);
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selector = npcm_clk_selector_get(priv->clk_data, clk->id);
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if (!selector)
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return -EINVAL;
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clksel = clkid_to_clksel(selector, parent->id);
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if (clksel < 0)
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return -EINVAL;
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val = readl(priv->base + selector->reg);
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val &= ~selector->mask;
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val |= clksel << (ffs(selector->mask) - 1);
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writel(val, priv->base + selector->reg);
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return 0;
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}
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static int npcm_clk_request(struct clk *clk)
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{
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struct npcm_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id >= priv->num_clks)
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return -EINVAL;
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return 0;
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}
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const struct clk_ops npcm_clk_ops = {
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.get_rate = npcm_clk_get_rate,
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.set_rate = npcm_clk_set_rate,
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.set_parent = npcm_clk_set_parent,
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.request = npcm_clk_request,
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};
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105
drivers/clk/nuvoton/clk_npcm.h
Normal file
105
drivers/clk/nuvoton/clk_npcm.h
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@ -0,0 +1,105 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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#ifndef _CLK_NPCM_H_
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#define _CLK_NPCM_H_
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#include <clk-uclass.h>
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/* Register offsets */
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#define CLKSEL 0x04 /* clock source selection */
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#define CLKDIV1 0x08 /* clock divider 1 */
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#define CLKDIV2 0x2C /* clock divider 2 */
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#define CLKDIV3 0x58 /* clock divider 3 */
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#define PLLCON0 0x0C /* pll0 control */
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#define PLLCON1 0x10 /* pll1 control */
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#define PLLCON2 0x54 /* pll2 control */
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/* CLKSEL bit filed */
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#define NPCM7XX_CPUCKSEL GENMASK(1, 0)
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#define NPCM8XX_CPUCKSEL GENMASK(2, 0)
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#define SDCKSEL GENMASK(7, 6)
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#define UARTCKSEL GENMASK(9, 8)
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#define TIMCKSEL GENMASK(15, 14)
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/* CLKDIV1 bit filed */
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#define SPI3CKDIV GENMASK(10, 6)
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#define MMCCKDIV GENMASK(15, 11)
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#define UARTDIV1 GENMASK(20, 16)
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#define TIMCKDIV GENMASK(25, 21)
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#define CLK4DIV GENMASK(27, 26)
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/* CLKDIV2 bit filed */
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#define APB5CKDIV GENMASK(23, 22)
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#define APB2CKDIV GENMASK(27, 26)
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/* CLKDIV3 bit filed */
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#define SPIXCKDIV GENMASK(5, 1)
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#define SPI0CKDIV GENMASK(10, 6)
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#define UARTDIV2 GENMASK(15, 11)
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#define SPI1CKDIV GENMASK(23, 16)
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/* PLLCON bit filed */
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#define PLLCON_INDV GENMASK(5, 0)
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#define PLLCON_OTDV1 GENMASK(10, 8)
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#define PLLCON_OTDV2 GENMASK(15, 13)
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#define PLLCON_FBDV GENMASK(27, 16)
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/* Flags */
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#define DIV_TYPE1 BIT(0) /* div = clkdiv + 1 */
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#define DIV_TYPE2 BIT(1) /* div = 1 << clkdiv */
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#define PRE_DIV2 BIT(2) /* Pre divisor = 2 */
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#define POST_DIV2 BIT(3) /* Post divisor = 2 */
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#define FIXED_PARENT BIT(4) /* clock source is fixed */
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/* Parameters of PLL configuration */
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struct npcm_clk_pll {
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const int id;
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const int parent_id;
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u32 reg;
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u32 flags;
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};
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/* Parent clock id to clksel mapping */
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struct parent_data {
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int id;
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int clksel;
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};
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/* Parameters of parent selection */
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struct npcm_clk_select {
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const int id;
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const struct parent_data *parents;
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u32 reg;
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u32 mask;
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u8 num_parents;
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u32 flags;
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};
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/* Parameters of clock divider */
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struct npcm_clk_div {
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const int id;
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u32 reg;
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u32 mask;
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u32 flags;
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};
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struct npcm_clk_data {
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struct npcm_clk_pll *clk_plls;
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int num_plls;
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struct npcm_clk_select *clk_selectors;
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int num_selectors;
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struct npcm_clk_div *clk_dividers;
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int num_dividers;
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int refclk_id;
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int pll0_id;
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};
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struct npcm_clk_priv {
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void __iomem *base;
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struct npcm_clk_data *clk_data;
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int num_clks;
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};
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extern const struct clk_ops npcm_clk_ops;
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#endif
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95
drivers/clk/nuvoton/clk_npcm7xx.c
Normal file
95
drivers/clk/nuvoton/clk_npcm7xx.c
Normal file
@ -0,0 +1,95 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2021 Nuvoton Technology Corp.
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*/
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#include <dm.h>
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#include <dt-bindings/clock/nuvoton,npcm7xx-clock.h>
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#include "clk_npcm.h"
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/* Parent clock map */
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static const struct parent_data pll_parents[] = {
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{NPCM7XX_CLK_PLL0, 0},
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{NPCM7XX_CLK_PLL1, 1},
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{NPCM7XX_CLK_REFCLK, 2},
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{NPCM7XX_CLK_PLL2DIV2, 3}
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};
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static const struct parent_data cpuck_parents[] = {
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{NPCM7XX_CLK_PLL0, 0},
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{NPCM7XX_CLK_PLL1, 1},
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{NPCM7XX_CLK_REFCLK, 2},
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};
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static const struct parent_data apb_parent[] = {{NPCM7XX_CLK_AHB, 0}};
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static struct npcm_clk_pll npcm7xx_clk_plls[] = {
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{NPCM7XX_CLK_PLL0, NPCM7XX_CLK_REFCLK, PLLCON0, 0},
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{NPCM7XX_CLK_PLL1, NPCM7XX_CLK_REFCLK, PLLCON1, 0},
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{NPCM7XX_CLK_PLL2, NPCM7XX_CLK_REFCLK, PLLCON2, 0},
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{NPCM7XX_CLK_PLL2DIV2, NPCM7XX_CLK_REFCLK, PLLCON2, POST_DIV2}
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};
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static struct npcm_clk_select npcm7xx_clk_selectors[] = {
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{NPCM7XX_CLK_AHB, cpuck_parents, CLKSEL, NPCM7XX_CPUCKSEL, 3, 0},
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{NPCM7XX_CLK_APB2, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM7XX_CLK_APB5, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM7XX_CLK_SPI0, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM7XX_CLK_SPI3, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM7XX_CLK_SPIX, apb_parent, 0, 0, 1, FIXED_PARENT},
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{NPCM7XX_CLK_UART, pll_parents, CLKSEL, UARTCKSEL, 4, 0},
|
||||
{NPCM7XX_CLK_TIMER, pll_parents, CLKSEL, TIMCKSEL, 4, 0},
|
||||
{NPCM7XX_CLK_SDHC, pll_parents, CLKSEL, SDCKSEL, 4, 0}
|
||||
};
|
||||
|
||||
static struct npcm_clk_div npcm7xx_clk_dividers[] = {
|
||||
{NPCM7XX_CLK_AHB, CLKDIV1, CLK4DIV, DIV_TYPE1 | PRE_DIV2},
|
||||
{NPCM7XX_CLK_APB2, CLKDIV2, APB2CKDIV, DIV_TYPE2},
|
||||
{NPCM7XX_CLK_APB5, CLKDIV2, APB5CKDIV, DIV_TYPE2},
|
||||
{NPCM7XX_CLK_SPI0, CLKDIV3, SPI0CKDIV, DIV_TYPE1},
|
||||
{NPCM7XX_CLK_SPI3, CLKDIV1, SPI3CKDIV, DIV_TYPE1},
|
||||
{NPCM7XX_CLK_SPIX, CLKDIV3, SPIXCKDIV, DIV_TYPE1},
|
||||
{NPCM7XX_CLK_UART, CLKDIV1, UARTDIV1, DIV_TYPE1},
|
||||
{NPCM7XX_CLK_TIMER, CLKDIV1, TIMCKDIV, DIV_TYPE2},
|
||||
{NPCM7XX_CLK_SDHC, CLKDIV1, MMCCKDIV, DIV_TYPE1}
|
||||
};
|
||||
|
||||
static struct npcm_clk_data npcm7xx_clk_data = {
|
||||
.clk_plls = npcm7xx_clk_plls,
|
||||
.num_plls = ARRAY_SIZE(npcm7xx_clk_plls),
|
||||
.clk_selectors = npcm7xx_clk_selectors,
|
||||
.num_selectors = ARRAY_SIZE(npcm7xx_clk_selectors),
|
||||
.clk_dividers = npcm7xx_clk_dividers,
|
||||
.num_dividers = ARRAY_SIZE(npcm7xx_clk_dividers),
|
||||
.refclk_id = NPCM7XX_CLK_REFCLK,
|
||||
.pll0_id = NPCM7XX_CLK_PLL0,
|
||||
};
|
||||
|
||||
static int npcm7xx_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct npcm_clk_priv *priv = dev_get_priv(dev);
|
||||
|
||||
priv->base = dev_read_addr_ptr(dev);
|
||||
if (!priv->base)
|
||||
return -EINVAL;
|
||||
|
||||
priv->clk_data = &npcm7xx_clk_data;
|
||||
priv->num_clks = NPCM7XX_NUM_CLOCKS;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id npcm7xx_clk_ids[] = {
|
||||
{ .compatible = "nuvoton,npcm750-clk" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(clk_npcm) = {
|
||||
.name = "clk_npcm",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = npcm7xx_clk_ids,
|
||||
.ops = &npcm_clk_ops,
|
||||
.priv_auto = sizeof(struct npcm_clk_priv),
|
||||
.probe = npcm7xx_clk_probe,
|
||||
.flags = DM_FLAG_PRE_RELOC,
|
||||
};
|
||||
46
include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
Normal file
46
include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
Normal file
@ -0,0 +1,46 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Nuvoton NPCM7xx Clock Generator binding
|
||||
* clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
|
||||
*
|
||||
* Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_NPCM7XX_H
|
||||
#define __DT_BINDINGS_CLOCK_NPCM7XX_H
|
||||
|
||||
#define NPCM7XX_CLK_CPU 0
|
||||
#define NPCM7XX_CLK_GFX_PIXEL 1
|
||||
#define NPCM7XX_CLK_MC 2
|
||||
#define NPCM7XX_CLK_ADC 3
|
||||
#define NPCM7XX_CLK_AHB 4
|
||||
#define NPCM7XX_CLK_TIMER 5
|
||||
#define NPCM7XX_CLK_UART 6
|
||||
#define NPCM7XX_CLK_MMC 7
|
||||
#define NPCM7XX_CLK_SPI3 8
|
||||
#define NPCM7XX_CLK_PCI 9
|
||||
#define NPCM7XX_CLK_AXI 10
|
||||
#define NPCM7XX_CLK_APB4 11
|
||||
#define NPCM7XX_CLK_APB3 12
|
||||
#define NPCM7XX_CLK_APB2 13
|
||||
#define NPCM7XX_CLK_APB1 14
|
||||
#define NPCM7XX_CLK_APB5 15
|
||||
#define NPCM7XX_CLK_CLKOUT 16
|
||||
#define NPCM7XX_CLK_GFX 17
|
||||
#define NPCM7XX_CLK_SU 18
|
||||
#define NPCM7XX_CLK_SU48 19
|
||||
#define NPCM7XX_CLK_SDHC 20
|
||||
#define NPCM7XX_CLK_SPI0 21
|
||||
#define NPCM7XX_CLK_SPIX 22
|
||||
#define NPCM7XX_CLK_REFCLK 23
|
||||
#define NPCM7XX_CLK_SYSBYPCK 24
|
||||
#define NPCM7XX_CLK_MCBYPCK 25
|
||||
#define NPCM7XX_CLK_PLL0 26
|
||||
#define NPCM7XX_CLK_PLL1 27
|
||||
#define NPCM7XX_CLK_PLL2 28
|
||||
#define NPCM7XX_CLK_PLL2DIV2 29
|
||||
#define NPCM7XX_NUM_CLOCKS (NPCM7XX_CLK_PLL2DIV2 + 1)
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user