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arm64: ls1043a: Remove the workaround of erratum A-009929
The workaround has been implemented in PBI phase, so remove the duplicated implementation from U-Boot. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -68,7 +68,6 @@ config ARCH_LS1043A
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select SYS_FSL_ERRATUM_A009660 if !TFABOOT
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select SYS_FSL_ERRATUM_A009663 if !TFABOOT
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select SYS_FSL_ERRATUM_A009798
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select SYS_FSL_ERRATUM_A009929
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select SYS_FSL_ERRATUM_A009942 if !TFABOOT
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010539
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@ -592,9 +591,6 @@ config SYS_FSL_ERRATUM_A009635
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config SYS_FSL_ERRATUM_A009660
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bool
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config SYS_FSL_ERRATUM_A009929
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bool
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config SYS_FSL_ERRATUM_A050382
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bool
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@ -445,20 +445,6 @@ int get_core_volt_from_fuse(void)
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}
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#elif defined(CONFIG_FSL_LSCH2)
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static void erratum_a009929(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009929
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struct ccsr_gur *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
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u32 __iomem *dcsr_cop_ccp = (void *)CONFIG_SYS_DCSR_COP_CCP_ADDR;
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u32 rstrqmr1 = gur_in32(&gur->rstrqmr1);
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rstrqmr1 |= 0x00000400;
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gur_out32(&gur->rstrqmr1, rstrqmr1);
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writel(0x01000000, dcsr_cop_ccp);
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#endif
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}
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/*
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* This erratum requires setting a value to eddrtqcr1 to optimal
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* the DDR performance. The eddrtqcr1 register is in SCFG space
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@ -724,7 +710,6 @@ void fsl_lsch2_early_init_f(void)
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#endif
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/* Erratum */
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erratum_a008850_early(); /* part 1 of 2 */
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erratum_a009929();
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erratum_a009660();
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erratum_a010539();
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erratum_a009008();
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