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Merge branch 'master' of git://git.denx.de/u-boot-i2c

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This commit is contained in:
Tom Rini 2016-07-26 08:29:30 -04:00
commit c3c9fd31ba
16 changed files with 900 additions and 362 deletions
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6
arch/arm/include/asm/arch-omap4/i2c.h
View File

@ -14,9 +14,9 @@ struct i2c {
unsigned short revnb_lo; /* 0x00 */
unsigned short res1;
unsigned short revnb_hi; /* 0x04 */
unsigned short res2[13];
unsigned short sysc; /* 0x20 */
unsigned short res3;
unsigned short res2[5];
unsigned short sysc; /* 0x10 */
unsigned short res3[9];
unsigned short irqstatus_raw; /* 0x24 */
unsigned short res4;
unsigned short stat; /* 0x28 */

6
arch/arm/include/asm/arch-omap5/i2c.h
View File

@ -14,9 +14,9 @@ struct i2c {
unsigned short revnb_lo; /* 0x00 */
unsigned short res1;
unsigned short revnb_hi; /* 0x04 */
unsigned short res2[13];
unsigned short sysc; /* 0x20 */
unsigned short res3;
unsigned short res2[5];
unsigned short sysc; /* 0x10 */
unsigned short res3[9];
unsigned short irqstatus_raw; /* 0x24 */
unsigned short res4;
unsigned short stat; /* 0x28 */

1
configs/am335x_boneblack_vboot_defconfig
View File

@ -49,3 +49,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_DM_I2C=y

1
configs/am335x_evm_defconfig
View File

@ -49,3 +49,4 @@ CONFIG_FIT=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_LIST="am335x-evm am335x-bone am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2"
CONFIG_DM_I2C=y

1
configs/am43xx_evm_defconfig
View File

@ -54,3 +54,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_SPL_OF_LIBFDT=y
CONFIG_DM_I2C=y

1
configs/am43xx_hs_evm_defconfig
View File

@ -58,3 +58,4 @@ CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0403
CONFIG_G_DNL_PRODUCT_NUM=0xbd00
CONFIG_SPL_OF_LIBFDT=y
CONFIG_DM_I2C=y

1
configs/am57xx_evm_defconfig
View File

@ -40,3 +40,4 @@ CONFIG_FIT=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_LIST="am57xx-beagle-x15 am572x-idk"
CONFIG_DM_I2C=y

1
configs/am57xx_hs_evm_defconfig
View File

@ -42,3 +42,4 @@ CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_LIST="am57xx-beagle-x15"
CONFIG_DM_I2C=y

1
configs/dra7xx_evm_defconfig
View File

@ -57,3 +57,4 @@ CONFIG_FIT=y
CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_LIST="dra7-evm dra72-evm"
CONFIG_DM_I2C=y

1
configs/dra7xx_hs_evm_defconfig
View File

@ -60,3 +60,4 @@ CONFIG_SPL_OF_LIBFDT=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_OF_LIST="dra7-evm dra72-evm"
CONFIG_DM_I2C=y

7
drivers/i2c/Kconfig
View File

@ -154,6 +154,13 @@ config SYS_I2C_UNIPHIER_F
Support for UniPhier FIFO-builtin I2C controller driver.
This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
config SYS_I2C_MVTWSI
bool "Marvell I2C driver"
depends on DM_I2C
help
Support for Marvell I2C controllers as used on the orion5x and
kirkwood SoC families.
source "drivers/i2c/muxes/Kconfig"
endmenu

14
drivers/i2c/i2c-uclass.c
View File

@ -467,6 +467,7 @@ int i2c_deblock(struct udevice *bus)
return ops->deblock(bus);
}
#if CONFIG_IS_ENABLED(OF_CONTROL)
int i2c_chip_ofdata_to_platdata(const void *blob, int node,
struct dm_i2c_chip *chip)
{
@ -482,31 +483,44 @@ int i2c_chip_ofdata_to_platdata(const void *blob, int node,
return 0;
}
#endif
static int i2c_post_probe(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
struct dm_i2c_bus *i2c = dev_get_uclass_priv(dev);
i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
"clock-frequency", 100000);
return dm_i2c_set_bus_speed(dev, i2c->speed_hz);
#else
return 0;
#endif
}
static int i2c_post_bind(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
/* Scan the bus for devices */
return dm_scan_fdt_node(dev, gd->fdt_blob, dev->of_offset, false);
#else
return 0;
#endif
}
static int i2c_child_post_bind(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_CONTROL)
struct dm_i2c_chip *plat = dev_get_parent_platdata(dev);
if (dev->of_offset == -1)
return 0;
return i2c_chip_ofdata_to_platdata(gd->fdt_blob, dev->of_offset, plat);
#else
return 0;
#endif
}
UCLASS_DRIVER(i2c) = {

781
drivers/i2c/mvtwsi.c
View File

@ -12,12 +12,19 @@
#include <i2c.h>
#include <asm/errno.h>
#include <asm/io.h>
#include <linux/compat.h>
#ifdef CONFIG_DM_I2C
#include <dm.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* include a file that will provide CONFIG_I2C_MVTWSI_BASE*
* and possibly other settings
* Include a file that will provide CONFIG_I2C_MVTWSI_BASE*, and possibly other
* settings
*/
#ifndef CONFIG_DM_I2C
#if defined(CONFIG_ORION5X)
#include <asm/arch/orion5x.h>
#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARCH_MVEBU))
@ -27,6 +34,7 @@
#else
#error Driver mvtwsi not supported by SoC or board
#endif
#endif /* CONFIG_DM_I2C */
/*
* TWSI register structure
@ -51,8 +59,8 @@ struct mvtwsi_registers {
u32 data;
u32 control;
union {
u32 status; /* when reading */
u32 baudrate; /* when writing */
u32 status; /* When reading */
u32 baudrate; /* When writing */
};
u32 xtnd_slave_addr;
u32 reserved[2];
@ -61,20 +69,43 @@ struct mvtwsi_registers {
#endif
#ifdef CONFIG_DM_I2C
struct mvtwsi_i2c_dev {
/* TWSI Register base for the device */
struct mvtwsi_registers *base;
/* Number of the device (determined from cell-index property) */
int index;
/* The I2C slave address for the device */
u8 slaveadd;
/* The configured I2C speed in Hz */
uint speed;
/* The current length of a clock period (depending on speed) */
uint tick;
};
#endif /* CONFIG_DM_I2C */
/*
* Control register fields
* enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
* register
*/
#define MVTWSI_CONTROL_ACK 0x00000004
#define MVTWSI_CONTROL_IFLG 0x00000008
#define MVTWSI_CONTROL_STOP 0x00000010
#define MVTWSI_CONTROL_START 0x00000020
#define MVTWSI_CONTROL_TWSIEN 0x00000040
#define MVTWSI_CONTROL_INTEN 0x00000080
enum mvtwsi_ctrl_register_fields {
/* Acknowledge bit */
MVTWSI_CONTROL_ACK = 0x00000004,
/* Interrupt flag */
MVTWSI_CONTROL_IFLG = 0x00000008,
/* Stop bit */
MVTWSI_CONTROL_STOP = 0x00000010,
/* Start bit */
MVTWSI_CONTROL_START = 0x00000020,
/* I2C enable */
MVTWSI_CONTROL_TWSIEN = 0x00000040,
/* Interrupt enable */
MVTWSI_CONTROL_INTEN = 0x00000080,
};
/*
* On sun6i and newer IFLG is a write-clear bit which is cleared by writing 1,
* on other platforms it is a normal r/w bit which is cleared by writing 0.
* On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
* on other platforms, it is a normal r/w bit, which is cleared by writing 0.
*/
#ifdef CONFIG_SUNXI_GEN_SUN6I
@ -84,53 +115,95 @@ struct mvtwsi_registers {
#endif
/*
* Status register values -- only those expected in normal master
* operation on non-10-bit-address devices; whatever status we don't
* expect in nominal conditions (bus errors, arbitration losses,
* missing ACKs...) we just pass back to the caller as an error
* enum mvstwsi_status_values - Possible values of I2C controller's status
* register
*
* Only those statuses expected in normal master operation on
* non-10-bit-address devices are specified.
*
* Every status that's unexpected during normal operation (bus errors,
* arbitration losses, missing ACKs...) is passed back to the caller as an error
* code.
*/
#define MVTWSI_STATUS_START 0x08
#define MVTWSI_STATUS_REPEATED_START 0x10
#define MVTWSI_STATUS_ADDR_W_ACK 0x18
#define MVTWSI_STATUS_DATA_W_ACK 0x28
#define MVTWSI_STATUS_ADDR_R_ACK 0x40
#define MVTWSI_STATUS_ADDR_R_NAK 0x48
#define MVTWSI_STATUS_DATA_R_ACK 0x50
#define MVTWSI_STATUS_DATA_R_NAK 0x58
#define MVTWSI_STATUS_IDLE 0xF8
enum mvstwsi_status_values {
/* START condition transmitted */
MVTWSI_STATUS_START = 0x08,
/* Repeated START condition transmitted */
MVTWSI_STATUS_REPEATED_START = 0x10,
/* Address + write bit transmitted, ACK received */
MVTWSI_STATUS_ADDR_W_ACK = 0x18,
/* Data transmitted, ACK received */
MVTWSI_STATUS_DATA_W_ACK = 0x28,
/* Address + read bit transmitted, ACK received */
MVTWSI_STATUS_ADDR_R_ACK = 0x40,
/* Address + read bit transmitted, ACK not received */
MVTWSI_STATUS_ADDR_R_NAK = 0x48,
/* Data received, ACK transmitted */
MVTWSI_STATUS_DATA_R_ACK = 0x50,
/* Data received, ACK not transmitted */
MVTWSI_STATUS_DATA_R_NAK = 0x58,
/* No relevant status */
MVTWSI_STATUS_IDLE = 0xF8,
};
/*
* MVTWSI controller base
* enum mvstwsi_ack_flags - Determine whether a read byte should be
* acknowledged or not.
*/
enum mvtwsi_ack_flags {
/* Send NAK after received byte */
MVTWSI_READ_NAK = 0,
/* Send ACK after received byte */
MVTWSI_READ_ACK = 1,
};
/*
* calc_tick() - Calculate the duration of a clock cycle from the I2C speed
*
* @speed: The speed in Hz to calculate the clock cycle duration for.
* @return The duration of a clock cycle in ns.
*/
inline uint calc_tick(uint speed)
{
/* One tick = the duration of a period at the specified speed in ns (we
* add 100 ns to be on the safe side) */
return (1000000000u / speed) + 100;
}
#ifndef CONFIG_DM_I2C
/*
* twsi_get_base() - Get controller register base for specified adapter
*
* @adap: Adapter to get the register base for.
* @return Register base for the specified adapter.
*/
static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
{
switch (adap->hwadapnr) {
#ifdef CONFIG_I2C_MVTWSI_BASE0
case 0:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0;
return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE0;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE1
case 1:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1;
return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE1;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE2
case 2:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2;
return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE2;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE3
case 3:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3;
return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE3;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE4
case 4:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE4;
#endif
#ifdef CONFIG_I2C_MVTWSI_BASE5
case 5:
return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE5;
return (struct mvtwsi_registers *)CONFIG_I2C_MVTWSI_BASE5;
#endif
default:
printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
@ -139,30 +212,48 @@ static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
return NULL;
}
#endif
/*
* Returned statuses are 0 for success and nonzero otherwise.
* Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
* Thus to ease debugging, the return status contains some debug info:
* - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'.
* - bits 23..16 are the last value of the control register.
* - bits 15..8 are the last value of the status register.
* - bits 7..0 are the expected value of the status register.
* enum mvtwsi_error_class - types of I2C errors
*/
#define MVTWSI_ERROR_WRONG_STATUS 0x01
#define MVTWSI_ERROR_TIMEOUT 0x02
#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \
((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF))
enum mvtwsi_error_class {
/* The controller returned a different status than expected */
MVTWSI_ERROR_WRONG_STATUS = 0x01,
/* The controller timed out */
MVTWSI_ERROR_TIMEOUT = 0x02,
};
/*
* Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
* return 0 (ok) or return 'wrong status'.
* mvtwsi_error() - Build I2C return code from error information
*
* For debugging purposes, this function packs some information of an occurred
* error into a return code. These error codes are returned from I2C API
* functions (i2c_{read,write}, dm_i2c_{read,write}, etc.).
*
* @ec: The error class of the error (enum mvtwsi_error_class).
* @lc: The last value of the control register.
* @ls: The last value of the status register.
* @es: The expected value of the status register.
* @return The generated error code.
*/
static int twsi_wait(struct i2c_adapter *adap, int expected_status)
inline uint mvtwsi_error(uint ec, uint lc, uint ls, uint es)
{
return ((ec << 24) & 0xFF000000)
| ((lc << 16) & 0x00FF0000)
| ((ls << 8) & 0x0000FF00)
| (es & 0xFF);
}
/*
* twsi_wait() - Wait for I2C bus interrupt flag and check status, or time out.
*
* @return Zero if status is as expected, or a non-zero code if either a time
* out occurred, or the status was not the expected one.
*/
static int twsi_wait(struct mvtwsi_registers *twsi, int expected_status,
uint tick)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
int control, status;
int timeout = 1000;
@ -173,105 +264,140 @@ static int twsi_wait(struct i2c_adapter *adap, int expected_status)
if (status == expected_status)
return 0;
else
return MVTWSI_ERROR(
return mvtwsi_error(
MVTWSI_ERROR_WRONG_STATUS,
control, status, expected_status);
}
udelay(10); /* one clock cycle at 100 kHz */
ndelay(tick); /* One clock cycle */
} while (timeout--);
status = readl(&twsi->status);
return MVTWSI_ERROR(
MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
return mvtwsi_error(MVTWSI_ERROR_TIMEOUT, control, status,
expected_status);
}
/*
* Assert the START condition, either in a single I2C transaction
* or inside back-to-back ones (repeated starts).
* twsi_start() - Assert a START condition on the bus.
*
* This function is used in both single I2C transactions and inside
* back-to-back transactions (repeated starts).
*
* @twsi: The MVTWSI register structure to use.
* @expected_status: The I2C bus status expected to be asserted after the
* operation completion.
* @tick: The duration of a clock cycle at the current I2C speed.
* @return Zero if status is as expected, or a non-zero code if either a time
* out occurred or the status was not the expected one.
*/
static int twsi_start(struct i2c_adapter *adap, int expected_status, u8 *flags)
static int twsi_start(struct mvtwsi_registers *twsi, int expected_status,
uint tick)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
/* globally set TWSIEN in case it was not */
*flags |= MVTWSI_CONTROL_TWSIEN;
/* assert START */
writel(*flags | MVTWSI_CONTROL_START |
MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to process START */
return twsi_wait(adap, expected_status);
/* Assert START */
writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_START |
MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* Wait for controller to process START */
return twsi_wait(twsi, expected_status, tick);
}
/*
* Send a byte (i2c address or data).
* twsi_send() - Send a byte on the I2C bus.
*
* The byte may be part of an address byte or data.
*
* @twsi: The MVTWSI register structure to use.
* @byte: The byte to send.
* @expected_status: The I2C bus status expected to be asserted after the
* operation completion.
* @tick: The duration of a clock cycle at the current I2C speed.
* @return Zero if status is as expected, or a non-zero code if either a time
* out occurred or the status was not the expected one.
*/
static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status,
u8 *flags)
static int twsi_send(struct mvtwsi_registers *twsi, u8 byte,
int expected_status, uint tick)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
/* put byte in data register for sending */
/* Write byte to data register for sending */
writel(byte, &twsi->data);
/* clear any pending interrupt -- that'll cause sending */
writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to receive byte and check ACK */
return twsi_wait(adap, expected_status);
/* Clear any pending interrupt -- that will cause sending */
writel(MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_CLEAR_IFLG,
&twsi->control);
/* Wait for controller to receive byte, and check ACK */
return twsi_wait(twsi, expected_status, tick);
}
/*
* Receive a byte.
* Global mvtwsi_control_flags variable says if we should ack or nak.
* twsi_recv() - Receive a byte on the I2C bus.
*
* The static variable mvtwsi_control_flags controls whether we ack or nak.
*
* @twsi: The MVTWSI register structure to use.
* @byte: The byte to send.
* @ack_flag: Flag that determines whether the received byte should
* be acknowledged by the controller or not (sent ACK/NAK).
* @tick: The duration of a clock cycle at the current I2C speed.
* @return Zero if status is as expected, or a non-zero code if either a time
* out occurred or the status was not the expected one.
*/
static int twsi_recv(struct i2c_adapter *adap, u8 *byte, u8 *flags)
static int twsi_recv(struct mvtwsi_registers *twsi, u8 *byte, int ack_flag,
uint tick)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
int expected_status, status;
int expected_status, status, control;
/* compute expected status based on ACK bit in global control flags */
if (*flags & MVTWSI_CONTROL_ACK)
expected_status = MVTWSI_STATUS_DATA_R_ACK;
else
expected_status = MVTWSI_STATUS_DATA_R_NAK;
/* acknowledge *previous state* and launch receive */
writel(*flags | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for controller to receive byte and assert ACK or NAK */
status = twsi_wait(adap, expected_status);
/* if we did receive expected byte then store it */
/* Compute expected status based on passed ACK flag */
expected_status = ack_flag ? MVTWSI_STATUS_DATA_R_ACK :
MVTWSI_STATUS_DATA_R_NAK;
/* Acknowledge *previous state*, and launch receive */
control = MVTWSI_CONTROL_TWSIEN;
control |= ack_flag == MVTWSI_READ_ACK ? MVTWSI_CONTROL_ACK : 0;
writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* Wait for controller to receive byte, and assert ACK or NAK */
status = twsi_wait(twsi, expected_status, tick);
/* If we did receive the expected byte, store it */
if (status == 0)
*byte = readl(&twsi->data);
/* return status */
return status;
}
/*
* Assert the STOP condition.
* This is also used to force the bus back in idle (SDA=SCL=1).
* twsi_stop() - Assert a STOP condition on the bus.
*
* This function is also used to force the bus back to idle state (SDA =
* SCL = 1).
*
* @twsi: The MVTWSI register structure to use.
* @tick: The duration of a clock cycle at the current I2C speed.
* @return Zero if the operation succeeded, or a non-zero code if a time out
* occurred.
*/
static int twsi_stop(struct i2c_adapter *adap, int status)
static int twsi_stop(struct mvtwsi_registers *twsi, uint tick)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
int control, stop_status;
int status = 0;
int timeout = 1000;
/* assert STOP */
/* Assert STOP */
control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
writel(control | MVTWSI_CONTROL_CLEAR_IFLG, &twsi->control);
/* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
/* Wait for IDLE; IFLG won't rise, so we can't use twsi_wait() */
do {
stop_status = readl(&twsi->status);
if (stop_status == MVTWSI_STATUS_IDLE)
break;
udelay(10); /* one clock cycle at 100 kHz */
ndelay(tick); /* One clock cycle */
} while (timeout--);
control = readl(&twsi->control);
if (stop_status != MVTWSI_STATUS_IDLE)
if (status == 0)
status = MVTWSI_ERROR(
MVTWSI_ERROR_TIMEOUT,
control, status, MVTWSI_STATUS_IDLE);
status = mvtwsi_error(MVTWSI_ERROR_TIMEOUT,
control, status, MVTWSI_STATUS_IDLE);
return status;
}
static unsigned int twsi_calc_freq(const int n, const int m)
/*
* twsi_calc_freq() - Compute I2C frequency depending on m and n parameters.
*
* @n: Parameter 'n' for the frequency calculation algorithm.
* @m: Parameter 'm' for the frequency calculation algorithm.
* @return The I2C frequency corresponding to the passed m and n parameters.
*/
static uint twsi_calc_freq(const int n, const int m)
{
#ifdef CONFIG_SUNXI
return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
@ -281,176 +407,303 @@ static unsigned int twsi_calc_freq(const int n, const int m)
}
/*
* Reset controller.
* Controller reset also resets the baud rate and slave address, so
* they must be re-established afterwards.
* twsi_reset() - Reset the I2C controller.
*
* Resetting the controller also resets the baud rate and slave address, hence
* they must be re-established after the reset.
*
* @twsi: The MVTWSI register structure to use.
*/
static void twsi_reset(struct i2c_adapter *adap)
static void twsi_reset(struct mvtwsi_registers *twsi)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
/* reset controller */
/* Reset controller */
writel(0, &twsi->soft_reset);
/* wait 2 ms -- this is what the Marvell LSP does */
/* Wait 2 ms -- this is what the Marvell LSP does */
udelay(20000);
}
/*
* I2C init called by cmd_i2c when doing 'i2c reset'.
* Sets baud to the highest possible value not exceeding requested one.
* __twsi_i2c_set_bus_speed() - Set the speed of the I2C controller.
*
* This function sets baud rate to the highest possible value that does not
* exceed the requested rate.
*
* @twsi: The MVTWSI register structure to use.
* @requested_speed: The desired frequency the controller should run at
* in Hz.
* @return The actual frequency the controller was configured to.
*/
static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
unsigned int requested_speed)
static uint __twsi_i2c_set_bus_speed(struct mvtwsi_registers *twsi,
uint requested_speed)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
unsigned int tmp_speed, highest_speed, n, m;
unsigned int baud = 0x44; /* baudrate at controller reset */
uint tmp_speed, highest_speed, n, m;
uint baud = 0x44; /* Baud rate after controller reset */
/* use actual speed to collect progressively higher values */
highest_speed = 0;
/* compute m, n setting for highest speed not above requested speed */
/* Successively try m, n combinations, and use the combination
* resulting in the largest speed that's not above the requested
* speed */
for (n = 0; n < 8; n++) {
for (m = 0; m < 16; m++) {
tmp_speed = twsi_calc_freq(n, m);
if ((tmp_speed <= requested_speed)
&& (tmp_speed > highest_speed)) {
if ((tmp_speed <= requested_speed) &&
(tmp_speed > highest_speed)) {
highest_speed = tmp_speed;
baud = (m << 3) | n;
}
}
}
writel(baud, &twsi->baudrate);
return 0;
}
static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
/* reset controller */
twsi_reset(adap);
/* set speed */
twsi_i2c_set_bus_speed(adap, speed);
/* set slave address even though we don't use it */
writel(slaveadd, &twsi->slave_address);
writel(0, &twsi->xtnd_slave_addr);
/* assert STOP but don't care for the result */
(void) twsi_stop(adap, 0);
/* Wait for controller for one tick */
#ifdef CONFIG_DM_I2C
ndelay(calc_tick(highest_speed));
#else
ndelay(10000);
#endif
return highest_speed;
}
/*
* Begin I2C transaction with expected start status, at given address.
* Common to i2c_probe, i2c_read and i2c_write.
* Expected address status will derive from direction bit (bit 0) in addr.
* __twsi_i2c_init() - Initialize the I2C controller.
*
* @twsi: The MVTWSI register structure to use.
* @speed: The initial frequency the controller should run at
* in Hz.
* @slaveadd: The I2C address to be set for the I2C master.
* @actual_speed: A output parameter that receives the actual frequency
* in Hz the controller was set to by the function.
* @return Zero if the operation succeeded, or a non-zero code if a time out
* occurred.
*/
static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
u8 addr, u8 *flags)
static void __twsi_i2c_init(struct mvtwsi_registers *twsi, int speed,
int slaveadd, uint *actual_speed)
{
/* Reset controller */
twsi_reset(twsi);
/* Set speed */
*actual_speed = __twsi_i2c_set_bus_speed(twsi, speed);
/* Set slave address; even though we don't use it */
writel(slaveadd, &twsi->slave_address);
writel(0, &twsi->xtnd_slave_addr);
/* Assert STOP, but don't care for the result */
#ifdef CONFIG_DM_I2C
(void) twsi_stop(twsi, calc_tick(*actual_speed));
#else
(void) twsi_stop(twsi, 10000);
#endif
}
/*
* i2c_begin() - Start a I2C transaction.
*
* Begin a I2C transaction with a given expected start status and chip address.
* A START is asserted, and the address byte is sent to the I2C controller. The
* expected address status will be derived from the direction bit (bit 0) of
* the address byte.
*
* @twsi: The MVTWSI register structure to use.
* @expected_start_status: The I2C status the controller is expected to
* assert after the address byte was sent.
* @addr: The address byte to be sent.
* @tick: The duration of a clock cycle at the current
* I2C speed.
* @return Zero if the operation succeeded, or a non-zero code if a time out or
* unexpected I2C status occurred.
*/
static int i2c_begin(struct mvtwsi_registers *twsi, int expected_start_status,
u8 addr, uint tick)
{
int status, expected_addr_status;
/* compute expected address status from direction bit in addr */
if (addr & 1) /* reading */
/* Compute the expected address status from the direction bit in
* the address byte */
if (addr & 1) /* Reading */
expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
else /* writing */
else /* Writing */
expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
/* assert START */
status = twsi_start(adap, expected_start_status, flags);
/* send out the address if the start went well */
/* Assert START */
status = twsi_start(twsi, expected_start_status, tick);
/* Send out the address if the start went well */
if (status == 0)
status = twsi_send(adap, addr, expected_addr_status,
flags);
/* return ok or status of first failure to caller */
status = twsi_send(twsi, addr, expected_addr_status, tick);
/* Return 0, or the status of the first failure */
return status;
}
/*
* I2C probe called by cmd_i2c when doing 'i2c probe'.
* Begin read, nak data byte, end.
* __twsi_i2c_probe_chip() - Probe the given I2C chip address.
*
* This function begins a I2C read transaction, does a dummy read and NAKs; if
* the procedure succeeds, the chip is considered to be present.
*
* @twsi: The MVTWSI register structure to use.
* @chip: The chip address to probe.
* @tick: The duration of a clock cycle at the current I2C speed.
* @return Zero if the operation succeeded, or a non-zero code if a time out or
* unexpected I2C status occurred.
*/
static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
static int __twsi_i2c_probe_chip(struct mvtwsi_registers *twsi, uchar chip,
uint tick)
{
u8 dummy_byte;
u8 flags = 0;
int status;
/* begin i2c read */
status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1, &flags);
/* dummy read was accepted: receive byte but NAK it. */
/* Begin i2c read */
status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1) | 1, tick);
/* Dummy read was accepted: receive byte, but NAK it. */
if (status == 0)
status = twsi_recv(adap, &dummy_byte, &flags);
status = twsi_recv(twsi, &dummy_byte, MVTWSI_READ_NAK, tick);
/* Stop transaction */
twsi_stop(adap, 0);
/* return 0 or status of first failure */
twsi_stop(twsi, tick);
/* Return 0, or the status of the first failure */
return status;
}
/*
* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
* Begin write, send address byte(s), begin read, receive data bytes, end.
* __twsi_i2c_read() - Read data from a I2C chip.
*
* NOTE: some EEPROMS want a stop right before the second start, while
* some will choke if it is there. Deciding which we should do is eeprom
* stuff, not i2c, but at the moment the APIs won't let us put it in
* cmd_eeprom, so we have to choose here, and for the moment that'll be
* a repeated start without a preceding stop.
* This function begins a I2C write transaction, and transmits the address
* bytes; then begins a I2C read transaction, and receives the data bytes.
*
* NOTE: Some devices want a stop right before the second start, while some
* will choke if it is there. Since deciding this is not yet supported in
* higher level APIs, we need to make a decision here, and for the moment that
* will be a repeated start without a preceding stop.
*
* @twsi: The MVTWSI register structure to use.
* @chip: The chip address to read from.
* @addr: The address bytes to send.
* @alen: The length of the address bytes in bytes.
* @data: The buffer to receive the data read from the chip (has to have
* a size of at least 'length' bytes).
* @length: The amount of data to be read from the chip in bytes.
* @tick: The duration of a clock cycle at the current I2C speed.
* @return Zero if the operation succeeded, or a non-zero code if a time out or
* unexpected I2C status occurred.
*/
static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *data, int length)
static int __twsi_i2c_read(struct mvtwsi_registers *twsi, uchar chip,
u8 *addr, int alen, uchar *data, int length,
uint tick)
{
int status;
u8 flags = 0;
int status = 0;
int stop_status;
int expected_start = MVTWSI_STATUS_START;
/* begin i2c write to send the address bytes */
status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
/* send addr bytes */
while ((status == 0) && alen--)
status = twsi_send(adap, addr >> (8*alen),
MVTWSI_STATUS_DATA_W_ACK, &flags);
/* begin i2c read to receive eeprom data bytes */
if (status == 0)
status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
(chip << 1) | 1, &flags);
/* prepare ACK if at least one byte must be received */
if (length > 0)
flags |= MVTWSI_CONTROL_ACK;
/* now receive actual bytes */
while ((status == 0) && length--) {
/* reset NAK if we if no more to read now */
if (length == 0)
flags &= ~MVTWSI_CONTROL_ACK;
/* read current byte */
status = twsi_recv(adap, data++, &flags);
if (alen > 0) {
/* Begin i2c write to send the address bytes */
status = i2c_begin(twsi, expected_start, (chip << 1), tick);
/* Send address bytes */
while ((status == 0) && alen--)
status = twsi_send(twsi, *(addr++),
MVTWSI_STATUS_DATA_W_ACK, tick);
/* Send repeated STARTs after the initial START */
expected_start = MVTWSI_STATUS_REPEATED_START;
}
/* Begin i2c read to receive data bytes */
if (status == 0)
status = i2c_begin(twsi, expected_start, (chip << 1) | 1, tick);
/* Receive actual data bytes; set NAK if we if we have nothing more to
* read */
while ((status == 0) && length--)
status = twsi_recv(twsi, data++,
length > 0 ?
MVTWSI_READ_ACK : MVTWSI_READ_NAK, tick);
/* Stop transaction */
status = twsi_stop(adap, status);
/* return 0 or status of first failure */
return status;
stop_status = twsi_stop(twsi, tick);
/* Return 0, or the status of the first failure */
return status != 0 ? status : stop_status;
}
/*
* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
* Begin write, send address byte(s), send data bytes, end.
* __twsi_i2c_write() - Send data to a I2C chip.
*
* This function begins a I2C write transaction, and transmits the address
* bytes; then begins a new I2C write transaction, and sends the data bytes.
*
* @twsi: The MVTWSI register structure to use.
* @chip: The chip address to read from.
* @addr: The address bytes to send.
* @alen: The length of the address bytes in bytes.
* @data: The buffer containing the data to be sent to the chip.
* @length: The length of data to be sent to the chip in bytes.
* @tick: The duration of a clock cycle at the current I2C speed.
* @return Zero if the operation succeeded, or a non-zero code if a time out or
* unexpected I2C status occurred.
*/
static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *data, int length)
static int __twsi_i2c_write(struct mvtwsi_registers *twsi, uchar chip,
u8 *addr, int alen, uchar *data, int length,
uint tick)
{
int status;
u8 flags = 0;
int status, stop_status;
/* begin i2c write to send the eeprom adress bytes then data bytes */
status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1), &flags);
/* send addr bytes */
while ((status == 0) && alen--)
status = twsi_send(adap, addr >> (8*alen),
MVTWSI_STATUS_DATA_W_ACK, &flags);
/* send data bytes */
/* Begin i2c write to send first the address bytes, then the
* data bytes */
status = i2c_begin(twsi, MVTWSI_STATUS_START, (chip << 1), tick);
/* Send address bytes */
while ((status == 0) && (alen-- > 0))
status = twsi_send(twsi, *(addr++), MVTWSI_STATUS_DATA_W_ACK,
tick);
/* Send data bytes */
while ((status == 0) && (length-- > 0))
status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK,
&flags);
status = twsi_send(twsi, *(data++), MVTWSI_STATUS_DATA_W_ACK,
tick);
/* Stop transaction */
status = twsi_stop(adap, status);
/* return 0 or status of first failure */
return status;
stop_status = twsi_stop(twsi, tick);
/* Return 0, or the status of the first failure */
return status != 0 ? status : stop_status;
}
#ifndef CONFIG_DM_I2C
static void twsi_i2c_init(struct i2c_adapter *adap, int speed,
int slaveadd)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
__twsi_i2c_init(twsi, speed, slaveadd, NULL);
}
static uint twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
uint requested_speed)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
__twsi_i2c_set_bus_speed(twsi, requested_speed);
return 0;
}
static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
return __twsi_i2c_probe_chip(twsi, chip, 10000);
}
static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *data, int length)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
u8 addr_bytes[4];
addr_bytes[0] = (addr >> 0) & 0xFF;
addr_bytes[1] = (addr >> 8) & 0xFF;
addr_bytes[2] = (addr >> 16) & 0xFF;
addr_bytes[3] = (addr >> 24) & 0xFF;
return __twsi_i2c_read(twsi, chip, addr_bytes, alen, data, length,
10000);
}
static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *data, int length)
{
struct mvtwsi_registers *twsi = twsi_get_base(adap);
u8 addr_bytes[4];
addr_bytes[0] = (addr >> 0) & 0xFF;
addr_bytes[1] = (addr >> 8) & 0xFF;
addr_bytes[2] = (addr >> 16) & 0xFF;
addr_bytes[3] = (addr >> 24) & 0xFF;
return __twsi_i2c_write(twsi, chip, addr_bytes, alen, data, length,
10000);
}
#ifdef CONFIG_I2C_MVTWSI_BASE0
@ -494,3 +747,99 @@ U_BOOT_I2C_ADAP_COMPLETE(twsi5, twsi_i2c_init, twsi_i2c_probe,
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 5)
#endif
#else /* CONFIG_DM_I2C */
static int mvtwsi_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
u32 chip_flags)
{
struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
return __twsi_i2c_probe_chip(dev->base, chip_addr, dev->tick);
}
static int mvtwsi_i2c_set_bus_speed(struct udevice *bus, uint speed)
{
struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
dev->speed = __twsi_i2c_set_bus_speed(dev->base, speed);
dev->tick = calc_tick(dev->speed);
return 0;
}
static int mvtwsi_i2c_ofdata_to_platdata(struct udevice *bus)
{
struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
dev->base = dev_get_addr_ptr(bus);
if (!dev->base)
return -ENOMEM;
dev->index = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
"cell-index", -1);
dev->slaveadd = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
"u-boot,i2c-slave-addr", 0x0);
dev->speed = fdtdec_get_int(gd->fdt_blob, bus->of_offset,
"clock-frequency", 100000);
return 0;
}
static int mvtwsi_i2c_probe(struct udevice *bus)
{
struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
uint actual_speed;
__twsi_i2c_init(dev->base, dev->speed, dev->slaveadd, &actual_speed);
dev->speed = actual_speed;
dev->tick = calc_tick(dev->speed);
return 0;
}
static int mvtwsi_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
struct mvtwsi_i2c_dev *dev = dev_get_priv(bus);
struct i2c_msg *dmsg, *omsg, dummy;
memset(&dummy, 0, sizeof(struct i2c_msg));
/* We expect either two messages (one with an offset and one with the
* actual data) or one message (just data or offset/data combined) */
if (nmsgs > 2 || nmsgs == 0) {
debug("%s: Only one or two messages are supported.", __func__);
return -1;
}
omsg = nmsgs == 1 ? &dummy : msg;
dmsg = nmsgs == 1 ? msg : msg + 1;
if (dmsg->flags & I2C_M_RD)
return __twsi_i2c_read(dev->base, dmsg->addr, omsg->buf,
omsg->len, dmsg->buf, dmsg->len,
dev->tick);
else
return __twsi_i2c_write(dev->base, dmsg->addr, omsg->buf,
omsg->len, dmsg->buf, dmsg->len,
dev->tick);
}
static const struct dm_i2c_ops mvtwsi_i2c_ops = {
.xfer = mvtwsi_i2c_xfer,
.probe_chip = mvtwsi_i2c_probe_chip,
.set_bus_speed = mvtwsi_i2c_set_bus_speed,
};
static const struct udevice_id mvtwsi_i2c_ids[] = {
{ .compatible = "marvell,mv64xxx-i2c", },
{ /* sentinel */ }
};
U_BOOT_DRIVER(i2c_mvtwsi) = {
.name = "i2c_mvtwsi",
.id = UCLASS_I2C,
.of_match = mvtwsi_i2c_ids,
.probe = mvtwsi_i2c_probe,
.ofdata_to_platdata = mvtwsi_i2c_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct mvtwsi_i2c_dev),
.ops = &mvtwsi_i2c_ops,
};
#endif /* CONFIG_DM_I2C */

407
drivers/i2c/omap24xx_i2c.c
View File

@ -39,6 +39,7 @@
*/
#include <common.h>
#include <dm.h>
#include <i2c.h>
#include <asm/arch/i2c.h>
@ -53,10 +54,14 @@ DECLARE_GLOBAL_DATA_PTR;
/* Absolutely safe for status update at 100 kHz I2C: */
#define I2C_WAIT 200
static int wait_for_bb(struct i2c_adapter *adap);
static struct i2c *omap24_get_base(struct i2c_adapter *adap);
static u16 wait_for_event(struct i2c_adapter *adap);
static void flush_fifo(struct i2c_adapter *adap);
struct omap_i2c {
struct udevice *clk;
struct i2c *regs;
unsigned int speed;
int waitdelay;
int clk_id;
};
static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
{
unsigned int sampleclk, prescaler;
@ -90,9 +95,96 @@ static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
}
return -1;
}
static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
/*
* Wait for the bus to be free by checking the Bus Busy (BB)
* bit to become clear
*/
static int wait_for_bb(struct i2c *i2c_base, int waitdelay)
{
int timeout = I2C_TIMEOUT;
u16 stat;
writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
#else
/* Read RAW status */
while ((stat = readw(&i2c_base->irqstatus_raw) &
I2C_STAT_BB) && timeout--) {
#endif
writew(stat, &i2c_base->stat);
udelay(waitdelay);
}
if (timeout <= 0) {
printf("Timed out in wait_for_bb: status=%04x\n",
stat);
return 1;
}
writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
return 0;
}
/*
* Wait for the I2C controller to complete current action
* and update status
*/
static u16 wait_for_event(struct i2c *i2c_base, int waitdelay)
{
u16 status;
int timeout = I2C_TIMEOUT;
do {
udelay(waitdelay);
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
status = readw(&i2c_base->stat);
#else
/* Read RAW status */
status = readw(&i2c_base->irqstatus_raw);
#endif
} while (!(status &
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
I2C_STAT_AL)) && timeout--);
if (timeout <= 0) {
printf("Timed out in wait_for_event: status=%04x\n",
status);
/*
* If status is still 0 here, probably the bus pads have
* not been configured for I2C, and/or pull-ups are missing.
*/
printf("Check if pads/pull-ups of bus are properly configured\n");
writew(0xFFFF, &i2c_base->stat);
status = 0;
}
return status;
}
static void flush_fifo(struct i2c *i2c_base)
{
u16 stat;
/*
* note: if you try and read data when its not there or ready
* you get a bus error
*/
while (1) {
stat = readw(&i2c_base->stat);
if (stat == I2C_STAT_RRDY) {
readb(&i2c_base->data);
writew(I2C_STAT_RRDY, &i2c_base->stat);
udelay(1000);
} else
break;
}
}
static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed,
int *waitdelay)
{
struct i2c *i2c_base = omap24_get_base(adap);
int psc, fsscll = 0, fssclh = 0;
int hsscll = 0, hssclh = 0;
u32 scll = 0, sclh = 0;
@ -142,8 +234,7 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
}
}
adap->speed = speed;
adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
*waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */
writew(0, &i2c_base->con);
writew(psc, &i2c_base->psc);
writew(scll, &i2c_base->scll);
@ -154,9 +245,8 @@ static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
return 0;
}
static void omap24_i2c_deblock(struct i2c_adapter *adap)
static void omap24_i2c_deblock(struct i2c *i2c_base)
{
struct i2c *i2c_base = omap24_get_base(adap);
int i;
u16 systest;
u16 orgsystest;
@ -200,9 +290,9 @@ static void omap24_i2c_deblock(struct i2c_adapter *adap)
writew(orgsystest, &i2c_base->systest);
}
static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd,
int *waitdelay)
{
struct i2c *i2c_base = omap24_get_base(adap);
int timeout = I2C_TIMEOUT;
int deblock = 1;
@ -224,7 +314,7 @@ retry:
udelay(1000);
}
if (0 != omap24_i2c_setspeed(adap, speed)) {
if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) {
printf("ERROR: failed to setup I2C bus-speed!\n");
return;
}
@ -241,45 +331,24 @@ retry:
I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
#endif
udelay(1000);
flush_fifo(adap);
flush_fifo(i2c_base);
writew(0xFFFF, &i2c_base->stat);
/* Handle possible failed I2C state */
if (wait_for_bb(adap))
if (wait_for_bb(i2c_base, *waitdelay))
if (deblock == 1) {
omap24_i2c_deblock(adap);
omap24_i2c_deblock(i2c_base);
deblock = 0;
goto retry;
}
}
static void flush_fifo(struct i2c_adapter *adap)
{
struct i2c *i2c_base = omap24_get_base(adap);
u16 stat;
/*
* note: if you try and read data when its not there or ready
* you get a bus error
*/
while (1) {
stat = readw(&i2c_base->stat);
if (stat == I2C_STAT_RRDY) {
readb(&i2c_base->data);
writew(I2C_STAT_RRDY, &i2c_base->stat);
udelay(1000);
} else
break;
}
}
/*
* i2c_probe: Use write access. Allows to identify addresses that are
* write-only (like the config register of dual-port EEPROMs)
*/
static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip)
{
struct i2c *i2c_base = omap24_get_base(adap);
u16 status;
int res = 1; /* default = fail */
@ -287,7 +356,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
return res;
/* Wait until bus is free */
if (wait_for_bb(adap))
if (wait_for_bb(i2c_base, waitdelay))
return res;
/* No data transfer, slave addr only */
@ -296,7 +365,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
I2C_CON_STP, &i2c_base->con);
status = wait_for_event(adap);
status = wait_for_event(i2c_base, waitdelay);
if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
/*
@ -306,8 +375,8 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
* following 'if' section:
*/
if (status == I2C_STAT_XRDY)
printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
adap->hwadapnr, status);
printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
status);
goto pr_exit;
}
@ -315,7 +384,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
/* Check for ACK (!NAK) */
if (!(status & I2C_STAT_NACK)) {
res = 0; /* Device found */
udelay(adap->waitdelay);/* Required by AM335X in SPL */
udelay(waitdelay);/* Required by AM335X in SPL */
/* Abort transfer (force idle state) */
writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
udelay(1000);
@ -323,7 +392,7 @@ static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
I2C_CON_STP, &i2c_base->con); /* STP */
}
pr_exit:
flush_fifo(adap);
flush_fifo(i2c_base);
writew(0xFFFF, &i2c_base->stat);
return res;
}
@ -341,10 +410,9 @@ pr_exit:
* or that do not need a register address at all (such as some clock
* distributors).
*/
static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *buffer, int len)
static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip,
uint addr, int alen, uchar *buffer, int len)
{
struct i2c *i2c_base = omap24_get_base(adap);
int i2c_error = 0;
u16 status;
@ -389,7 +457,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
#endif
/* Wait until bus not busy */
if (wait_for_bb(adap))
if (wait_for_bb(i2c_base, waitdelay))
return 1;
/* Zero, one or two bytes reg address (offset) */
@ -410,12 +478,12 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
#endif
/* Send register offset */
while (1) {
status = wait_for_event(adap);
status = wait_for_event(i2c_base, waitdelay);
/* Try to identify bus that is not padconf'd for I2C */
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
adap->hwadapnr, status);
printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
status);
goto rd_exit;
}
if (status == 0 || (status & I2C_STAT_NACK)) {
@ -450,7 +518,7 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
/* Receive data */
while (1) {
status = wait_for_event(adap);
status = wait_for_event(i2c_base, waitdelay);
/*
* Try to identify bus that is not padconf'd for I2C. This
* state could be left over from previous transactions if
@ -458,8 +526,8 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
*/
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
adap->hwadapnr, status);
printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
status);
goto rd_exit;
}
if (status == 0 || (status & I2C_STAT_NACK)) {
@ -477,16 +545,15 @@ static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
}
rd_exit:
flush_fifo(adap);
flush_fifo(i2c_base);
writew(0xFFFF, &i2c_base->stat);
return i2c_error;
}
/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *buffer, int len)
static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip,
uint addr, int alen, uchar *buffer, int len)
{
struct i2c *i2c_base = omap24_get_base(adap);
int i;
u16 status;
int i2c_error = 0;
@ -536,7 +603,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
#endif
/* Wait until bus not busy */
if (wait_for_bb(adap))
if (wait_for_bb(i2c_base, waitdelay))
return 1;
/* Start address phase - will write regoffset + len bytes data */
@ -549,12 +616,12 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
while (alen) {
/* Must write reg offset (one or two bytes) */
status = wait_for_event(adap);
status = wait_for_event(i2c_base, waitdelay);
/* Try to identify bus that is not padconf'd for I2C */
if (status == I2C_STAT_XRDY) {
i2c_error = 2;
printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
adap->hwadapnr, status);
printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
status);
goto wr_exit;
}
if (status == 0 || (status & I2C_STAT_NACK)) {
@ -576,7 +643,7 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
}
/* Address phase is over, now write data */
for (i = 0; i < len; i++) {
status = wait_for_event(adap);
status = wait_for_event(i2c_base, waitdelay);
if (status == 0 || (status & I2C_STAT_NACK)) {
i2c_error = 1;
printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
@ -598,87 +665,22 @@ static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
* transferred on the bus.
*/
do {
status = wait_for_event(adap);
status = wait_for_event(i2c_base, waitdelay);
} while (!(status & I2C_STAT_ARDY) && timeout--);
if (timeout <= 0)
printf("i2c_write: timed out writig last byte!\n");
wr_exit:
flush_fifo(adap);
flush_fifo(i2c_base);
writew(0xFFFF, &i2c_base->stat);
return i2c_error;
}
#ifndef CONFIG_DM_I2C
/*
* Wait for the bus to be free by checking the Bus Busy (BB)
* bit to become clear
* The legacy I2C functions. These need to get removed once
* all users of this driver are converted to DM.
*/
static int wait_for_bb(struct i2c_adapter *adap)
{
struct i2c *i2c_base = omap24_get_base(adap);
int timeout = I2C_TIMEOUT;
u16 stat;
writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
#else
/* Read RAW status */
while ((stat = readw(&i2c_base->irqstatus_raw) &
I2C_STAT_BB) && timeout--) {
#endif
writew(stat, &i2c_base->stat);
udelay(adap->waitdelay);
}
if (timeout <= 0) {
printf("Timed out in wait_for_bb: status=%04x\n",
stat);
return 1;
}
writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
return 0;
}
/*
* Wait for the I2C controller to complete current action
* and update status
*/
static u16 wait_for_event(struct i2c_adapter *adap)
{
struct i2c *i2c_base = omap24_get_base(adap);
u16 status;
int timeout = I2C_TIMEOUT;
do {
udelay(adap->waitdelay);
#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
status = readw(&i2c_base->stat);
#else
/* Read RAW status */
status = readw(&i2c_base->irqstatus_raw);
#endif
} while (!(status &
(I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
I2C_STAT_AL)) && timeout--);
if (timeout <= 0) {
printf("Timed out in wait_for_event: status=%04x\n",
status);
/*
* If status is still 0 here, probably the bus pads have
* not been configured for I2C, and/or pull-ups are missing.
*/
printf("Check if pads/pull-ups of bus %d are properly configured\n",
adap->hwadapnr);
writew(0xFFFF, &i2c_base->stat);
status = 0;
}
return status;
}
static struct i2c *omap24_get_base(struct i2c_adapter *adap)
{
switch (adap->hwadapnr) {
@ -710,6 +712,56 @@ static struct i2c *omap24_get_base(struct i2c_adapter *adap)
return NULL;
}
static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *buffer, int len)
{
struct i2c *i2c_base = omap24_get_base(adap);
return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr,
alen, buffer, len);
}
static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *buffer, int len)
{
struct i2c *i2c_base = omap24_get_base(adap);
return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr,
alen, buffer, len);
}
static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
{
struct i2c *i2c_base = omap24_get_base(adap);
int ret;
ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay);
if (ret) {
error("%s: set i2c speed failed\n", __func__);
return ret;
}
adap->speed = speed;
return 0;
}
static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
{
struct i2c *i2c_base = omap24_get_base(adap);
return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay);
}
static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
{
struct i2c *i2c_base = omap24_get_base(adap);
return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip);
}
#if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
#define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
#endif
@ -769,3 +821,92 @@ U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
#endif
#endif
#endif
#else /* CONFIG_DM_I2C */
static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
{
struct omap_i2c *priv = dev_get_priv(bus);
int ret;
debug("i2c_xfer: %d messages\n", nmsgs);
for (; nmsgs > 0; nmsgs--, msg++) {
debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
if (msg->flags & I2C_M_RD) {
ret = __omap24_i2c_read(priv->regs, priv->waitdelay,
msg->addr, 0, 0, msg->buf,
msg->len);
} else {
ret = __omap24_i2c_write(priv->regs, priv->waitdelay,
msg->addr, 0, 0, msg->buf,
msg->len);
}
if (ret) {
debug("i2c_write: error sending\n");
return -EREMOTEIO;
}
}
return 0;
}
static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
struct omap_i2c *priv = dev_get_priv(bus);
priv->speed = speed;
return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay);
}
static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
uint chip_flags)
{
struct omap_i2c *priv = dev_get_priv(bus);
return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr);
}
static int omap_i2c_probe(struct udevice *bus)
{
struct omap_i2c *priv = dev_get_priv(bus);
__omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay);
return 0;
}
static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
{
struct omap_i2c *priv = dev_get_priv(bus);
priv->regs = map_physmem(dev_get_addr(bus), sizeof(void *),
MAP_NOCACHE);
priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED;
return 0;
}
static const struct dm_i2c_ops omap_i2c_ops = {
.xfer = omap_i2c_xfer,
.probe_chip = omap_i2c_probe_chip,
.set_bus_speed = omap_i2c_set_bus_speed,
};
static const struct udevice_id omap_i2c_ids[] = {
{ .compatible = "ti,omap4-i2c" },
{ }
};
U_BOOT_DRIVER(i2c_omap) = {
.name = "i2c_omap",
.id = UCLASS_I2C,
.of_match = omap_i2c_ids,
.ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
.probe = omap_i2c_probe,
.priv_auto_alloc_size = sizeof(struct omap_i2c),
.ops = &omap_i2c_ops,
.flags = DM_FLAG_PRE_RELOC,
};
#endif /* CONFIG_DM_I2C */

16
include/configs/ti_armv7_common.h
View File

@ -108,9 +108,25 @@
/* Timer information. */
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
/*
* Disable DM_* for SPL build and can be re-enabled after adding
* DM support in SPL
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_I2C
#endif
/* I2C IP block */
#define CONFIG_I2C
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#else
/*
* Enable CONFIG_DM_I2C_COMPAT temporarily until all the i2c client
* devices are adopted to DM
*/
#define CONFIG_DM_I2C_COMPAT
#endif
/* MMC/SD IP block */
#define CONFIG_MMC

17
tools/env/fw_env.c vendored
View File

@ -661,8 +661,8 @@ static int flash_bad_block (int fd, uint8_t mtd_type, loff_t *blockstart)
if (badblock) {
#ifdef DEBUG
fprintf (stderr, "Bad block at 0x%llx, "
"skipping\n", *blockstart);
fprintf (stderr, "Bad block at 0x%llx, skipping\n",
(unsigned long long) *blockstart);
#endif
return badblock;
}
@ -749,7 +749,8 @@ static int flash_read_buf (int dev, int fd, void *buf, size_t count,
}
#ifdef DEBUG
fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
rc, blockstart + block_seek, DEVNAME(dev));
rc, (unsigned long long) blockstart + block_seek,
DEVNAME(dev));
#endif
processed += readlen;
readlen = min (blocklen, count - processed);
@ -847,8 +848,9 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count,
if (block_seek + count != write_total) {
if (block_seek != 0)
fprintf(stderr, " and ");
fprintf(stderr, "0x%lx - 0x%x",
block_seek + count, write_total - 1);
fprintf(stderr, "0x%lx - 0x%lx",
(unsigned long) block_seek + count,
(unsigned long) write_total - 1);
}
fprintf(stderr, "\n");
#endif
@ -911,8 +913,9 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count,
}
#ifdef DEBUG
fprintf(stderr, "Write 0x%x bytes at 0x%llx\n", erasesize,
blockstart);
fprintf(stderr, "Write 0x%llx bytes at 0x%llx\n",
(unsigned long long) erasesize,
(unsigned long long) blockstart);
#endif
if (write (fd, data + processed, erasesize) != erasesize) {
fprintf (stderr, "Write error on %s: %s\n",