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Patch by Yuli Barcohen, 20 May 2004:
Add support for Interphase iSPAN boards.
This commit is contained in:
wdenk
parent
f39748ae8e
commit
c3c7f861ae
@ -2,7 +2,12 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Paul Ruhland, 17 May 2004:
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* Patch by Yuli Barcohen, 20 May 2004:
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Add support for Interphase iSPAN boards.
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* Patches by Paul Ruhland, 17 May 2004:
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- Add I/O functions to the smc91111 ethernet driver to support the
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Logic LPD7A40x boards.
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- Add support for the Logic Zoom LH7A40x based SDK board(s),
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specifically the LPD7A400.
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1
CREDITS
1
CREDITS
@ -38,6 +38,7 @@ N: Yuli Barcohen
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E: yuli@arabellasw.com
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D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards.
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D: Support for Zephyr Engineering ZPC.1900 board.
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D: Support for Interphase iSPAN boards.
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W: http://www.arabellasw.com
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N: Jerry van Baren
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@ -27,6 +27,7 @@ Pantelis Antoniou <panto@intracom.gr>
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Yuli Barcohen <yuli@arabellasw.com>
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ISPAN MPC8260
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MPC8260ADS MPC826x/MPC827x/MPC8280
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ZPC1900 MPC8265
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10
MAKEALL
10
MAKEALL
@ -86,11 +86,11 @@ LIST_824x=" \
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LIST_8260=" \
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atc cogent_mpc8260 CPU86 ep8260 \
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gw8260 hymod IPHASE4539 MPC8260ADS \
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MPC8266ADS MPC8272ADS PM826 PM828 \
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ppmc8260 PQ2FADS RPXsuper rsdproto \
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sacsng sbc8260 SCM TQM8260_AC \
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TQM8260_AD TQM8260_AE ZPC1900 \
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gw8260 hymod IPHASE4539 ISPAN \
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MPC8260ADS MPC8266ADS MPC8272ADS PM826 \
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PM828 ppmc8260 PQ2FADS RPXsuper \
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rsdproto sacsng sbc8260 SCM \
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TQM8260_AC TQM8260_AD TQM8260_AE ZPC1900 \
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"
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#########################################################################
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7
Makefile
7
Makefile
@ -789,6 +789,13 @@ hymod_config: unconfig
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IPHASE4539_config: unconfig
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@./mkconfig $(@:_config=) ppc mpc8260 iphase4539
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ISPAN_config \
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ISPAN_REVB_config: unconfig
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@if [ "$(findstring _REVB_,$@)" ] ; then \
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echo "#define CFG_REV_B" > include/config.h ; \
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fi
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@./mkconfig -a ISPAN ppc mpc8260 ispan
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MPC8260ADS_config \
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MPC8260ADS_33MHz_config \
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MPC8260ADS_40MHz_config \
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46
board/ispan/Makefile
Normal file
46
board/ispan/Makefile
Normal file
@ -0,0 +1,46 @@
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#
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# Copyright (C) 2004 Arabella Software Ltd.
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# Yuli Barcohen <yuli@arabellasw.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(BOARD).a
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OBJS := $(BOARD).o
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$(LIB): $(OBJS) $(SOBJS)
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$(AR) crv $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak .depend
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#########################################################################
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.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
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$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
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-include .depend
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#########################################################################
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29
board/ispan/config.mk
Normal file
29
board/ispan/config.mk
Normal file
@ -0,0 +1,29 @@
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#
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# Copyright (C) 2004 Arabella Software Ltd.
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# Yuli Barcohen <yuli@arabellasw.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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#
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# Interphase iSPAN Communications Controllers
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#
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#TEXT_BASE = 0xFF800000
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#TEXT_BASE = 0xFFBA0000
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TEXT_BASE = 0xFE7A0000
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462
board/ispan/ispan.c
Normal file
462
board/ispan/ispan.c
Normal file
@ -0,0 +1,462 @@
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/*
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* Copyright (C) 2004 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Support for Interphase iSPAN Communications Controllers
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* (453x and others). Tested on 4532.
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*
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* Derived from iSPAN 4539 port (iphase4539) by
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* Wolfgang Grandegger <wg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <asm/io.h>
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/*
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* I/O Ports configuration table
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*
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* If conf is 1, then that port pin will be configured at boot time
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* according to the five values podr/pdir/ppar/psor/pdat for that entry
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*/
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#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
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#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
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#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
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const iop_conf_t iop_conf_tab[4][32] = {
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/* Port A */
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{ /* conf ppar psor pdir podr pdat */
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/* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
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/* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
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/* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
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/* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
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/* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
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/* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
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/* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
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/* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
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/* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
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/* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
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/* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
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/* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
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/* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
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/* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
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/* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
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/* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
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/* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
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/* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
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/* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
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/* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
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/* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
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/* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
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/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */
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/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */
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/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
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/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
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/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
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/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
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/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
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/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
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/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
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/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
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},
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/* Port B */
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{ /* conf ppar psor pdir podr pdat */
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/* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
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/* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
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/* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
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/* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
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/* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
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/* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
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/* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
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/* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
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/* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
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/* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
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/* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
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/* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
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/* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
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/* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
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/* PB17 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
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/* PB16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
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/* PB15 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
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/* PB14 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
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/* PB13 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
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/* PB12 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
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/* PB11 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
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/* PB10 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
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/* PB9 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
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/* PB8 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
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/* PB7 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
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/* PB6 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
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/* PB5 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
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/* PB4 */ { CFG_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
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/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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},
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/* Port C */
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{ /* conf ppar psor pdir podr pdat */
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/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
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/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
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/* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
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/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
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/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
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/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
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/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
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/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
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/* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
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/* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
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/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
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/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
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/* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
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/* PC18 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
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/* PC16 */ { CFG_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */
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/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
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/* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
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/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
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/* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
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/* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
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/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
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/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
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/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
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/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
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/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
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/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
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/* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */
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},
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
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/* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
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/* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
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/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
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/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
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/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
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/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
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/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
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/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
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/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
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/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
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/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
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/* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */
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/* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */
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/* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */
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/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */
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/* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */
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/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
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/* PD6 */ { CFG_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */
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/* PD5 */ { CFG_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */
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/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
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/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
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/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
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}
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};
|
||||
|
||||
#define PSPAN_ADDR 0xF0020000
|
||||
#define EEPROM_REG 0x408
|
||||
#define EEPROM_READ_CMD 0xA000
|
||||
#define PSPAN_WRITE(a,v) \
|
||||
*((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
|
||||
#define PSPAN_READ(a) \
|
||||
*((volatile unsigned long *)(PSPAN_ADDR+(a)))
|
||||
|
||||
static int seeprom_read (int addr, uchar * data, int size)
|
||||
{
|
||||
ulong val, cmd;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < size; i++) {
|
||||
|
||||
cmd = EEPROM_READ_CMD;
|
||||
cmd |= ((addr + i) << 24) & 0xff000000;
|
||||
|
||||
/* Wait for ACT to authorize write */
|
||||
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
|
||||
eieio ();
|
||||
|
||||
/* Write command */
|
||||
PSPAN_WRITE (EEPROM_REG, cmd);
|
||||
|
||||
/* Wait for data to be valid */
|
||||
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
|
||||
eieio ();
|
||||
/* Do it twice, first read might be erratic */
|
||||
while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
|
||||
eieio ();
|
||||
|
||||
/* Read error */
|
||||
if (val & 0x00000040) {
|
||||
return -1;
|
||||
} else {
|
||||
data[i] = (val >> 16) & 0xff;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/***************************************************************
|
||||
* We take some basic Hardware Configuration Parameter from the
|
||||
* Serial EEPROM conected to the PSpan bridge. We keep it as
|
||||
* simple as possible.
|
||||
*/
|
||||
static int hwc_flash_size (void)
|
||||
{
|
||||
uchar byte;
|
||||
|
||||
if (!seeprom_read (0x40, &byte, sizeof (byte))) {
|
||||
switch ((byte >> 2) & 0x3) {
|
||||
case 0x1:
|
||||
return 0x0400000;
|
||||
break;
|
||||
case 0x2:
|
||||
return 0x0800000;
|
||||
break;
|
||||
case 0x3:
|
||||
return 0x1000000;
|
||||
default:
|
||||
return 0x0100000;
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int hwc_local_sdram_size (void)
|
||||
{
|
||||
uchar byte;
|
||||
|
||||
if (!seeprom_read (0x40, &byte, sizeof (byte))) {
|
||||
switch ((byte & 0x03)) {
|
||||
case 0x1:
|
||||
return 0x0800000;
|
||||
case 0x2:
|
||||
return 0x1000000;
|
||||
default:
|
||||
return 0; /* not present */
|
||||
}
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int hwc_main_sdram_size (void)
|
||||
{
|
||||
uchar byte;
|
||||
|
||||
if (!seeprom_read (0x41, &byte, sizeof (byte))) {
|
||||
return 0x1000000 << ((byte >> 5) & 0x7);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int hwc_serial_number (void)
|
||||
{
|
||||
int sn = -1;
|
||||
|
||||
if (!seeprom_read (0xa0, (char *) &sn, sizeof (sn))) {
|
||||
sn = cpu_to_le32 (sn);
|
||||
}
|
||||
return sn;
|
||||
}
|
||||
|
||||
static int hwc_mac_address (char *str)
|
||||
{
|
||||
char mac[6];
|
||||
|
||||
if (!seeprom_read (0xb0, mac, sizeof (mac))) {
|
||||
sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
|
||||
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
|
||||
} else {
|
||||
strcpy (str, "ERROR");
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int hwc_manufact_date (char *str)
|
||||
{
|
||||
uchar byte;
|
||||
int value;
|
||||
|
||||
if (seeprom_read (0x92, &byte, sizeof (byte)))
|
||||
goto out;
|
||||
value = byte;
|
||||
if (seeprom_read (0x93, &byte, sizeof (byte)))
|
||||
goto out;
|
||||
value += byte << 8;
|
||||
sprintf (str, "%02d/%02d/%04d",
|
||||
value & 0x1F, (value >> 5) & 0xF,
|
||||
1980 + ((value >> 9) & 0x1FF));
|
||||
return 0;
|
||||
|
||||
out:
|
||||
strcpy (str, "ERROR");
|
||||
return -1;
|
||||
}
|
||||
|
||||
static int hwc_board_type (char **str)
|
||||
{
|
||||
ushort id = 0;
|
||||
|
||||
if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
|
||||
switch (id) {
|
||||
case 0x9080:
|
||||
*str = "4532-002";
|
||||
break;
|
||||
case 0x9081:
|
||||
*str = "4532-001";
|
||||
break;
|
||||
case 0x9082:
|
||||
*str = "4532-000";
|
||||
break;
|
||||
default:
|
||||
*str = "Unknown";
|
||||
}
|
||||
} else {
|
||||
*str = "Unknown";
|
||||
}
|
||||
|
||||
return id;
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long maxsize = hwc_main_sdram_size();
|
||||
|
||||
#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE)
|
||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||||
volatile uchar *base;
|
||||
int i;
|
||||
|
||||
immap->im_siu_conf.sc_ppc_acr = 0x00000026;
|
||||
immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
|
||||
immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
|
||||
immap->im_siu_conf.sc_lcl_acr = 0x00000000;
|
||||
immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
|
||||
immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
|
||||
immap->im_siu_conf.sc_tescr1 = 0x00004000;
|
||||
immap->im_siu_conf.sc_ltescr1 = 0x00004000;
|
||||
|
||||
memctl->memc_mptpr = CFG_MPTPR;
|
||||
|
||||
/* Initialise 60x bus SDRAM */
|
||||
base = (uchar *)(CFG_SDRAM_BASE | 0x110);
|
||||
memctl->memc_psrt = CFG_PSRT;
|
||||
memctl->memc_or1 = CFG_60x_OR;
|
||||
memctl->memc_br1 = CFG_SDRAM_BASE | CFG_60x_BR;
|
||||
|
||||
memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
|
||||
*base = 0xFF;
|
||||
memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
|
||||
for (i = 0; i < 8; i++)
|
||||
*base = 0xFF;
|
||||
memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
|
||||
*base = 0xFF;
|
||||
memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
|
||||
|
||||
/* Initialise local bus SDRAM */
|
||||
base = (uchar *)CFG_LSDRAM_BASE;
|
||||
memctl->memc_lsrt = CFG_LSRT;
|
||||
memctl->memc_or2 = CFG_LOC_OR;
|
||||
memctl->memc_br2 = CFG_LSDRAM_BASE | CFG_LOC_BR;
|
||||
|
||||
memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
|
||||
*base = 0xFF;
|
||||
memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
|
||||
for (i = 0; i < 8; i++)
|
||||
*base = 0xFF;
|
||||
memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
|
||||
*base = 0xFF;
|
||||
memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
|
||||
|
||||
/* We must be able to test a location outsize the maximum legal size
|
||||
* to find out THAT we are outside; but this address still has to be
|
||||
* mapped by the controller. That means, that the initial mapping has
|
||||
* to be (at least) twice as large as the maximum expected size.
|
||||
*/
|
||||
maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
|
||||
|
||||
maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
|
||||
|
||||
memctl->memc_or1 |= ~(maxsize - 1);
|
||||
|
||||
if (maxsize != hwc_main_sdram_size())
|
||||
puts("Oops: memory test has not found all memory!\n");
|
||||
#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */
|
||||
|
||||
/* Return total RAM size (size of 60x SDRAM) */
|
||||
return maxsize;
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
char string[32], *id;
|
||||
|
||||
hwc_manufact_date(string);
|
||||
hwc_board_type(&id);
|
||||
printf("Board: Interphase iSPAN %s (#%d %s)\n",
|
||||
id, hwc_serial_number(), string);
|
||||
#ifdef DEBUG
|
||||
printf("Manufacturing date: %s\n", string);
|
||||
printf("Serial number : %d\n", hwc_serial_number());
|
||||
printf("FLASH size : %d MB\n", hwc_flash_size() >> 20);
|
||||
printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20);
|
||||
printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20);
|
||||
hwc_mac_address(string);
|
||||
printf("MAC address : %s\n", string);
|
||||
#endif
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
char *s, str[32];
|
||||
int num;
|
||||
|
||||
if ((s = getenv("serial#")) == NULL &&
|
||||
(num = hwc_serial_number()) != -1) {
|
||||
sprintf(str, "%06d", num);
|
||||
setenv("serial#", str);
|
||||
}
|
||||
if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
|
||||
setenv("ethaddr", str);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
122
board/ispan/u-boot.lds
Normal file
122
board/ispan/u-boot.lds
Normal file
@ -0,0 +1,122 @@
|
||||
/*
|
||||
* (C) Copyright 2001-2003
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Modified by Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/mpc8260/start.o (.text)
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
. = ALIGN(16);
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(4096);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(4096);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
||||
ENTRY(_start)
|
||||
@ -220,6 +220,77 @@ int get_rom_mac(char *v_rom_mac);
|
||||
------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_SMC_USE_IOFUNCS
|
||||
/*
|
||||
* input and output functions
|
||||
*
|
||||
* Implemented due to inx,outx macros accessing the device improperly
|
||||
* and putting the device into an unkown state.
|
||||
*
|
||||
* For instance, on Sharp LPD7A400 SDK, affects were chip memory
|
||||
* could not be free'd (hence the alloc failures), duplicate packets,
|
||||
* packets being corrupt (shifted) on the wire, etc. Switching to the
|
||||
* inx,outx functions fixed this problem.
|
||||
*/
|
||||
static inline word SMC_inw(dword offset);
|
||||
static inline void SMC_outw(word value, dword offset);
|
||||
static inline byte SMC_inb(dword offset);
|
||||
static inline void SMC_outb(byte value, dword offset);
|
||||
static inline void SMC_insw(dword offset, volatile uchar* buf, dword len);
|
||||
static inline void SMC_outsw(dword offset, uchar* buf, dword len);
|
||||
|
||||
#define barrier() __asm__ __volatile__("": : :"memory")
|
||||
|
||||
static inline word SMC_inw(dword offset)
|
||||
{
|
||||
word v;
|
||||
v = *((volatile word*)(SMC_BASE_ADDRESS+offset));
|
||||
barrier(); *(volatile u32*)(0xc0000000);
|
||||
return v;
|
||||
}
|
||||
|
||||
static inline void SMC_outw(word value, dword offset)
|
||||
{
|
||||
*((volatile word*)(SMC_BASE_ADDRESS+offset)) = value;
|
||||
barrier(); *(volatile u32*)(0xc0000000);
|
||||
}
|
||||
|
||||
static inline byte SMC_inb(dword offset)
|
||||
{
|
||||
word _w;
|
||||
|
||||
_w = SMC_inw(offset & ~((dword)1));
|
||||
return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w);
|
||||
}
|
||||
|
||||
static inline void SMC_outb(byte value, dword offset)
|
||||
{
|
||||
word _w;
|
||||
|
||||
_w = SMC_inw(offset & ~((dword)1));
|
||||
if (offset & 1)
|
||||
*((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff);
|
||||
else
|
||||
*((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00);
|
||||
}
|
||||
|
||||
static inline void SMC_insw(dword offset, volatile uchar* buf, dword len)
|
||||
{
|
||||
while (len-- > 0) {
|
||||
*((word*)buf)++ = SMC_inw(offset);
|
||||
barrier(); *((volatile u32*)(0xc0000000));
|
||||
}
|
||||
}
|
||||
|
||||
static inline void SMC_outsw(dword offset, uchar* buf, dword len)
|
||||
{
|
||||
while (len-- > 0) {
|
||||
SMC_outw(*((word*)buf)++, offset);
|
||||
barrier(); *(volatile u32*)(0xc0000000);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_SMC_USE_IOFUNCS */
|
||||
|
||||
static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8};
|
||||
|
||||
/*
|
||||
|
||||
@ -139,6 +139,7 @@ typedef unsigned long int dword;
|
||||
|
||||
#else /* if not CONFIG_PXA250 */
|
||||
|
||||
#ifndef CONFIG_SMC_USE_IOFUNCS /* these macros don't work on some boards */
|
||||
/*
|
||||
* We have only 16 Bit PCMCIA access on Socket 0
|
||||
*/
|
||||
@ -186,6 +187,8 @@ typedef unsigned long int dword;
|
||||
})
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_SMC_USE_IOFUNCS */
|
||||
|
||||
#if defined(CONFIG_SMC_USE_32_BIT)
|
||||
|
||||
#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))))
|
||||
|
||||
344
include/configs/ISPAN.h
Normal file
344
include/configs/ISPAN.h
Normal file
@ -0,0 +1,344 @@
|
||||
/*
|
||||
* Copyright (C) 2004 Arabella Software Ltd.
|
||||
* Yuli Barcohen <yuli@arabellasw.com>
|
||||
*
|
||||
* Support for Interphase iSPAN Communications Controllers
|
||||
* (453x and others). Tested on 4532.
|
||||
*
|
||||
* Derived from iSPAN 4539 port (iphase4539) by
|
||||
* Wolfgang Grandegger <wg@denx.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_MPC8260 /* This is an MPC8260 CPU */
|
||||
#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Select serial console configuration
|
||||
*
|
||||
* If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
|
||||
* CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
|
||||
* for SCC).
|
||||
*
|
||||
* If CONFIG_CONS_NONE is defined, then the serial console routines must be
|
||||
* defined elsewhere (for example, on the cogent platform, there are serial
|
||||
* ports on the motherboard which are used for the serial console - see
|
||||
* cogent/cma101/serial.[ch]).
|
||||
*/
|
||||
#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
|
||||
#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
|
||||
#undef CONFIG_CONS_NONE /* Define if console on something else */
|
||||
#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Select Ethernet configuration
|
||||
*
|
||||
* If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
|
||||
* CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
|
||||
* for FCC).
|
||||
*
|
||||
* If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
|
||||
* be defined elsewhere (as for the console), or CFG_CMD_NET must be removed
|
||||
* from CONFIG_COMMANDS to remove support for networking.
|
||||
*/
|
||||
#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
|
||||
#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
|
||||
#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
|
||||
|
||||
#ifdef CONFIG_ETHER_ON_FCC
|
||||
|
||||
#if CONFIG_ETHER_INDEX == 3
|
||||
|
||||
#define CFG_PHY_ADDR 0
|
||||
#define CFG_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
|
||||
#define CFG_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
|
||||
|
||||
#endif /* CONFIG_ETHER_INDEX == 3 */
|
||||
|
||||
#define CFG_CPMFCR_RAMTYPE 0
|
||||
#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
|
||||
|
||||
#define CONFIG_MII /* MII PHY management */
|
||||
#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
|
||||
/*
|
||||
* GPIO pins used for bit-banged MII communications
|
||||
*/
|
||||
#define MDIO_PORT 3 /* Port D */
|
||||
|
||||
#define CFG_MDIO_PIN 0x00040000 /* PD13 */
|
||||
#define CFG_MDC_PIN 0x00080000 /* PD12 */
|
||||
|
||||
#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN)
|
||||
#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN)
|
||||
#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0)
|
||||
|
||||
#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \
|
||||
else iop->pdat &= ~CFG_MDIO_PIN
|
||||
|
||||
#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \
|
||||
else iop->pdat &= ~CFG_MDC_PIN
|
||||
|
||||
#define MIIDELAY udelay(1)
|
||||
|
||||
#endif /* CONFIG_ETHER_ON_FCC */
|
||||
|
||||
#define CONFIG_8260_CLKIN 65536000 /* in Hz */
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL \
|
||||
| CFG_CMD_ASKENV \
|
||||
| CFG_CMD_DHCP \
|
||||
| CFG_CMD_ECHO \
|
||||
| CFG_CMD_IMMAP \
|
||||
| CFG_CMD_MII \
|
||||
| CFG_CMD_PING \
|
||||
| CFG_CMD_REGINFO \
|
||||
)
|
||||
|
||||
/* This must be included AFTER the definition of CONFIG_COMMANDS */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||
#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
|
||||
#define CONFIG_BOOTARGS "root=/dev/ram rw"
|
||||
|
||||
#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
|
||||
#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#define CFG_HUSH_PARSER
|
||||
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||
#define CFG_LONGHELP /* #undef to save memory */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* Max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* Default load address */
|
||||
|
||||
#define CFG_HZ 1000 /* Decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
#define CFG_RESET_ADDRESS 0x09900000
|
||||
|
||||
#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
||||
#ifdef CONFIG_BZIP2
|
||||
#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
|
||||
#else
|
||||
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
|
||||
#endif /* CONFIG_BZIP2 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xFE000000
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
#define CFG_MAX_FLASH_BANKS 1 /* Max num of memory banks */
|
||||
#define CFG_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
|
||||
|
||||
/* Environment is in flash, there is little space left in Serial EEPROM */
|
||||
#define CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Hard Reset Configuration Words
|
||||
*
|
||||
* If you change bits in the HRCW, you must also change the CFG_*
|
||||
* defines for the various registers affected by the HRCW e.g. changing
|
||||
* HRCW_DPPCxx requires you to also change CFG_SIUMCR.
|
||||
*/
|
||||
/* 0x1686B245 */
|
||||
#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
|
||||
HRCW_L2CPC10 | HRCW_ISB110 |\
|
||||
HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
|
||||
HRCW_CS10PC01 | HRCW_MODCK_H0101 \
|
||||
)
|
||||
/* No slaves */
|
||||
#define CFG_HRCW_SLAVE1 0
|
||||
#define CFG_HRCW_SLAVE2 0
|
||||
#define CFG_HRCW_SLAVE3 0
|
||||
#define CFG_HRCW_SLAVE4 0
|
||||
#define CFG_HRCW_SLAVE5 0
|
||||
#define CFG_HRCW_SLAVE6 0
|
||||
#define CFG_HRCW_SLAVE7 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CFG_IMMR 0xF0F00000
|
||||
#ifdef CFG_REV_B
|
||||
#define CFG_DEFAULT_IMMR 0xFF000000
|
||||
#endif /* CFG_REV_B */
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||
#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
|
||||
#define CFG_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */
|
||||
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* HIDx - Hardware Implementation-dependent Registers 2-11
|
||||
*-----------------------------------------------------------------------
|
||||
* HID0 also contains cache control.
|
||||
*
|
||||
* HID1 has only read-only information - nothing to set.
|
||||
*/
|
||||
#define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
|
||||
HID0_IFEM|HID0_ABE)
|
||||
#define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
|
||||
#define CFG_HID2 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5
|
||||
*-----------------------------------------------------------------------
|
||||
* turn on Checkstop Reset Enable
|
||||
*/
|
||||
#define CFG_RMR RMR_CSRE
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* BCR - Bus Configuration 4-25
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_BCR 0xA01C0000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 4-31
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_SIUMCR 0x42250000/* 0x4205C000 */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 4-35
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
|
||||
*/
|
||||
#if defined (CONFIG_WATCHDOG)
|
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
|
||||
#else
|
||||
#define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
|
||||
SYPCR_SWRI|SYPCR_SWP)
|
||||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
* and enable Time Counter
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
* Periodic timer
|
||||
*/
|
||||
#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock Control 9-8
|
||||
*-----------------------------------------------------------------------
|
||||
* Ensure DFBRG is Divide by 16
|
||||
*/
|
||||
#define CFG_SCCR SCCR_DFBRG01
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CFG_RCCR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* Bank Bus Machine PortSize Device
|
||||
* ---- --- ------- ----------------------------- ------
|
||||
* 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
|
||||
* 1 60x SDRAM 64 bit SDRAM
|
||||
* 2 Local SDRAM 32 bit SDRAM
|
||||
*/
|
||||
#define CFG_USE_FIRMWARE /* If defined - do not initialise memory
|
||||
controller, rely on initialisation
|
||||
performed by the Interphase boot firmware.
|
||||
*/
|
||||
|
||||
#define CFG_OR0_PRELIM 0xFE000882
|
||||
#ifdef CFG_REV_B
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_8 | BRx_V)
|
||||
#else /* Rev. D */
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | BRx_PS_16 | BRx_V)
|
||||
#endif /* CFG_REV_B */
|
||||
|
||||
#define CFG_MPTPR 0x7F00
|
||||
|
||||
/* Please note that 60x SDRAM MUST start at 0 */
|
||||
#define CFG_SDRAM_BASE 0x00000000
|
||||
#define CFG_60x_BR 0x00000041
|
||||
#define CFG_60x_OR 0xF0002CD0
|
||||
#define CFG_PSDMR 0x0049929A
|
||||
#define CFG_PSRT 0x07
|
||||
|
||||
#define CFG_LSDRAM_BASE 0xF7000000
|
||||
#define CFG_LOC_BR 0x00001861
|
||||
#define CFG_LOC_OR 0xFF803280
|
||||
#define CFG_LSDMR 0x8285A552
|
||||
#define CFG_LSRT 0x07
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user