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ARM: mx6: ddr: Add support for iMX6SX

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This patch adds support for iMX6SX MMDC into the DDR calibration
code. The only difference between MX6DQ and MX6SX is that the SX
has 2 SDQS registers, while the DQ has 8.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Eric Nelson <eric@nelint.com>
This commit is contained in:
Marek Vasut 2019-11-26 09:34:52 +01:00 committed by Stefano Babic
parent b314003fda
commit c35b19531d
1 changed files with 14 additions and 4 deletions
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18
arch/arm/mach-imx/mx6/ddr.c
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@ -247,12 +247,22 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
static void mmdc_set_sdqs(bool set) static void mmdc_set_sdqs(bool set)
{ {
struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux = struct mx6dq_iomux_ddr_regs *mx6dq_ddr_iomux =
(struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE; (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
u32 sdqs = (u32)(&mx6_ddr_iomux->dram_sdqs0); struct mx6sx_iomux_ddr_regs *mx6sx_ddr_iomux =
int i; (struct mx6sx_iomux_ddr_regs *)MX6SX_IOM_DDR_BASE;
int i, sdqs_cnt;
u32 sdqs;
for (i = 0; i < 8; i++) { if (is_mx6sx()) {
sdqs = (u32)(&mx6sx_ddr_iomux->dram_sdqs0);
sdqs_cnt = 2;
} else { /* MX6DQ */
sdqs = (u32)(&mx6dq_ddr_iomux->dram_sdqs0);
sdqs_cnt = 8;
}
for (i = 0; i < sdqs_cnt; i++) {
if (set) if (set)
setbits_le32(sdqs + (4 * i), 0x7000); setbits_le32(sdqs + (4 * i), 0x7000);
else else