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spl: introduce SPL_XIP to config

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U-Boot and SPL don't necessary share the same location, so we might end
with U-Boot SPL in read-only memory (XIP) and U-Boot in read-write memory.

In case of non XIP boot mode, we rely on such variables as "hart_lottery"
and "available_harts_lock" which we use as atomics.

The problem is that CONFIG_XIP also propagate to main U-Boot, not only SPL,
so we need CONFIG_SPL_XIP to distinguish SPL XIP from other XIP modes.

This adds an option special for SPL to behave it in XIP manner and we don't
use hart_lottery and available_harts_lock, during start proccess.

Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Nikita Shubin 2022-09-02 11:47:39 +03:00 committed by Leo Yu-Chi Liang
parent 435596d57f
commit c2bdf02c9d
8 changed files with 15 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/riscv/Kconfig
View File

@ -269,6 +269,13 @@ config XIP
from a NOR flash memory without copying the code to ram.
Say yes here if U-Boot boots from flash directly.
config SPL_XIP
bool "Enable XIP mode for SPL"
help
If SPL starts in read-only memory (XIP for example) then we shouldn't
rely on lock variables (for example hart_lottery and available_harts_lock),
this affects only SPL, other stages should proceed as non-XIP.
config SHOW_REGS
bool "Show registers on unhandled exception"

2
arch/riscv/cpu/cpu.c
View File

@ -19,7 +19,7 @@
* The variables here must be stored in the data section since they are used
* before the bss section is available.
*/
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
u32 hart_lottery __section(".data") = 0;
/*

4
arch/riscv/cpu/start.S
View File

@ -122,7 +122,7 @@ call_board_init_f_0:
call_harts_early_init:
jal harts_early_init
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
/*
* Pick hart to initialize global data and run U-Boot. The other harts
* wait for initialization to complete.
@ -152,7 +152,7 @@ call_harts_early_init:
/* save the boot hart id to global_data */
SREG tp, GD_BOOT_HART(gp)
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
la t0, available_harts_lock
amoswap.w.rl zero, zero, 0(t0)

2
arch/riscv/include/asm/global_data.h
View File

@ -27,7 +27,7 @@ struct arch_global_data {
#if CONFIG_IS_ENABLED(SMP)
struct ipi_data ipi[CONFIG_NR_CPUS];
#endif
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
ulong available_harts;
#endif
};

2
arch/riscv/lib/asm-offsets.c
View File

@ -16,7 +16,7 @@ int main(void)
{
DEFINE(GD_BOOT_HART, offsetof(gd_t, arch.boot_hart));
DEFINE(GD_FIRMWARE_FDT_ADDR, offsetof(gd_t, arch.firmware_fdt_addr));
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
DEFINE(GD_AVAILABLE_HARTS, offsetof(gd_t, arch.available_harts));
#endif

2
arch/riscv/lib/smp.c
View File

@ -45,7 +45,7 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
continue;
}
#ifndef CONFIG_XIP
#if !CONFIG_IS_ENABLED(XIP)
/* skip if hart is not available */
if (!(gd->arch.available_harts & (1 << reg)))
continue;

2
configs/ae350_rv32_spl_xip_defconfig
View File

@ -11,7 +11,7 @@ CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00

2
configs/ae350_rv64_spl_xip_defconfig
View File

@ -12,7 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000
CONFIG_TARGET_AX25_AE350=y
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
CONFIG_XIP=y
CONFIG_SPL_XIP=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe70