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riscv: cache: Implement dcache for cv1800b

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Add dcache operations invalidate_dcache_range and flush_dcache_range for
cv1800b.

Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Kongyang Liu 2024-03-10 00:54:57 +08:00 committed by Leo Yu-Chi Liang
parent ae800aa79a
commit c21dfcb556
2 changed files with 46 additions and 0 deletions
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1
arch/riscv/cpu/cv1800b/Makefile
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@ -4,3 +4,4 @@
obj-y += dram.o
obj-y += cpu.o
obj-y += cache.o

45
arch/riscv/cpu/cv1800b/cache.c Normal file
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@ -0,0 +1,45 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2024, Kongyang Liu <seashell11234455@gmail.com>
*/
#include <cpu_func.h>
/*
* dcache.ipa rs1 (invalidate)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01010 rs1 000 00000 0001011
*
* dcache.cpa rs1 (clean)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01001 rs1 000 00000 0001011
*
* dcache.cipa rs1 (clean then invalidate)
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000001 01011 rs1 000 00000 0001011
*
* sync.s
* | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
* 0000000 11001 00000 000 00000 0001011
*/
#define DCACHE_IPA_A0 ".long 0x02a5000b"
#define DCACHE_CPA_A0 ".long 0x0295000b"
#define DCACHE_CIPA_A0 ".long 0x02b5000b"
#define SYNC_S ".long 0x0190000b"
void invalidate_dcache_range(unsigned long start, unsigned long end)
{
register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
__asm__ __volatile__(DCACHE_IPA_A0);
__asm__ __volatile__(SYNC_S);
}
void flush_dcache_range(unsigned long start, unsigned long end)
{
register unsigned long i asm("a0") = start & ~(CONFIG_SYS_CACHELINE_SIZE - 1);
for (; i < end; i += CONFIG_SYS_CACHELINE_SIZE)
__asm__ __volatile__(DCACHE_CPA_A0);
__asm__ __volatile__(SYNC_S);
}