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pinctrl: rmobile: Add R8A77970 V3M PFC tables

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Add PFC tables for R8A77970 V3M SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Marek Vasut 2017-10-09 20:57:29 +02:00 committed by Marek Vasut
parent 2c150950b0
commit c106bb53ea
5 changed files with 2620 additions and 0 deletions
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11
drivers/pinctrl/renesas/Kconfig
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@ -28,4 +28,15 @@ config PINCTRL_PFC_R8A7796
the GPIO definitions and pin control functions for each available
multiplex function.
config PINCTRL_PFC_R8A77970
bool "Renesas RCar Gen3 R8A77970 pin control driver"
def_bool y if R8A77970
depends on PINCTRL_PFC
help
Support pin multiplexing control on Renesas RCar Gen3 R8A77970 SoCs.
The driver is controlled by a device tree node which contains both
the GPIO definitions and pin control functions for each available
multiplex function.
endif

1
drivers/pinctrl/renesas/Makefile
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@ -1,3 +1,4 @@
obj-$(CONFIG_PINCTRL_PFC) += pfc.o
obj-$(CONFIG_PINCTRL_PFC_R8A7795) += pfc-r8a7795.o
obj-$(CONFIG_PINCTRL_PFC_R8A7796) += pfc-r8a7796.o
obj-$(CONFIG_PINCTRL_PFC_R8A77970) += pfc-r8a77970.o

2585
drivers/pinctrl/renesas/pfc-r8a77970.c Normal file
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File diff suppressed because it is too large Load Diff

11
drivers/pinctrl/renesas/pfc.c
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@ -26,6 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
enum sh_pfc_model {
SH_PFC_R8A7795 = 0,
SH_PFC_R8A7796,
SH_PFC_R8A77970,
};
struct sh_pfc_pin_config {
@ -778,6 +779,10 @@ static int sh_pfc_pinctrl_probe(struct udevice *dev)
if (model == SH_PFC_R8A7796)
priv->pfc.info = &r8a7796_pinmux_info;
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77970
if (model == SH_PFC_R8A77970)
priv->pfc.info = &r8a77970_pinmux_info;
#endif
priv->pmx.pfc = &priv->pfc;
sh_pfc_init_ranges(&priv->pfc);
@ -798,6 +803,12 @@ static const struct udevice_id sh_pfc_pinctrl_ids[] = {
.compatible = "renesas,pfc-r8a7796",
.data = SH_PFC_R8A7796,
},
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A77970
{
.compatible = "renesas,pfc-r8a77970",
.data = SH_PFC_R8A77970,
},
#endif
{ },
};

12
drivers/pinctrl/renesas/sh_pfc.h
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@ -247,6 +247,7 @@ int sh_pfc_config_mux_for_gpio(struct udevice *dev, unsigned pin_selector);
extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
/* -----------------------------------------------------------------------------
* Helper macros to create pin and port lists
*/
@ -338,6 +339,11 @@ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
#define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
#define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
PORT_GP_CFG_4(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
@ -399,6 +405,12 @@ extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
#define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
#define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
PORT_GP_CFG_18(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
#define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
#define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
PORT_GP_CFG_21(bank, fn, sfx, cfg), \
PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \