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spi: cadence_qspi: move the sram partition in init

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There is no need to re-configure sram partition for every read/write for
better full use of sram for read or write. This patch divides the half
sram for read & half for write once at initialization.

Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This commit is contained in:
Vikas Manocha 2015-07-02 18:29:43 -07:00 committed by Jagan Teki
parent 51d558392b
commit c0535c0ef0
1 changed files with 5 additions and 11 deletions
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16
drivers/spi/cadence_qspi_apb.c
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@ -38,10 +38,7 @@
/* Controller sram size in word */
#define CQSPI_REG_SRAM_SIZE_WORD (128)
#define CQSPI_REG_SRAM_RESV_WORDS (2)
#define CQSPI_REG_SRAM_PARTITION_WR (1)
#define CQSPI_REG_SRAM_PARTITION_RD \
(CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2)
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
/* Transfer mode */
@ -538,6 +535,10 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
/* Configure the remap address register, no remap */
writel(0, plat->regbase + CQSPI_REG_REMAP);
/* Indirect mode configurations */
writel(CQSPI_REG_SRAM_PARTITION_RD,
plat->regbase + CQSPI_REG_SRAMPARTITION);
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
@ -700,10 +701,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
/* Configure SRAM partition for read. */
writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
CQSPI_REG_SRAMPARTITION);
/* Configure the opcode */
rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
@ -801,9 +798,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
writel(CQSPI_REG_SRAM_PARTITION_WR,
plat->regbase + CQSPI_REG_SRAMPARTITION);
/* Configure the opcode */
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);