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arm: at91: add support for mini-box picosam9g45 board
Bootlog:
U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21)
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 258000 Hz, block size 512
mci: setting clock 33024000 Hz, block size 512
reading u-boot.img
reading u-boot.img
U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000)
CPU: AT91SAM9G45
Crystal frequency: 12 MHz
CPU clock : 400 MHz
Master clock : 133.333 MHz
Watchdog enabled
DRAM: 256 MiB
WARNING: Caches not enabled
MMC: mci: 0
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 260416 Hz, block size 512
mci: setting clock 33333333 Hz, block size 512
reading uboot.env
In: serial
Out: serial
Err: serial
Net: macb0
Error: macb0 address not set.
Hit any key to stop autoboot: 0
U-Boot>
Signed-off-by: Erik van Luijk <evanluijk@interact.nl>
[add 'picosam9g45_defconfig' to MAINTAINERS]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Erik van Luijk
Andreas Bießmann
parent
c982f6b9bf
commit
bfc37f3cb8
@ -1105,6 +1105,7 @@ extern unsigned int __machine_arch_type;
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#define MACH_TYPE_UBISYS_P9D_EVP 3493
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#define MACH_TYPE_UBISYS_P9D_EVP 3493
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#define MACH_TYPE_ATDGP318 3494
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#define MACH_TYPE_ATDGP318 3494
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#define MACH_TYPE_OMAP5_SEVM 3777
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#define MACH_TYPE_OMAP5_SEVM 3777
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#define MACH_TYPE_PICOSAM9G45 3838
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#define MACH_TYPE_ARMADILLO_800EVA 3863
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#define MACH_TYPE_ARMADILLO_800EVA 3863
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#define MACH_TYPE_KZM9G 4140
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#define MACH_TYPE_KZM9G 4140
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#define MACH_TYPE_COLIBRI_T30 4493
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#define MACH_TYPE_COLIBRI_T30 4493
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@ -64,6 +64,11 @@ config TARGET_PM9G45
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bool "Ronetix pm9g45 board"
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bool "Ronetix pm9g45 board"
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select CPU_ARM926EJS
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select CPU_ARM926EJS
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config TARGET_PICOSAM9G45
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bool "Mini-box picosam9g45 board"
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select CPU_ARM926EJS
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select SUPPORT_SPL
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config TARGET_AT91SAM9N12EK
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config TARGET_AT91SAM9N12EK
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bool "Atmel AT91SAM9N12-EK board"
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bool "Atmel AT91SAM9N12-EK board"
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select CPU_ARM926EJS
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select CPU_ARM926EJS
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@ -155,6 +160,7 @@ source "board/egnite/ethernut5/Kconfig"
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source "board/esd/meesc/Kconfig"
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source "board/esd/meesc/Kconfig"
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source "board/esd/otc570/Kconfig"
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source "board/esd/otc570/Kconfig"
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source "board/eukrea/cpu9260/Kconfig"
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source "board/eukrea/cpu9260/Kconfig"
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source "board/mini-box/picosam9g45/Kconfig"
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source "board/ronetix/pm9261/Kconfig"
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source "board/ronetix/pm9261/Kconfig"
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source "board/ronetix/pm9263/Kconfig"
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source "board/ronetix/pm9263/Kconfig"
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source "board/ronetix/pm9g45/Kconfig"
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source "board/ronetix/pm9g45/Kconfig"
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12
board/mini-box/picosam9g45/Kconfig
Normal file
12
board/mini-box/picosam9g45/Kconfig
Normal file
@ -0,0 +1,12 @@
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if TARGET_PICOSAM9G45
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config SYS_BOARD
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default "picosam9g45"
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config SYS_VENDOR
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default "mini-box"
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config SYS_CONFIG_NAME
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default "picosam9g45"
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endif
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6
board/mini-box/picosam9g45/MAINTAINERS
Normal file
6
board/mini-box/picosam9g45/MAINTAINERS
Normal file
@ -0,0 +1,6 @@
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PICOSAM9G45 BOARD
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M: Erik van Luijk <evanluijk@interact.nl>
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S: Maintained
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F: board/mini-box/picosam9g45/
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F: include/configs/picosam9g45.h
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F: configs/picosam9g45_defconfig
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19
board/mini-box/picosam9g45/Makefile
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19
board/mini-box/picosam9g45/Makefile
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@ -0,0 +1,19 @@
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#
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# Makefile for mini-box PICOSAM9G45 (AT91SAM9G45) based board
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# (C) Copytight 2015 Inter Act B.V.
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#
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# Based on:
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# U-Boot file: board/atmel/at91sam9m10g45ek/Makefile
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#
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# (C) Copyright 2003-2008
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# (C) Copyright 2008
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# Stelian Pop <stelian@popies.net>
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# Lead Tech Design <www.leadtechdesign.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += picosam9g45.o
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obj-y += led.o
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25
board/mini-box/picosam9g45/led.c
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25
board/mini-box/picosam9g45/led.c
Normal file
@ -0,0 +1,25 @@
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/*
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/at91sam9g45.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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void coloured_LED_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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/* Enable clock */
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writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
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at91_set_gpio_output(CONFIG_GREEN_LED, 1);
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at91_set_gpio_value(CONFIG_GREEN_LED, 1);
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}
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354
board/mini-box/picosam9g45/picosam9g45.c
Normal file
354
board/mini-box/picosam9g45/picosam9g45.c
Normal file
@ -0,0 +1,354 @@
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/*
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* Board functions for mini-box PICOSAM9G45 (AT91SAM9G45) based board
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* (C) Copyright 2015 Inter Act B.V.
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*
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* Based on:
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* U-Boot file: board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
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* (C) Copyright 2007-2008
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* Stelian Pop <stelian@popies.net>
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* Lead Tech Design <www.leadtechdesign.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/at91sam9g45_matrix.h>
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#include <asm/arch/at91sam9_smc.h>
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/clk.h>
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#include <lcd.h>
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#include <linux/mtd/nand.h>
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#include <atmel_lcdc.h>
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#include <atmel_mci.h>
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#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
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#include <net.h>
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#endif
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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#if defined(CONFIG_SPL_BUILD)
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#include <spl.h>
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void at91_spl_board_init(void)
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{
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#ifdef CONFIG_SYS_USE_MMC
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at91_mci_hw_init();
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#endif
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}
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#include <asm/arch/atmel_mpddrc.h>
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static void ddr2_conf(struct atmel_mpddr *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_DQMS_SHARED |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
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ddr2->rtr = 0x24b;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
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1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
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1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
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struct atmel_mpddr ddr2;
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unsigned long csa;
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ddr2_conf(&ddr2);
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/* enable DDR2 clock */
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writel(AT91_PMC_DDR, &pmc->scer);
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/* Chip select 1 is for DDR2/SDRAM */
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csa = readl(&mat->ebicsa);
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csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
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csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
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writel(csa, &mat->ebicsa);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRSDRC0, ATMEL_BASE_CS6, &ddr2);
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ddr2_init(ATMEL_BASE_DDRSDRC1, ATMEL_BASE_CS1, &ddr2);
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}
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#endif
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#ifdef CONFIG_CMD_USB
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static void picosam9g45_usb_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
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at91_set_gpio_output(AT91_PIN_PD1, 0);
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at91_set_gpio_output(AT91_PIN_PD3, 0);
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}
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#endif
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#ifdef CONFIG_MACB
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static void picosam9g45_macb_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
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/* Enable clock */
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writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
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/*
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* Disable pull-up on:
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* RXDV (PA15) => PHY normal mode (not Test mode)
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* ERX0 (PA12) => PHY ADDR0
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* ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
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*
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* PHY has internal pull-down
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*/
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writel(pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA12) |
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pin_to_mask(AT91_PIN_PA13),
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&pioa->pudr);
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at91_phy_reset();
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/* Re-enable pull-up */
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writel(pin_to_mask(AT91_PIN_PA15) |
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pin_to_mask(AT91_PIN_PA12) |
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pin_to_mask(AT91_PIN_PA13),
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&pioa->puer);
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/* And the pins. */
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at91_macb_hw_init();
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}
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#endif
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#ifdef CONFIG_LCD
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vidinfo_t panel_info = {
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.vl_col = 480,
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.vl_row = 272,
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.vl_clk = 9000000,
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.vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
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ATMEL_LCDC_INVFRAME_NORMAL,
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.vl_bpix = 3,
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.vl_tft = 1,
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.vl_hsync_len = 45,
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.vl_left_margin = 1,
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.vl_right_margin = 1,
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.vl_vsync_len = 1,
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.vl_upper_margin = 40,
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.vl_lower_margin = 1,
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.mmio = ATMEL_BASE_LCDC,
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};
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void lcd_enable(void)
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{
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at91_set_A_periph(AT91_PIN_PE6, 1); /* power up */
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}
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void lcd_disable(void)
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{
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at91_set_A_periph(AT91_PIN_PE6, 0); /* power down */
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}
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static void picosam9g45_lcd_hw_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
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at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
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at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
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at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
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at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
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at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
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at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
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at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
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at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
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at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
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at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
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at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
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at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
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at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
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at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
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at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
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at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
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at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
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|
at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
|
||||||
|
at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
|
||||||
|
at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
|
||||||
|
|
||||||
|
writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
|
||||||
|
|
||||||
|
gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_LCD_INFO
|
||||||
|
#include <nand.h>
|
||||||
|
#include <version.h>
|
||||||
|
|
||||||
|
void lcd_show_board_info(void)
|
||||||
|
{
|
||||||
|
ulong dram_size;
|
||||||
|
int i;
|
||||||
|
char temp[32];
|
||||||
|
|
||||||
|
lcd_printf("%s\n", U_BOOT_VERSION);
|
||||||
|
lcd_printf("(C) 2015 Inter Act B.V.\n");
|
||||||
|
lcd_printf("support@interact.nl\n");
|
||||||
|
lcd_printf("%s CPU at %s MHz\n",
|
||||||
|
ATMEL_CPU_NAME,
|
||||||
|
strmhz(temp, get_cpu_clk_rate()));
|
||||||
|
|
||||||
|
dram_size = 0;
|
||||||
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
|
||||||
|
dram_size += gd->bd->bi_dram[i].size;
|
||||||
|
lcd_printf(" %ld MB SDRAM\n", dram_size >> 20);
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_LCD_INFO */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef CONFIG_GENERIC_ATMEL_MCI
|
||||||
|
int board_mmc_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
at91_mci_hw_init();
|
||||||
|
|
||||||
|
return atmel_mci_init((void *)ATMEL_BASE_MCI0);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
at91_seriald_hw_init();
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
gd->bd->bi_arch_number = MACH_TYPE_PICOSAM9G45;
|
||||||
|
|
||||||
|
/* adress of boot parameters */
|
||||||
|
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||||
|
|
||||||
|
#ifdef CONFIG_CMD_USB
|
||||||
|
picosam9g45_usb_hw_init();
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_HAS_DATAFLASH
|
||||||
|
at91_spi0_hw_init(1 << 0);
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_ATMEL_SPI
|
||||||
|
at91_spi0_hw_init(1 << 4);
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_MACB
|
||||||
|
picosam9g45_macb_hw_init();
|
||||||
|
#endif
|
||||||
|
#ifdef CONFIG_LCD
|
||||||
|
picosam9g45_lcd_hw_init();
|
||||||
|
#endif
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int dram_init(void)
|
||||||
|
{
|
||||||
|
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE)
|
||||||
|
+ get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void dram_init_banksize(void)
|
||||||
|
{
|
||||||
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||||
|
gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
|
||||||
|
PHYS_SDRAM_1_SIZE);
|
||||||
|
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
||||||
|
gd->bd->bi_dram[1].size = get_ram_size((long *)PHYS_SDRAM_2,
|
||||||
|
PHYS_SDRAM_2_SIZE);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_RESET_PHY_R
|
||||||
|
void reset_phy(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int board_eth_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
int rc = 0;
|
||||||
|
#ifdef CONFIG_MACB
|
||||||
|
rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
|
||||||
|
#endif
|
||||||
|
return rc;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* SPI chip select control */
|
||||||
|
#ifdef CONFIG_ATMEL_SPI
|
||||||
|
#include <spi.h>
|
||||||
|
|
||||||
|
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
|
||||||
|
{
|
||||||
|
return bus == 0 && cs < 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_cs_activate(struct spi_slave *slave)
|
||||||
|
{
|
||||||
|
switch (slave->cs) {
|
||||||
|
case 1:
|
||||||
|
at91_set_gpio_output(AT91_PIN_PB18, 0);
|
||||||
|
break;
|
||||||
|
case 0:
|
||||||
|
default:
|
||||||
|
at91_set_gpio_output(AT91_PIN_PB3, 0);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void spi_cs_deactivate(struct spi_slave *slave)
|
||||||
|
{
|
||||||
|
switch (slave->cs) {
|
||||||
|
case 1:
|
||||||
|
at91_set_gpio_output(AT91_PIN_PB18, 1);
|
||||||
|
break;
|
||||||
|
case 0:
|
||||||
|
default:
|
||||||
|
at91_set_gpio_output(AT91_PIN_PB3, 1);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* CONFIG_ATMEL_SPI */
|
||||||
12
configs/picosam9g45_defconfig
Normal file
12
configs/picosam9g45_defconfig
Normal file
@ -0,0 +1,12 @@
|
|||||||
|
CONFIG_ARM=y
|
||||||
|
CONFIG_ARCH_AT91=y
|
||||||
|
CONFIG_TARGET_PICOSAM9G45=y
|
||||||
|
CONFIG_SPL=y
|
||||||
|
CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
|
||||||
|
# CONFIG_CMD_BDI is not set
|
||||||
|
# CONFIG_CMD_IMI is not set
|
||||||
|
# CONFIG_CMD_IMLS is not set
|
||||||
|
# CONFIG_CMD_LOADS is not set
|
||||||
|
# CONFIG_CMD_FLASH is not set
|
||||||
|
# CONFIG_CMD_FPGA is not set
|
||||||
|
# CONFIG_CMD_SETEXPR is not set
|
||||||
211
include/configs/picosam9g45.h
Normal file
211
include/configs/picosam9g45.h
Normal file
@ -0,0 +1,211 @@
|
|||||||
|
/*
|
||||||
|
* Configuration settings for the mini-box PICOSAM9G45 board.
|
||||||
|
* (C) Copyright 2015 Inter Act B.V.
|
||||||
|
*
|
||||||
|
* Based on:
|
||||||
|
* U-Boot file: include/configs/at91sam9m10g45ek.h
|
||||||
|
* (C) Copyright 2007-2008
|
||||||
|
* Stelian Pop <stelian@popies.net>
|
||||||
|
* Lead Tech Design <www.leadtechdesign.com>
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: GPL-2.0+
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
#include <asm/hardware.h>
|
||||||
|
|
||||||
|
#define CONFIG_SYS_TEXT_BASE 0x23f00000
|
||||||
|
|
||||||
|
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
|
||||||
|
|
||||||
|
/* ARM asynchronous clock */
|
||||||
|
#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
|
||||||
|
#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
|
||||||
|
|
||||||
|
#define CONFIG_PICOSAM
|
||||||
|
|
||||||
|
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
|
||||||
|
#define CONFIG_SETUP_MEMORY_TAGS
|
||||||
|
#define CONFIG_INITRD_TAG
|
||||||
|
#define CONFIG_SKIP_LOWLEVEL_INIT
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
#define CONFIG_DISPLAY_CPUINFO
|
||||||
|
|
||||||
|
#define CONFIG_CMD_BOOTZ
|
||||||
|
#define CONFIG_OF_LIBFDT
|
||||||
|
|
||||||
|
#define CONFIG_SYS_GENERIC_BOARD
|
||||||
|
|
||||||
|
/* general purpose I/O */
|
||||||
|
#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
|
||||||
|
#define CONFIG_AT91_GPIO
|
||||||
|
#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */
|
||||||
|
|
||||||
|
/* serial console */
|
||||||
|
#define CONFIG_ATMEL_USART
|
||||||
|
#define CONFIG_USART_BASE ATMEL_BASE_DBGU
|
||||||
|
#define CONFIG_USART_ID ATMEL_ID_SYS
|
||||||
|
|
||||||
|
/* LCD */
|
||||||
|
#define CONFIG_LCD
|
||||||
|
#define LCD_BPP LCD_COLOR8
|
||||||
|
#define CONFIG_LCD_LOGO
|
||||||
|
#undef LCD_TEST_PATTERN
|
||||||
|
#define CONFIG_LCD_INFO
|
||||||
|
#define CONFIG_LCD_INFO_BELOW_LOGO
|
||||||
|
#define CONFIG_SYS_WHITE_ON_BLACK
|
||||||
|
#define CONFIG_ATMEL_LCD
|
||||||
|
#define CONFIG_ATMEL_LCD_RGB565
|
||||||
|
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
|
||||||
|
/* board specific(not enough SRAM) */
|
||||||
|
#define CONFIG_AT91SAM9G45_LCD_BASE 0x23E00000
|
||||||
|
|
||||||
|
/* LED */
|
||||||
|
#define CONFIG_AT91_LED
|
||||||
|
#define CONFIG_GREEN_LED AT91_PIN_PD31 /* this is the user1 led */
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 3
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BOOTP options
|
||||||
|
*/
|
||||||
|
#define CONFIG_BOOTP_BOOTFILESIZE
|
||||||
|
#define CONFIG_BOOTP_BOOTPATH
|
||||||
|
#define CONFIG_BOOTP_GATEWAY
|
||||||
|
#define CONFIG_BOOTP_HOSTNAME
|
||||||
|
|
||||||
|
/* Enable the watchdog */
|
||||||
|
#define CONFIG_AT91SAM9_WATCHDOG
|
||||||
|
#define CONFIG_HW_WATCHDOG
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Command line configuration.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* No NOR flash */
|
||||||
|
#define CONFIG_SYS_NO_FLASH
|
||||||
|
#define CONFIG_CMD_PING
|
||||||
|
#define CONFIG_CMD_DHCP
|
||||||
|
#define CONFIG_CMD_USB
|
||||||
|
|
||||||
|
/* SDRAM */
|
||||||
|
#define CONFIG_NR_DRAM_BANKS 2
|
||||||
|
#define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */
|
||||||
|
#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */
|
||||||
|
#define PHYS_SDRAM_2 ATMEL_BASE_CS6 /* on DDRSDRC0 */
|
||||||
|
#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */
|
||||||
|
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
|
||||||
|
|
||||||
|
#define CONFIG_SYS_INIT_SP_ADDR \
|
||||||
|
(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
|
||||||
|
|
||||||
|
/* MMC */
|
||||||
|
#define CONFIG_CMD_MMC
|
||||||
|
|
||||||
|
#ifdef CONFIG_CMD_MMC
|
||||||
|
#define CONFIG_MMC
|
||||||
|
#define CONFIG_GENERIC_MMC
|
||||||
|
#define CONFIG_GENERIC_ATMEL_MCI
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
|
||||||
|
#define CONFIG_CMD_FAT
|
||||||
|
#define CONFIG_DOS_PARTITION
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Ethernet */
|
||||||
|
#define CONFIG_MACB
|
||||||
|
#define CONFIG_RMII
|
||||||
|
#define CONFIG_NET_RETRY_COUNT 20
|
||||||
|
#define CONFIG_RESET_PHY_R
|
||||||
|
#define CONFIG_AT91_WANTS_COMMON_PHY
|
||||||
|
|
||||||
|
/* USB */
|
||||||
|
#define CONFIG_USB_EHCI
|
||||||
|
#define CONFIG_USB_EHCI_ATMEL
|
||||||
|
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
|
||||||
|
#define CONFIG_USB_STORAGE
|
||||||
|
|
||||||
|
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||||
|
#define CONFIG_SYS_MEMTEST_END 0x23e00000
|
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_USE_MMC
|
||||||
|
/* bootstrap + u-boot + env + linux in mmc */
|
||||||
|
#define FAT_ENV_INTERFACE "mmc"
|
||||||
|
/*
|
||||||
|
* We don't specify the part number, if device 0 has partition table, it means
|
||||||
|
* the first partition; it no partition table, then take whole device as a
|
||||||
|
* FAT file system.
|
||||||
|
*/
|
||||||
|
#define FAT_ENV_DEVICE_AND_PART "0"
|
||||||
|
#define FAT_ENV_FILE "uboot.env"
|
||||||
|
#define CONFIG_ENV_IS_IN_FAT
|
||||||
|
#define CONFIG_FAT_WRITE
|
||||||
|
#define CONFIG_ENV_SIZE 0x4000
|
||||||
|
|
||||||
|
#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
|
||||||
|
"root=/dev/mmcblk0p2 rw rootwait"
|
||||||
|
#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \
|
||||||
|
"fatload mmc 0:1 0x22000000 zImage; " \
|
||||||
|
"bootz 0x22000000 - 0x21000000"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200
|
||||||
|
|
||||||
|
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||||
|
#define CONFIG_SYS_CBSIZE 256
|
||||||
|
#define CONFIG_SYS_MAXARGS 16
|
||||||
|
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||||
|
+ sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||||
|
#define CONFIG_SYS_LONGHELP
|
||||||
|
#define CONFIG_CMDLINE_EDITING
|
||||||
|
#define CONFIG_AUTO_COMPLETE
|
||||||
|
#define CONFIG_SYS_HUSH_PARSER
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Size of malloc() pool
|
||||||
|
*/
|
||||||
|
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
|
||||||
|
|
||||||
|
/* Defines for SPL */
|
||||||
|
#define CONFIG_SPL_FRAMEWORK
|
||||||
|
#define CONFIG_SPL_TEXT_BASE 0x300000
|
||||||
|
#define CONFIG_SPL_MAX_SIZE 0x010000
|
||||||
|
#define CONFIG_SPL_STACK 0x310000
|
||||||
|
|
||||||
|
#define CONFIG_SPL_LIBCOMMON_SUPPORT
|
||||||
|
#define CONFIG_SPL_LIBGENERIC_SUPPORT
|
||||||
|
#define CONFIG_SPL_SERIAL_SUPPORT
|
||||||
|
#define CONFIG_SPL_GPIO_SUPPORT
|
||||||
|
#define CONFIG_SPL_WATCHDOG_SUPPORT
|
||||||
|
|
||||||
|
#define CONFIG_SYS_MONITOR_LEN 0x80000
|
||||||
|
|
||||||
|
#ifdef CONFIG_SYS_USE_MMC
|
||||||
|
|
||||||
|
#define CONFIG_SPL_BSS_START_ADDR 0x20000000
|
||||||
|
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
|
||||||
|
#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
|
||||||
|
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
|
||||||
|
|
||||||
|
#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
|
||||||
|
#define CONFIG_SPL_MMC_SUPPORT
|
||||||
|
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
|
||||||
|
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
|
||||||
|
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
|
||||||
|
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
|
||||||
|
#define CONFIG_SPL_FAT_SUPPORT
|
||||||
|
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||||
|
|
||||||
|
#define CONFIG_SPL_ATMEL_SIZE
|
||||||
|
#define CONFIG_SYS_MASTER_CLOCK 132096000
|
||||||
|
#define CONFIG_SYS_AT91_PLLA 0x20c73f03
|
||||||
|
#define CONFIG_SYS_MCKR 0x1301
|
||||||
|
#define CONFIG_SYS_MCKR_CSS 0x1302
|
||||||
|
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
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Reference in New Issue
Block a user