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sh: Add support Renesas SH7724
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Nobuhiro Iwamatsu
Nobuhiro Iwamatsu
parent
c67ce95433
commit
bead86a836
@ -44,6 +44,8 @@
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# include <asm/cpu_sh7722.h>
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#elif defined (CONFIG_CPU_SH7723)
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# include <asm/cpu_sh7723.h>
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#elif defined (CONFIG_CPU_SH7724)
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# include <asm/cpu_sh7724.h>
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#elif defined (CONFIG_CPU_SH7757)
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# include <asm/cpu_sh7757.h>
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#elif defined (CONFIG_CPU_SH7763)
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234
arch/sh/include/asm/cpu_sh7724.h
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234
arch/sh/include/asm/cpu_sh7724.h
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@ -0,0 +1,234 @@
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/*
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* (C) Copyright 2008, 2011 Renesas Solutions Corp.
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*
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* SH7724 Internal I/O register
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _ASM_CPU_SH7724_H_
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#define _ASM_CPU_SH7724_H_
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#define CACHE_OC_NUM_WAYS 4
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#define CCR_CACHE_INIT 0x0000090d
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/* EXP */
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#define TRA 0xFF000020
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#define EXPEVT 0xFF000024
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#define INTEVT 0xFF000028
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/* MMU */
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#define PTEH 0xFF000000
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#define PTEL 0xFF000004
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#define TTB 0xFF000008
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#define TEA 0xFF00000C
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#define MMUCR 0xFF000010
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#define PASCR 0xFF000070
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#define IRMCR 0xFF000078
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/* CACHE */
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#define CCR 0xFF00001C
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#define RAMCR 0xFF000074
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/* INTC */
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/* BSC */
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#define MMSELR 0xFF800020
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#define CMNCR 0xFEC10000
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#define CS0BCR 0xFEC10004
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#define CS2BCR 0xFEC10008
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#define CS4BCR 0xFEC10010
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#define CS5ABCR 0xFEC10014
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#define CS5BBCR 0xFEC10018
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#define CS6ABCR 0xFEC1001C
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#define CS6BBCR 0xFEC10020
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#define CS0WCR 0xFEC10024
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#define CS2WCR 0xFEC10028
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#define CS4WCR 0xFEC10030
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#define CS5AWCR 0xFEC10034
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#define CS5BWCR 0xFEC10038
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#define CS6AWCR 0xFEC1003C
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#define CS6BWCR 0xFEC10040
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#define RBWTCNT 0xFEC10054
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/* SBSC */
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#define SBSC_SDCR 0xFE400008
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#define SBSC_SDWCR 0xFE40000C
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#define SBSC_SDPCR 0xFE400010
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#define SBSC_RTCSR 0xFE400014
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#define SBSC_RTCNT 0xFE400018
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#define SBSC_RTCOR 0xFE40001C
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#define SBSC_RFCR 0xFE400020
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/* DSBC */
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#define DBKIND 0xFD000008
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#define DBSTATE 0xFD00000C
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#define DBEN 0xFD000010
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#define DBCMDCNT 0xFD000014
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#define DBCKECNT 0xFD000018
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#define DBCONF 0xFD000020
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#define DBTR0 0xFD000030
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#define DBTR1 0xFD000034
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#define DBTR2 0xFD000038
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#define DBTR3 0xFD00003C
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#define DBRFPDN0 0xFD000040
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#define DBRFPDN1 0xFD000044
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#define DBRFPDN2 0xFD000048
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#define DBRFSTS 0xFD00004C
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#define DBMRCNT 0xFD000060
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#define DBPDCNT0 0xFD000108
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/* DMAC */
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/* CPG */
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#define FRQCRA 0xA4150000
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#define FRQCRB 0xA4150004
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#define FRQCR FRQCRA
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#define VCLKCR 0xA4150004
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#define SCLKACR 0xA4150008
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#define SCLKBCR 0xA415000C
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#define IRDACLKCR 0xA4150018
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#define PLLCR 0xA4150024
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#define DLLFRQ 0xA4150050
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/* LOW POWER MODE */
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#define STBCR 0xA4150020
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#define MSTPCR0 0xA4150030
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#define MSTPCR1 0xA4150034
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#define MSTPCR2 0xA4150038
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/* RWDT */
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#define RWTCNT 0xA4520000
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#define RWTCSR 0xA4520004
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#define WTCNT RWTCNT
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/* TMU */
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#define TSTR 0xFFD80004
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#define TCOR0 0xFFD80008
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#define TCNT0 0xFFD8000C
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#define TCR0 0xFFD80010
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#define TCOR1 0xFFD80014
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#define TCNT1 0xFFD80018
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#define TCR1 0xFFD8001C
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#define TCOR2 0xFFD80020
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#define TCNT2 0xFFD80024
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#define TCR2 0xFFD80028
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/* TPU */
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/* CMT */
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#define CMSTR 0xA44A0000
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#define CMCSR 0xA44A0060
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#define CMCNT 0xA44A0064
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#define CMCOR 0xA44A0068
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/* MSIOF */
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/* SCIF */
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#define SCIF0_BASE 0xFFE00000
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#define SCIF1_BASE 0xFFE10000
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#define SCIF2_BASE 0xFFE20000
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#define SCIF3_BASE 0xa4e30000
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#define SCIF4_BASE 0xa4e40000
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#define SCIF5_BASE 0xa4e50000
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/* RTC */
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/* IrDA */
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/* KEYSC */
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/* USB */
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/* IIC */
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/* FLCTL */
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/* VPU */
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/* VIO(CEU) */
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/* VIO(VEU) */
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/* VIO(BEU) */
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/* 2DG */
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/* LCDC */
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/* VOU */
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/* TSIF */
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/* SIU */
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/* ATAPI */
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/* PFC */
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#define PACR 0xA4050100
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#define PBCR 0xA4050102
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#define PCCR 0xA4050104
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#define PDCR 0xA4050106
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#define PECR 0xA4050108
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#define PFCR 0xA405010A
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#define PGCR 0xA405010C
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#define PHCR 0xA405010E
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#define PJCR 0xA4050110
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#define PKCR 0xA4050112
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#define PLCR 0xA4050114
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#define PMCR 0xA4050116
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#define PNCR 0xA4050118
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#define PQCR 0xA405011A
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#define PRCR 0xA405011C
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#define PSCR 0xA405011E
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#define PTCR 0xA4050140
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#define PUCR 0xA4050142
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#define PVCR 0xA4050144
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#define PWCR 0xA4050146
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#define PXCR 0xA4050148
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#define PYCR 0xA405014A
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#define PZCR 0xA405014C
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#define PSELA 0xA405014E
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#define PSELB 0xA4050150
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#define PSELC 0xA4050152
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#define PSELD 0xA4050154
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#define PSELE 0xA4050156
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#define HIZCRA 0xA4050158
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#define HIZCRB 0xA405015A
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#define HIZCRC 0xA405015C
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#define HIZCRD 0xA405015E
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#define MSELCRA 0xA4050180
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#define MSELCRB 0xA4050182
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#define PULCR 0xA4050184
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#define DRVCRA 0xA405018A
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#define DRVCRB 0xA405018C
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/* I/O Port */
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#define PADR 0xA4050120
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#define PBDR 0xA4050122
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#define PCDR 0xA4050124
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#define PDDR 0xA4050126
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#define PEDR 0xA4050128
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#define PFDR 0xA405012A
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#define PGDR 0xA405012C
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#define PHDR 0xA405012E
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#define PJDR 0xA4050130
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#define PKDR 0xA4050132
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#define PLDR 0xA4050134
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#define PMDR 0xA4050136
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#define PNDR 0xA4050138
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#define PQDR 0xA405013A
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#define PRDR 0xA405013C
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#define PSDR 0xA405013E
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#define PTDR 0xA4050160
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#define PUDR 0xA4050162
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#define PVDR 0xA4050164
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#define PWDR 0xA4050166
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#define PYDR 0xA4050168
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#define PZDR 0xA405016A
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/* Ether */
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#define EDMR 0xA4600000
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/* UBC */
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/* H-UDI */
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#endif /* _ASM_CPU_SH7724_H_ */
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