mirror of
https://github.com/u-boot/u-boot.git
synced 2024-11-27 14:14:37 +08:00
- mvebu: Support for 2 new Armada 385 boards (Tony) - mvebu: Minor misc board enhancements (Tony) - kirkwood: Serial driver fixes (Kconfig & dtsi) (Tony) - cmd: return code when tlv_eeprom incorrectly called (Heinrich)
This commit is contained in:
Tom Rini
commit
be9399b399
@ -247,6 +247,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-385-atl-x530.dtb \
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armada-385-atl-x530DP.dtb \
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armada-385-db-88f6820-amc.dtb \
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armada-385-synology-ds116.dtb \
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armada-385-thecus-n2350.dtb \
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armada-385-turris-omnia.dtb \
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armada-388-clearfog.dtb \
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armada-388-gp.dtb \
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291
arch/arm/dts/armada-385-synology-ds116.dts
Normal file
291
arch/arm/dts/armada-385-synology-ds116.dts
Normal file
@ -0,0 +1,291 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for Synology DS116 NAS
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*
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* Copyright (C) 2017 Willy Tarreau <w@1wt.eu>
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*/
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/dts-v1/;
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#include "armada-385.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Synology DS116";
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compatible = "marvell,a385-gp", "marvell,armada385", "marvell,armada380";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; /* 1 GB */
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};
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soc {
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ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
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MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
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MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
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MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
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MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
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internal-regs {
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i2c@11000 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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};
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};
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serial@12000 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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serial@12100 {
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/* A PIC16F1829 is connected to uart1 at 9600 bps,
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* and takes single-character orders :
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* "1" : power off // already handled by the poweroff node
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* "2" : short beep
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* "3" : long beep
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* "4" : turn the power LED ON
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* "5" : flash the power LED
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* "6" : turn the power LED OFF
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* "7" : turn the status LED OFF
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* "8" : turn the status LED ON
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* "9" : flash the status LED
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* "A" : flash the motherboard LED (D8)
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* "B" : turn the motherboard LED OFF
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* "C" : hard reset
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*/
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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poweroff@12100 {
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compatible = "synology,power-off";
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reg = <0x12100 0x100>;
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clocks = <&coreclk 0>;
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};
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ethernet@70000 {
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pinctrl-names = "default";
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phy = <&phy0>;
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phy-mode = "sgmii";
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buffer-manager = <&bm>;
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bm,pool-long = <0>;
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status = "okay";
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};
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mdio@72004 {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins>;
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phy0: ethernet-phy@1 {
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reg = <1>;
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};
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};
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sata@a8000 {
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pinctrl-names = "default";
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pinctrl-0 = <&sata0_pins>;
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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sata0: sata-port@0 {
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reg = <0>;
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target-supply = <®_5v_sata0>;
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};
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};
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bm@c8000 {
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status = "okay";
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};
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usb3@f0000 {
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usb-phy = <&usb3_0_phy>;
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status = "okay";
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};
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usb3@f8000 {
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usb-phy = <&usb3_1_phy>;
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status = "okay";
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};
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};
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bm-bppi {
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status = "okay";
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};
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gpio-fan {
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compatible = "gpio-fan";
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gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>,
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<&gpio1 17 GPIO_ACTIVE_HIGH>,
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<&gpio1 16 GPIO_ACTIVE_HIGH>;
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gpio-fan,speed-map = < 0 0
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1500 1
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2500 2
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3000 3
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3400 4
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3700 5
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3900 6
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4000 7>;
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#cooling-cells = <2>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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/* The green part is on gpio0.20 which is also used by
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* sata0, and accesses to SATA disk 0 make it blink so it
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* doesn't need to be declared here.
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*/
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orange {
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gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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label = "ds116:orange:disk";
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default-state = "off";
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};
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};
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};
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usb3_0_phy: usb3_0_phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <®_usb3_0_vbus>;
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#phy-cells = <0>;
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};
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usb3_1_phy: usb3_1_phy {
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compatible = "usb-nop-xceiv";
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vcc-supply = <®_usb3_1_vbus>;
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#phy-cells = <0>;
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};
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reg_usb3_0_vbus: usb3-vbus0 {
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compatible = "regulator-fixed";
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regulator-name = "usb3-vbus0";
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pinctrl-names = "default";
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pinctrl-0 = <&xhci0_vbus_pins>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
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};
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reg_usb3_1_vbus: usb3-vbus1 {
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compatible = "regulator-fixed";
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regulator-name = "usb3-vbus1";
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pinctrl-names = "default";
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pinctrl-0 = <&xhci1_vbus_pins>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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enable-active-high;
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gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
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};
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reg_sata0: pwr-sata0 {
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compatible = "regulator-fixed";
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regulator-name = "pwr_en_sata0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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enable-active-high;
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regulator-boot-on;
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gpio = <&gpio0 15 GPIO_ACTIVE_HIGH>;
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};
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reg_5v_sata0: v5-sata0 {
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compatible = "regulator-fixed";
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regulator-name = "v5.0-sata0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <®_sata0>;
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};
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reg_12v_sata0: v12-sata0 {
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compatible = "regulator-fixed";
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regulator-name = "v12.0-sata0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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vin-supply = <®_sata0>;
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};
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};
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "macronix,mx25l6405d", "jedec,spi-nor";
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reg = <0>; /* Chip select 0 */
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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/* Note: there is a redboot partition table despite u-boot
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* being used. The names presented here are the same as those
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* found in the FIS directory. There is also a small device
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* tree in the last 64kB of the RedBoot partition which is not
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* enumerated. The MAC address and the serial number are listed
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* in the "vendor" partition.
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*/
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partition@0 {
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label = "RedBoot";
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reg = <0x00000000 0x000f0000>;
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read-only;
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};
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partition@c0000 {
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label = "zImage";
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reg = <0x000f0000 0x002d0000>;
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};
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partition@390000 {
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label = "rd.gz";
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reg = <0x003c0000 0x00410000>;
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};
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partition@7d0000 {
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label = "vendor";
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reg = <0x007d0000 0x00010000>;
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read-only;
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};
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partition@7e0000 {
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label = "RedBoot config";
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reg = <0x007e0000 0x00010000>;
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read-only;
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};
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partition@7f0000 {
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label = "FIS directory";
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reg = <0x007f0000 0x00010000>;
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read-only;
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};
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};
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};
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&pinctrl {
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/* use only one pin for UART1, as mpp20 is used by sata0 */
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uart1_pins: uart-pins-1 {
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marvell,pins = "mpp19";
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marvell,function = "ua1";
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};
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xhci0_vbus_pins: xhci0_vbus_pins {
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marvell,pins = "mpp58";
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marvell,function = "gpio";
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};
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xhci1_vbus_pins: xhci1_vbus_pins {
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marvell,pins = "mpp59";
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marvell,function = "gpio";
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};
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};
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446
arch/arm/dts/armada-385-thecus-n2350.dts
Normal file
446
arch/arm/dts/armada-385-thecus-n2350.dts
Normal file
@ -0,0 +1,446 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device Tree file for Thecus N2350 board
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*
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* Copyright (C) 2018-2023 Tony Dinh <mibodhi@gmail.com>
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* Copyright (C) 2018 Manuel Jung <manuel.jung@hotmail.com>
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||||
*/
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/dts-v1/;
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-385.dtsi"
|
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/ {
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model = "Thecus N2350";
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compatible = "thecus,n2350", "marvell,armada385";
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||||
aliases {
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ethernet0 = ð0;
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};
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|
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chosen {
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stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
|
||||
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
|
||||
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
|
||||
|
||||
};
|
||||
|
||||
usb3_0_phy: usb3_0_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&usb3_0_power>;
|
||||
};
|
||||
|
||||
usb3_1_phy: usb3_1_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
vcc-supply = <&usb3_1_power>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&pmx_power_button &pmx_copy_button &pmx_reset_button>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button@1 {
|
||||
label = "Power Button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
button@2 {
|
||||
label = "Copy Button";
|
||||
linux,code = <KEY_COPY>;
|
||||
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
button@3 {
|
||||
label = "Reset Button";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&pmx_sata1_white_led
|
||||
&pmx_sata1_red_led
|
||||
&pmx_sata2_white_led
|
||||
&pmx_sata2_red_led
|
||||
&pmx_sys_white_led
|
||||
&pmx_sys_red_led
|
||||
&pmx_pwr_blue_led
|
||||
&pmx_pwr_red_led
|
||||
&pmx_usb_white_led
|
||||
&pmx_usb_red_led>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
|
||||
white_sata1 {
|
||||
label = "n2350:white:sata1";
|
||||
gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "ide-disk1";
|
||||
};
|
||||
|
||||
red_sata1 {
|
||||
label = "n2350:red:sata1";
|
||||
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
white-sata2 {
|
||||
label = "n2350:white:sata2";
|
||||
gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
red-sata2 {
|
||||
label = "n2350:red:sata2";
|
||||
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
white-sys {
|
||||
label = "n2350:white:sys";
|
||||
gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
red-sys {
|
||||
label = "n2350:red:sys";
|
||||
gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
blue-pwr {
|
||||
label = "n2350:blue:pwr";
|
||||
gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
red-pwr {
|
||||
label = "n2350:red:pwr";
|
||||
gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
white-usb {
|
||||
label = "n2350:white:usb";
|
||||
gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
red-usb {
|
||||
label = "n2350:red:usb";
|
||||
gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
usb3_0_power: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "USB3_0_Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
usb3_1_power: regulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "USB3_1_Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_sata0: regulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata0: v5-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_12v_sata0: v12-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_sata1: regulator@4 {
|
||||
regulator-name = "pwr_en_sata1";
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata1: v5-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_12v_sata1: v12-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata1";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gpio-poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
pinctrl-0 = <&pmx_pwr_off>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&ahci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&bm_bppi {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð0 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
buffer-manager = <&bm>;
|
||||
bm,pool-long = <0>;
|
||||
bm,pool-short = <1>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
&nand_controller {
|
||||
status = "okay";
|
||||
|
||||
nand@0 {
|
||||
status = "okay";
|
||||
reg = <0>;
|
||||
label = "pxa3xx_nand-0";
|
||||
nand-rb = <0>;
|
||||
marvell,nand-keep-config;
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "rootfs";
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pciec {
|
||||
status = "okay";
|
||||
/*
|
||||
* The two PCIe units are accessible through
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pinctrl-names = "default";
|
||||
|
||||
pmx_power_button: pmx-power-button {
|
||||
marvell,pins = "mpp49";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_copy_button: pmx-copy-button {
|
||||
marvell,pins = "mpp52";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_reset_button: pmx-reset-button {
|
||||
marvell,pins = "mpp50";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_sata1_white_led: pmx-sata1-white-led {
|
||||
marvell,pins = "mpp20";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_sata1_red_led: pmx-sata1-red-led {
|
||||
marvell,pins = "mpp46";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_sata2_white_led: pmx-sata2-white-led {
|
||||
marvell,pins = "mpp19";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_sata2_red_led: pmx-sata2-red-led {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_sys_white_led: pmx-sys-white-led {
|
||||
marvell,pins = "mpp14";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_sys_red_led: pmx-sys-red-led {
|
||||
marvell,pins = "mpp15";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_buzzer: pmx-buzzer {
|
||||
marvell,pins = "mpp51";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_pwr_off: pmx-pwr-off {
|
||||
marvell,pins = "mpp54";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_pwr_blue_led: pmx-pwr-blue-led {
|
||||
marvell,pins = "mpp43";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_pwr_red_led: pmx-pwr-red-led {
|
||||
marvell,pins = "mpp18";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_usb_white_led: pmx-usb-white-led {
|
||||
marvell,pins = "mpp16";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
pmx_usb_red_led: pmx-usb-red-led {
|
||||
marvell,pins = "mpp17";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
broken-cd;
|
||||
wp-inverted;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
/* spi: 4M Flash Macronix MX25L3205D */
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "macronix,mx25l3205d", "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
|
||||
spi-max-frequency = <108000000>;
|
||||
spi-cpha;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x00000000 0x00100000>;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x00100000 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb3_1 {
|
||||
status = "okay";
|
||||
};
|
||||
7
arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
Normal file
7
arch/arm/dts/kirkwood-pogoplug-series-4-u-boot.dtsi
Normal file
@ -0,0 +1,7 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
*/
|
||||
&uart0 {
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
@ -15,6 +15,7 @@ config SHEEVA_88SV131
|
||||
config KIRKWOOD_COMMON
|
||||
bool
|
||||
select DM_SERIAL
|
||||
select SYS_NS16550
|
||||
|
||||
config HAS_CUSTOM_SYS_INIT_SP_ADDR
|
||||
bool "Use a custom location for the initial stack pointer address"
|
||||
|
||||
@ -97,6 +97,9 @@ config 88F6820
|
||||
config CUSTOMER_BOARD_SUPPORT
|
||||
bool
|
||||
|
||||
config DDR4
|
||||
bool "Support Marvell DDR4 Training driver"
|
||||
|
||||
choice
|
||||
prompt "Armada XP/375/38x/3700/7K/8K/Alleycat-5 board select"
|
||||
optional
|
||||
@ -166,6 +169,10 @@ config TARGET_DB_MV784MP_GP
|
||||
select BOARD_ECC_SUPPORT
|
||||
select MV78460
|
||||
|
||||
config TARGET_DS116
|
||||
bool "Support Synology DS116"
|
||||
select 88F6820
|
||||
|
||||
config TARGET_DS414
|
||||
bool "Support Synology DS414"
|
||||
select MV78230
|
||||
@ -175,6 +182,11 @@ config TARGET_MAXBCM
|
||||
select BOARD_ECC_SUPPORT
|
||||
select MV78460
|
||||
|
||||
config TARGET_N2350
|
||||
bool "Support Thecus N2350"
|
||||
select 88F6820
|
||||
select DDR4
|
||||
|
||||
config TARGET_THEADORABLE
|
||||
bool "Support theadorable Armada XP"
|
||||
select BOARD_LATE_INIT if USB
|
||||
@ -255,8 +267,10 @@ config SYS_BOARD
|
||||
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
|
||||
default "octeontx2_cn913x" if TARGET_OCTEONTX2_CN913x
|
||||
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
||||
default "ds116" if TARGET_DS116
|
||||
default "ds414" if TARGET_DS414
|
||||
default "maxbcm" if TARGET_MAXBCM
|
||||
default "n2350" if TARGET_N2350
|
||||
default "theadorable" if TARGET_THEADORABLE
|
||||
default "a38x" if TARGET_CONTROLCENTERDC
|
||||
default "x530" if TARGET_X530
|
||||
@ -274,8 +288,10 @@ config SYS_CONFIG_NAME
|
||||
default "mvebu_armada-8k" if TARGET_MVEBU_ARMADA_8K
|
||||
default "mvebu_armada-8k" if TARGET_OCTEONTX2_CN913x
|
||||
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
|
||||
default "ds116" if TARGET_DS116
|
||||
default "ds414" if TARGET_DS414
|
||||
default "maxbcm" if TARGET_MAXBCM
|
||||
default "n2350" if TARGET_N2350
|
||||
default "theadorable" if TARGET_THEADORABLE
|
||||
default "turris_omnia" if TARGET_TURRIS_OMNIA
|
||||
default "turris_mox" if TARGET_TURRIS_MOX
|
||||
@ -297,7 +313,9 @@ config SYS_VENDOR
|
||||
default "Marvell" if TARGET_MVEBU_DB_88F7040
|
||||
default "solidrun" if TARGET_CLEARFOG
|
||||
default "kobol" if TARGET_HELIOS4
|
||||
default "Synology" if TARGET_DS116
|
||||
default "Synology" if TARGET_DS414
|
||||
default "thecus" if TARGET_N2350
|
||||
default "CZ.NIC" if TARGET_TURRIS_OMNIA
|
||||
default "CZ.NIC" if TARGET_TURRIS_MOX
|
||||
default "gdsys" if TARGET_CONTROLCENTERDC
|
||||
|
||||
7
board/Synology/ds116/MAINTAINERS
Normal file
7
board/Synology/ds116/MAINTAINERS
Normal file
@ -0,0 +1,7 @@
|
||||
DS116 BOARD
|
||||
M: Tony Dinh <mibodhi@gmail.com>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/armada-385-synology-ds116.dts
|
||||
F: board/Synology/ds116/
|
||||
F: include/configs/ds116.h
|
||||
F: configs/ds116_defconfig
|
||||
6
board/Synology/ds116/Makefile
Normal file
6
board/Synology/ds116/Makefile
Normal file
@ -0,0 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
#
|
||||
|
||||
obj-y := ds116.o
|
||||
135
board/Synology/ds116/ds116.c
Normal file
135
board/Synology/ds116/ds116.c
Normal file
@ -0,0 +1,135 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <i2c.h>
|
||||
#include <init.h>
|
||||
#include <miiphy.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
|
||||
#include <../serdes/a38x/high_speed_env_spec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Those DS116_GPP_xx values and defines in board_serdes_map, and board_topology_map
|
||||
* are taken from Marvell U-Boot version
|
||||
* U-Boot 2013.01-g6cc0a6d (Marvell version: 2015_T1.0p16)
|
||||
*/
|
||||
#define DS116_GPP_OUT_ENA_LOW \
|
||||
(~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \
|
||||
BIT(10) | BIT(11) | BIT(15) | BIT(19) | BIT(22) | BIT(23) | \
|
||||
BIT(25) | BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
|
||||
#define DS116_GPP_OUT_ENA_MID \
|
||||
(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \
|
||||
BIT(16) | BIT(17) | BIT(18) | BIT(26) | BIT(27)))
|
||||
|
||||
#define DS116_GPP_OUT_VAL_LOW BIT(15)
|
||||
#define DS116_GPP_OUT_VAL_MID (BIT(26) | BIT(27))
|
||||
#define DS116_GPP_POL_LOW 0x0
|
||||
#define DS116_GPP_POL_MID 0x0
|
||||
|
||||
static struct serdes_map board_serdes_map[] = {
|
||||
{SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{SATA0, SERDES_SPEED_6_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
};
|
||||
|
||||
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
|
||||
{
|
||||
*serdes_map_array = board_serdes_map;
|
||||
*count = ARRAY_SIZE(board_serdes_map);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the DDR layout / topology here in the board file. This will
|
||||
* be used by the DDR3 init code in the SPL U-Boot version to configure
|
||||
* the DDR3 controller.
|
||||
*/
|
||||
static struct mv_ddr_topology_map board_topology_map = {
|
||||
DEBUG_LEVEL_ERROR,
|
||||
0x1, /* active interfaces */
|
||||
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
|
||||
{ { { {0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0} },
|
||||
SPEED_BIN_DDR_1866L, /* speed_bin */
|
||||
MV_DDR_DEV_WIDTH_16BIT, /* memory_width - 16 bits */
|
||||
MV_DDR_DIE_CAP_4GBIT, /* mem_size - DS116 board has 2x512MB DRAM banks */
|
||||
MV_DDR_FREQ_800, /* frequency */
|
||||
0, 0, /* cas_wl cas_l */
|
||||
MV_DDR_TEMP_LOW, /* temperature */
|
||||
MV_DDR_TIM_DEFAULT} }, /* timing */
|
||||
BUS_MASK_32BIT, /* Busses mask */
|
||||
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
|
||||
NOT_COMBINED, /* ddr twin-die combined */
|
||||
{ {0} }, /* raw spd data */
|
||||
{0} /* timing parameters */
|
||||
};
|
||||
|
||||
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
|
||||
{
|
||||
/* Return the board topology as defined in the board code */
|
||||
return &board_topology_map;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/*
|
||||
* Those MPP values are taken from the Marvell U-Boot version
|
||||
* U-Boot 2013.01-g6cc0a6d (Marvell version: 2015_T1.0p16)
|
||||
*/
|
||||
|
||||
/* Configure MPP */
|
||||
writel(0x00111111, MVEBU_MPP_BASE + 0x00);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x04);
|
||||
writel(0x11040330, MVEBU_MPP_BASE + 0x08);
|
||||
writel(0x00000011, MVEBU_MPP_BASE + 0x0c);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x10);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x14);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x18);
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
|
||||
|
||||
/* Set GPP Out value */
|
||||
writel(DS116_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(DS116_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(DS116_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(DS116_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(DS116_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(DS116_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
7
board/thecus/n2350/MAINTAINERS
Normal file
7
board/thecus/n2350/MAINTAINERS
Normal file
@ -0,0 +1,7 @@
|
||||
N2350 BOARD
|
||||
M: Tony Dinh <mibodhi@gmail.com>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/armada-385-thecus-n2350.dts
|
||||
F: board/thecus/n2350/
|
||||
F: include/configs/n2350.h
|
||||
F: configs/n2350_defconfig
|
||||
6
board/thecus/n2350/Makefile
Normal file
6
board/thecus/n2350/Makefile
Normal file
@ -0,0 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
# Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
#
|
||||
|
||||
obj-y := n2350.o
|
||||
126
board/thecus/n2350/n2350.c
Normal file
126
board/thecus/n2350/n2350.c
Normal file
@ -0,0 +1,126 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <asm/arch/soc.h>
|
||||
#include <linux/bitops.h>
|
||||
|
||||
#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
|
||||
#include <../serdes/a38x/high_speed_env_spec.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Those N2350_GPP_xx values and defines in board_serdes_map, and board_topology_map
|
||||
* are taken from the Marvell U-Boot version "u-boot-a38x-2015T1_p18_Thecus"
|
||||
*/
|
||||
|
||||
#define N2350_GPP_OUT_ENA_LOW (~(BIT(20) | BIT(21) | BIT(24)))
|
||||
#define N2350_GPP_OUT_ENA_MID (~(BIT(12) | BIT(13) | BIT(16) | BIT(19) | BIT(22)))
|
||||
#define N2350_GPP_OUT_VAL_LOW (BIT(21) | BIT(24))
|
||||
#define N2350_GPP_OUT_VAL_MID (BIT(0) | BIT(12) | BIT(13))
|
||||
#define N2350_GPP_POL_LOW 0x0
|
||||
#define N2350_GPP_POL_MID 0x0
|
||||
|
||||
static struct serdes_map board_serdes_map[] = {
|
||||
{ SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
{ USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
|
||||
};
|
||||
|
||||
int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
|
||||
{
|
||||
*serdes_map_array = board_serdes_map;
|
||||
*count = ARRAY_SIZE(board_serdes_map);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Define the DDR layout / topology here in the board file. This will
|
||||
* be used by the DDR4 init code in the SPL U-Boot version to configure
|
||||
* the DDR4 controller.
|
||||
*/
|
||||
|
||||
static struct mv_ddr_topology_map board_topology_map = {
|
||||
DEBUG_LEVEL_ERROR,
|
||||
0x1, /* active interfaces */
|
||||
/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
|
||||
{ { { {0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0},
|
||||
{0x1, 0, 0, 0} },
|
||||
SPEED_BIN_DDR_1866L, /* speed_bin */
|
||||
MV_DDR_DEV_WIDTH_16BIT, /* memory_width - 16 bits */
|
||||
MV_DDR_DIE_CAP_4GBIT, /* mem_size - N2350 board has 2x512MB DRAM banks */
|
||||
MV_DDR_FREQ_800, /* frequency */
|
||||
0, 0, /* cas_wl cas_l */
|
||||
MV_DDR_TEMP_LOW, /* temperature */
|
||||
MV_DDR_TIM_DEFAULT} }, /* timing */
|
||||
BUS_MASK_32BIT, /* Busses mask */
|
||||
MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
|
||||
NOT_COMBINED, /* ddr twin-die combined */
|
||||
{ {0} }, /* raw spd data */
|
||||
{0} /* timing parameters */
|
||||
};
|
||||
|
||||
struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
|
||||
{
|
||||
/* Return the board topology as defined in the board code */
|
||||
return &board_topology_map;
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
/* Those MPP values are taken from the Marvell U-Boot version
|
||||
* "u-boot-a38x-2015T1_p18_Thecus"
|
||||
*/
|
||||
|
||||
/* Configure MPP */
|
||||
writel(0x50111111, MVEBU_MPP_BASE + 0x00); /* MPP0_7 */
|
||||
writel(0x00555555, MVEBU_MPP_BASE + 0x04); /* MPP8_15 */
|
||||
writel(0x55000000, MVEBU_MPP_BASE + 0x08); /* MPP16_23 */
|
||||
writel(0x05050050, MVEBU_MPP_BASE + 0x0c); /* MPP24_31 */
|
||||
writel(0x05555555, MVEBU_MPP_BASE + 0x10); /* MPP32_39 */
|
||||
writel(0x00000565, MVEBU_MPP_BASE + 0x14); /* MPP40_47 */
|
||||
writel(0x00000000, MVEBU_MPP_BASE + 0x18); /* MPP48_55 */
|
||||
writel(0x00004444, MVEBU_MPP_BASE + 0x1c); /* MPP56_63 */
|
||||
|
||||
/* Set GPP Out value */
|
||||
writel(N2350_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
|
||||
writel(N2350_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
|
||||
|
||||
/* Set GPP Polarity */
|
||||
writel(N2350_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
|
||||
writel(N2350_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
|
||||
|
||||
/* Set GPP Out Enable */
|
||||
writel(N2350_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
|
||||
writel(N2350_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
/* Address of boot parameters */
|
||||
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(struct bd_info *bis)
|
||||
{
|
||||
cpu_eth_init(bis); /* Built in controller(s) come first */
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
@ -479,17 +479,14 @@ int do_tlv_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
show_tlv_devices();
|
||||
break;
|
||||
default:
|
||||
cmd_usage(cmdtp);
|
||||
break;
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
// The set command takes one or two args.
|
||||
if (argc > 4) {
|
||||
cmd_usage(cmdtp);
|
||||
return 0;
|
||||
}
|
||||
if (argc > 4)
|
||||
return CMD_RET_USAGE;
|
||||
|
||||
// Set command. If the TLV exists in the EEPROM, delete it. Then if
|
||||
// data was supplied for this TLV add the TLV with the new contents at
|
||||
@ -512,7 +509,7 @@ int do_tlv_eeprom(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
|
||||
current_dev = devnum;
|
||||
has_been_read = 0;
|
||||
} else {
|
||||
cmd_usage(cmdtp);
|
||||
return CMD_RET_USAGE;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
92
configs/ds116_defconfig
Normal file
92
configs/ds116_defconfig
Normal file
@ -0,0 +1,92 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_SYS_THUMB_BUILD=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_CMDLINE_TAG=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x00800000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_TARGET_DS116=y
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x7E0000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-385-synology-ds116"
|
||||
CONFIG_SPL_TEXT_BASE=0x40000030
|
||||
CONFIG_SYS_PROMPT="DS116> "
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xf1012000
|
||||
CONFIG_DEBUG_UART_CLOCK=250000000
|
||||
CONFIG_IDENT_STRING="\nSynology DS116"
|
||||
CONFIG_SYS_LOAD_ADDR=0x800000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x22fd0
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x40023000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_STACK=0x4002c000
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SYS_MAXARGS=32
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPIO_READ=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_DNS=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi0.0:1m(u-boot),7040k(kernel),64k(u-boot-env),-(data)"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_ARP_TIMEOUT=200
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_SYS_64BIT_LBA=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MVTWSI=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_SF_DEFAULT_SPEED=50000000
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MVNETA=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_MVMDIO=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MVEBU=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_ARMADA_38X=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_ARMADA38X=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_KIRKWOOD_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
93
configs/n2350_defconfig
Normal file
93
configs/n2350_defconfig
Normal file
@ -0,0 +1,93 @@
|
||||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_CPU_INIT=y
|
||||
CONFIG_SYS_THUMB_BUILD=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_SUPPORT_PASSING_ATAGS=y
|
||||
CONFIG_CMDLINE_TAG=y
|
||||
CONFIG_INITRD_TAG=y
|
||||
CONFIG_TEXT_BASE=0x00800000
|
||||
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
||||
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
||||
CONFIG_NR_DRAM_BANKS=2
|
||||
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
|
||||
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xff0000
|
||||
CONFIG_TARGET_N2350=y
|
||||
CONFIG_ENV_SIZE=0x10000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-385-thecus-n2350"
|
||||
CONFIG_SPL_TEXT_BASE=0x40000030
|
||||
CONFIG_SYS_PROMPT="N2350 > "
|
||||
CONFIG_SPL_SERIAL=y
|
||||
CONFIG_SPL_STACK=0x4002c000
|
||||
CONFIG_SPL=y
|
||||
CONFIG_DEBUG_UART_BASE=0xf1012000
|
||||
CONFIG_DEBUG_UART_CLOCK=250000000
|
||||
CONFIG_IDENT_STRING="\nThecus N2350"
|
||||
CONFIG_SYS_LOAD_ADDR=0x800000
|
||||
CONFIG_ENV_ADDR=0x100000
|
||||
CONFIG_DEBUG_UART=y
|
||||
CONFIG_AHCI=y
|
||||
CONFIG_DISTRO_DEFAULTS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_USE_PREBOOT=y
|
||||
CONFIG_SYS_CONSOLE_INFO_QUIET=y
|
||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
||||
CONFIG_DISPLAY_BOARDINFO_LATE=y
|
||||
CONFIG_SPL_MAX_SIZE=0x22fd0
|
||||
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
|
||||
CONFIG_SPL_BSS_START_ADDR=0x40023000
|
||||
CONFIG_SPL_BSS_MAX_SIZE=0x4000
|
||||
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
|
||||
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
|
||||
CONFIG_SPL_I2C=y
|
||||
CONFIG_SYS_MAXARGS=32
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_GPIO_READ=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SPI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_TFTPPUT=y
|
||||
CONFIG_CMD_SNTP=y
|
||||
CONFIG_CMD_DNS=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_TIME=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=pxa3xx_nand-0:-(rootfs);spi1.0:1M(u-boot),64K@1M(u-boot-env),-(data)"
|
||||
CONFIG_ENV_OVERWRITE=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_VERSION_VARIABLE=y
|
||||
CONFIG_ARP_TIMEOUT=200
|
||||
CONFIG_NET_RETRY_COUNT=50
|
||||
CONFIG_NET_RANDOM_ETHADDR=y
|
||||
CONFIG_NETCONSOLE=y
|
||||
CONFIG_SPL_OF_TRANSLATE=y
|
||||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_LBA48=y
|
||||
CONFIG_SYS_64BIT_LBA=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_MVTWSI=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_SF_DEFAULT_SPEED=50000000
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_MVNETA=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_MVMDIO=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MVEBU=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_ARMADA_38X=y
|
||||
CONFIG_DM_RTC=y
|
||||
CONFIG_RTC_ARMADA38X=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_SPL_DEBUG_UART_BASE=0xd0012000
|
||||
CONFIG_DEBUG_UART_SHIFT=2
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_KIRKWOOD_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
@ -26,6 +26,11 @@ CONFIG_USE_PREBOOT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_SYS_MAXARGS=32
|
||||
CONFIG_CMD_BOOTZ=y
|
||||
# CONFIG_BOOTM_PLAN9 is not set
|
||||
# CONFIG_BOOTM_RTEMS is not set
|
||||
# CONFIG_BOOTM_VXWORKS is not set
|
||||
# CONFIG_CMD_IMI is not set
|
||||
# CONFIG_CMD_XIMG is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_NAND=y
|
||||
|
||||
56
include/configs/ds116.h
Normal file
56
include/configs/ds116.h
Normal file
@ -0,0 +1,56 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_DS116_H
|
||||
#define _CONFIG_DS116_H
|
||||
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
|
||||
/* Keep device tree and initrd in lower memory so the kernel can access them */
|
||||
#define RELOCATION_LIMITS_ENV_SETTINGS \
|
||||
"fdt_high=0x10000000\0" \
|
||||
"initrd_high=0x10000000\0"
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/* Include the common distro boot environment */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(USB, usb, 0) \
|
||||
func(SCSI, scsi, 0) \
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#define KERNEL_ADDR_R __stringify(0x1000000)
|
||||
#define FDT_ADDR_R __stringify(0x2000000)
|
||||
#define RAMDISK_ADDR_R __stringify(0x2200000)
|
||||
#define SCRIPT_ADDR_R __stringify(0x1800000)
|
||||
#define PXEFILE_ADDR_R __stringify(0x1900000)
|
||||
|
||||
#define LOAD_ADDRESS_ENV_SETTINGS \
|
||||
"kernel_addr_r=" KERNEL_ADDR_R "\0" \
|
||||
"fdt_addr_r=" FDT_ADDR_R "\0" \
|
||||
"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
|
||||
"scriptaddr=" SCRIPT_ADDR_R "\0" \
|
||||
"pxefile_addr_r=" PXEFILE_ADDR_R "\0"
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
RELOCATION_LIMITS_ENV_SETTINGS \
|
||||
LOAD_ADDRESS_ENV_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
|
||||
"console=ttyS0,115200\0" \
|
||||
BOOTENV
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
#endif /* _CONFIG_DS116_H */
|
||||
56
include/configs/n2350.h
Normal file
56
include/configs/n2350.h
Normal file
@ -0,0 +1,56 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright (C) 2023 Tony Dinh <mibodhi@gmail.com>
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _CONFIG_N2350_H
|
||||
#define _CONFIG_N2350_H
|
||||
|
||||
#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
|
||||
|
||||
/* Keep device tree and initrd in lower memory so the kernel can access them */
|
||||
#define RELOCATION_LIMITS_ENV_SETTINGS \
|
||||
"fdt_high=0x10000000\0" \
|
||||
"initrd_high=0x10000000\0"
|
||||
|
||||
/*
|
||||
* mv-common.h should be defined after CMD configs since it used them
|
||||
* to enable certain macros
|
||||
*/
|
||||
#include "mv-common.h"
|
||||
|
||||
/* Include the common distro boot environment */
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
|
||||
#define BOOT_TARGET_DEVICES(func) \
|
||||
func(SCSI, scsi, 0) \
|
||||
func(USB, usb, 0) \
|
||||
func(PXE, pxe, na) \
|
||||
func(DHCP, dhcp, na)
|
||||
|
||||
#define KERNEL_ADDR_R __stringify(0x1000000)
|
||||
#define FDT_ADDR_R __stringify(0x2000000)
|
||||
#define RAMDISK_ADDR_R __stringify(0x2200000)
|
||||
#define SCRIPT_ADDR_R __stringify(0x1800000)
|
||||
#define PXEFILE_ADDR_R __stringify(0x1900000)
|
||||
|
||||
#define LOAD_ADDRESS_ENV_SETTINGS \
|
||||
"kernel_addr_r=" KERNEL_ADDR_R "\0" \
|
||||
"fdt_addr_r=" FDT_ADDR_R "\0" \
|
||||
"ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \
|
||||
"scriptaddr=" SCRIPT_ADDR_R "\0" \
|
||||
"pxefile_addr_r=" PXEFILE_ADDR_R "\0"
|
||||
|
||||
#include <config_distro_bootcmd.h>
|
||||
|
||||
#define CFG_EXTRA_ENV_SETTINGS \
|
||||
RELOCATION_LIMITS_ENV_SETTINGS \
|
||||
LOAD_ADDRESS_ENV_SETTINGS \
|
||||
"fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
|
||||
"console=ttyS0,115200\0" \
|
||||
BOOTENV
|
||||
|
||||
#endif /* CONFIG_SPL_BUILD */
|
||||
|
||||
#endif /* _CONFIG_N2350_H */
|
||||
Loading…
Reference in New Issue
Block a user