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dm: tegra: Enable driver model in SPL and adjust the GPIO driver

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Use the full driver model GPIO and serial drivers in SPL now that these are
supported. Since device tree is not available they will use platform data.

Remove the special SPL GPIO function as it is no longer needed.

This is all in one commit to maintain bisectability.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2015-03-03 08:02:59 -07:00 committed by Tom Rini
parent fc8fdc76e7
commit bdfb34167f
5 changed files with 19 additions and 25 deletions
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3
arch/arm/mach-tegra/Kconfig
View File

@ -29,6 +29,9 @@ config USE_PRIVATE_LIBGCC
config DM
default y
config SPL_DM
default y
config DM_SERIAL
default y

4
board/nvidia/seaboard/seaboard.c
View File

@ -20,10 +20,8 @@
void gpio_early_init_uart(void)
{
/* Enable UART via GPIO_PI3 (port 8, bit 3) so serial console works */
#ifndef CONFIG_SPL_BUILD
gpio_request(GPIO_PI3, NULL);
#endif
tegra_spl_gpio_direction_output(GPIO_PI3, 0);
gpio_direction_output(GPIO_PI3, 0);
}
#endif

4
drivers/gpio/Makefile
View File

@ -8,6 +8,10 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
endif
/* TODO(sjg@chromium.org): Only tegra supports driver model in SPL */
ifdef CONFIG_TEGRA_GPIO
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
endif
obj-$(CONFIG_AT91_GPIO) += at91_gpio.o
obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o

27
drivers/gpio/tegra_gpio.c
View File

@ -132,21 +132,6 @@ static void set_level(unsigned gpio, int high)
writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
}
/* set GPIO pin 'gpio' as an output, with polarity 'value' */
int tegra_spl_gpio_direction_output(int gpio, int value)
{
/* Configure as a GPIO */
set_config(gpio, 1);
/* Configure GPIO output value. */
set_level(gpio, value);
/* Configure GPIO direction as output. */
set_direction(gpio, 1);
return 0;
}
/*
* Generic_GPIO primitives.
*/
@ -338,12 +323,19 @@ static int gpio_tegra_bind(struct udevice *parent)
int bank_count;
int bank;
int ret;
int len;
/* If this is a child device, there is nothing to do here */
if (plat)
return 0;
/* TODO(sjg@chromium.org): Remove once SPL supports device tree */
#ifdef CONFIG_SPL_BUILD
ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
bank_count = TEGRA_GPIO_BANKS;
#else
{
int len;
/*
* This driver does not make use of interrupts, other than to figure
* out the number of GPIO banks
@ -353,6 +345,8 @@ static int gpio_tegra_bind(struct udevice *parent)
bank_count = len / 3 / sizeof(u32);
ctlr = (struct gpio_ctlr *)fdtdec_get_addr(gd->fdt_blob,
parent->of_offset, "reg");
}
#endif
for (bank = 0; bank < bank_count; bank++) {
int port;
@ -388,4 +382,5 @@ U_BOOT_DRIVER(gpio_tegra) = {
.probe = gpio_tegra_probe,
.priv_auto_alloc_size = sizeof(struct tegra_port_info),
.ops = &gpio_tegra_ops,
.flags = DM_FLAG_PRE_RELOC,
};

6
include/configs/tegra-common.h
View File

@ -43,13 +43,7 @@
/*
* NS16550 Configuration
*/
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
#else
#define CONFIG_TEGRA_SERIAL
#endif
#define CONFIG_SYS_NS16550
/*