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riscv: timer: Add support for an early timer

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Added support for timer_early_get_count() and timer_early_get_rate()
This is mostly useful in tracing.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
This commit is contained in:
Pragnesh Patel 2021-01-17 18:11:25 +05:30 committed by Andes
parent a80f85138c
commit bc8d12bfd8
6 changed files with 75 additions and 3 deletions
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21
drivers/timer/andes_plmt_timer.c
View File

@ -18,11 +18,30 @@
/* mtime register */
#define MTIME_REG(base) ((ulong)(base))
static u64 andes_plmt_get_count(struct udevice *dev)
static u64 notrace andes_plmt_get_count(struct udevice *dev)
{
return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
}
#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
/**
* timer_early_get_rate() - Get the timer rate before driver model
*/
unsigned long notrace timer_early_get_rate(void)
{
return RISCV_MMODE_TIMER_FREQ;
}
/**
* timer_early_get_count() - Get the timer count before driver model
*
*/
u64 notrace timer_early_get_count(void)
{
return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
}
#endif
static const struct timer_ops andes_plmt_ops = {
.get_count = andes_plmt_get_count,
};

21
drivers/timer/riscv_timer.c
View File

@ -16,7 +16,7 @@
#include <timer.h>
#include <asm/csr.h>
static u64 riscv_timer_get_count(struct udevice *dev)
static u64 notrace riscv_timer_get_count(struct udevice *dev)
{
__maybe_unused u32 hi, lo;
@ -31,6 +31,25 @@ static u64 riscv_timer_get_count(struct udevice *dev)
return ((u64)hi << 32) | lo;
}
#if CONFIG_IS_ENABLED(RISCV_SMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
/**
* timer_early_get_rate() - Get the timer rate before driver model
*/
unsigned long notrace timer_early_get_rate(void)
{
return RISCV_SMODE_TIMER_FREQ;
}
/**
* timer_early_get_count() - Get the timer count before driver model
*
*/
u64 notrace timer_early_get_count(void)
{
return riscv_timer_get_count(NULL);
}
#endif
static int riscv_timer_probe(struct udevice *dev)
{
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);

21
drivers/timer/sifive_clint_timer.c
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@ -15,11 +15,30 @@
/* mtime register */
#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
static u64 sifive_clint_get_count(struct udevice *dev)
static u64 notrace sifive_clint_get_count(struct udevice *dev)
{
return readq((void __iomem *)MTIME_REG(dev_get_priv(dev)));
}
#if CONFIG_IS_ENABLED(RISCV_MMODE) && IS_ENABLED(CONFIG_TIMER_EARLY)
/**
* timer_early_get_rate() - Get the timer rate before driver model
*/
unsigned long notrace timer_early_get_rate(void)
{
return RISCV_MMODE_TIMER_FREQ;
}
/**
* timer_early_get_count() - Get the timer count before driver model
*
*/
u64 notrace timer_early_get_count(void)
{
return readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE));
}
#endif
static const struct timer_ops sifive_clint_ops = {
.get_count = sifive_clint_get_count,
};

5
include/configs/ax25-ae350.h
View File

@ -17,6 +17,11 @@
#endif
#endif
#define RISCV_MMODE_TIMERBASE 0xe6000000
#define RISCV_MMODE_TIMER_FREQ 60000000
#define RISCV_SMODE_TIMER_FREQ 60000000
/*
* CPU and Board Configuration Options
*/

5
include/configs/qemu-riscv.h
View File

@ -29,6 +29,11 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMER_FREQ 1000000
#define RISCV_SMODE_TIMER_FREQ 1000000
/* Environment options */
#ifndef CONFIG_SPL_BUILD

5
include/configs/sifive-fu540.h
View File

@ -36,6 +36,11 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
#define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMER_FREQ 1000000
#define RISCV_SMODE_TIMER_FREQ 1000000
/* Environment options */
#ifndef CONFIG_SPL_BUILD