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armv8: layerscape: move TZASC and TZPC configs to Kconfig

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Moves FSL_TZASC_400 and FSL_TZPC_BP147 configs to Kconfig
for LS1088A and LS2088A platforms.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Rajesh Bhagat 2019-01-20 05:30:06 +00:00 committed by Prabhakar Kushwaha
parent a860806005
commit bbf5b25282
4 changed files with 9 additions and 6 deletions
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9
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -113,6 +113,8 @@ config ARCH_LS1088A
select SYS_FSL_SRDS_1
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_400
select FSL_TZPC_BP147
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
@ -145,6 +147,8 @@ config ARCH_LS2080A
select SYS_FSL_SRDS_2
select FSL_TZASC_1
select FSL_TZASC_2
select FSL_TZASC_400
select FSL_TZPC_BP147
select SYS_FSL_ERRATUM_A008336 if !TFABOOT
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008514 if !TFABOOT
@ -410,6 +414,11 @@ config FSL_TZASC_1
config FSL_TZASC_2
bool
config FSL_TZASC_400
bool
config FSL_TZPC_BP147
bool
endmenu
menu "Layerscape clock tree configuration"

3
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -26,7 +26,6 @@
#ifndef L1_CACHE_BYTES
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#define CONFIG_FSL_TZASC_400
#endif
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@ -121,8 +120,6 @@
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#define CONFIG_FSL_TZASC_400
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4

1
include/configs/ls2080a_common.h
View File

@ -10,7 +10,6 @@
#define CONFIG_REMAKE_ELF
#define CONFIG_FSL_LAYERSCAPE
#define CONFIG_GICV3
#define CONFIG_FSL_TZPC_BP147
#include <asm/arch/stream_id_lsch3.h>
#include <asm/arch/config.h>

2
scripts/config_whitelist.txt
View File

@ -670,8 +670,6 @@ CONFIG_FSL_SGMII_RISER
CONFIG_FSL_SPI_INTERFACE
CONFIG_FSL_TBCLK_EXTRA_DIV
CONFIG_FSL_TRUST_ARCH_v1
CONFIG_FSL_TZASC_400
CONFIG_FSL_TZPC_BP147
CONFIG_FSL_USDHC
CONFIG_FSL_VIA
CONFIG_FSMC_NAND_BASE