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pci: tegra: port to standard clock/reset/pwr domain APIs
Tegra186 supports the new standard clock, reset, and power domain APIs. Older Tegra SoCs still use custom APIs. Enhance the Tegra PCIe driver so that it can operate with either set of APIs. On Tegra186, the BPMP handles all aspects of PCIe PHY (UPHY) programming. Consequently, this logic is disabled too. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren
Tom Warren
parent
c04930762d
commit
bbc5b36b25
@ -31,6 +31,7 @@ config PCI_SANDBOX
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config PCI_TEGRA
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bool "Tegra PCI support"
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depends on TEGRA
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depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
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help
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Enable support for the PCIe controller found on some generations of
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Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
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@ -13,22 +13,35 @@
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#define pr_fmt(fmt) "tegra-pcie: " fmt
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <malloc.h>
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#include <pci.h>
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#include <power-domain.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <linux/list.h>
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#ifndef CONFIG_TEGRA186
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#include <asm/arch/clock.h>
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#include <asm/arch/powergate.h>
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#include <asm/arch-tegra/xusb-padctl.h>
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#include <linux/list.h>
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#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
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#endif
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/*
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* FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that
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* should not be present. These are needed because newer Tegra SoCs support
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* only the standard clock/reset APIs, whereas older Tegra SoCs support only
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* a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
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* fixed to implement the standard APIs, and all drivers converted to solely
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* use the new standard APIs, with no ifdefs.
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*/
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DECLARE_GLOBAL_DATA_PTR;
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@ -103,6 +116,9 @@ DECLARE_GLOBAL_DATA_PTR;
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401 (0x0 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211 (0x1 << 20)
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#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111 (0x2 << 20)
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#define AFI_FUSE 0x104
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#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
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@ -110,6 +126,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define AFI_PEX0_CTRL 0x110
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#define AFI_PEX1_CTRL 0x118
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#define AFI_PEX2_CTRL 0x128
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#define AFI_PEX2_CTRL_T186 0x19c
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#define AFI_PEX_CTRL_RST (1 << 0)
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#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
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#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
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@ -173,6 +190,7 @@ enum tegra_pci_id {
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TEGRA30_PCIE,
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TEGRA124_PCIE,
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TEGRA210_PCIE,
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TEGRA186_PCIE,
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};
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struct tegra_pcie_port {
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@ -189,6 +207,7 @@ struct tegra_pcie_soc {
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unsigned int num_ports;
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unsigned long pads_pll_ctl;
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unsigned long tx_ref_sel;
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unsigned long afi_pex2_ctrl;
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u32 pads_refclk_cfg0;
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u32 pads_refclk_cfg1;
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bool has_pex_clkreq_en;
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@ -209,7 +228,17 @@ struct tegra_pcie {
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unsigned long xbar;
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const struct tegra_pcie_soc *soc;
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#ifdef CONFIG_TEGRA186
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struct clk clk_afi;
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struct clk clk_pex;
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struct reset_ctl reset_afi;
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struct reset_ctl reset_pex;
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struct reset_ctl reset_pcie_x;
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struct power_domain pwrdom;
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#else
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struct tegra_xusb_phy *phy;
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#endif
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};
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static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
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@ -229,10 +258,12 @@ static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
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writel(value, pcie->pads.start + offset);
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}
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#ifndef CONFIG_TEGRA186
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static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
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{
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return readl(pcie->pads.start + offset);
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}
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#endif
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static unsigned long rp_readl(struct tegra_pcie_port *port,
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unsigned long offset)
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@ -400,6 +431,24 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
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return 0;
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}
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break;
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case TEGRA186_PCIE:
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switch (lanes) {
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case 0x0010004:
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debug("x4 x1 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_401;
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return 0;
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case 0x0010102:
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debug("x2 x1 x1 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_211;
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return 0;
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case 0x0010101:
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debug("x1 x1 x1 configuration\n");
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*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_T186_111;
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return 0;
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}
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break;
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default:
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break;
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}
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@ -471,6 +520,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
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return err;
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}
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#ifndef CONFIG_TEGRA186
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pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
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if (pcie->phy) {
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err = tegra_xusb_phy_prepare(pcie->phy);
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@ -479,6 +529,7 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
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return err;
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}
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}
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#endif
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fdt_for_each_subnode(fdt, subnode, node) {
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unsigned int index = 0, num_lanes = 0;
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@ -523,6 +574,44 @@ static int tegra_pcie_parse_dt(const void *fdt, int node, enum tegra_pci_id id,
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return 0;
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}
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#ifdef CONFIG_TEGRA186
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static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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{
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int ret;
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ret = power_domain_on(&pcie->pwrdom);
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if (ret) {
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error("power_domain_on() failed: %d\n", ret);
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return ret;
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}
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ret = clk_enable(&pcie->clk_afi);
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if (ret) {
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error("clk_enable(afi) failed: %d\n", ret);
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return ret;
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}
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ret = clk_enable(&pcie->clk_pex);
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if (ret) {
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error("clk_enable(pex) failed: %d\n", ret);
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return ret;
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}
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ret = reset_deassert(&pcie->reset_afi);
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if (ret) {
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error("reset_deassert(afi) failed: %d\n", ret);
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return ret;
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}
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ret = reset_deassert(&pcie->reset_pex);
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if (ret) {
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error("reset_deassert(pex) failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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#else
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static int tegra_pcie_power_on(struct tegra_pcie *pcie)
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{
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const struct tegra_pcie_soc *soc = pcie->soc;
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@ -639,6 +728,7 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
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return 0;
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}
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#endif
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static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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{
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@ -647,7 +737,11 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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u32 value;
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int err;
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#ifdef CONFIG_TEGRA186
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{
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#else
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if (pcie->phy) {
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#endif
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value = afi_readl(pcie, AFI_PLLE_CONTROL);
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value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
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value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
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@ -675,6 +769,7 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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afi_writel(pcie, value, AFI_FUSE);
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#ifndef CONFIG_TEGRA186
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if (pcie->phy)
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err = tegra_xusb_phy_enable(pcie->phy);
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else
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@ -684,9 +779,18 @@ static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
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error("failed to power on PHY: %d\n", err);
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return err;
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}
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#endif
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/* take the PCIEXCLK logic out of reset */
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#ifdef CONFIG_TEGRA186
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err = reset_deassert(&pcie->reset_pcie_x);
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if (err) {
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error("reset_deassert(pcie_x) failed: %d\n", err);
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return err;
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}
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#else
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reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
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#endif
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/* finally enable PCIe */
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value = afi_readl(pcie, AFI_CONFIGURATION);
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@ -787,7 +891,7 @@ static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
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break;
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case 2:
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ret = AFI_PEX2_CTRL;
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ret = port->pcie->soc->afi_pex2_ctrl;
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break;
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}
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@ -945,6 +1049,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
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.num_ports = 3,
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.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
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.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
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.afi_pex2_ctrl = AFI_PEX2_CTRL,
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.pads_refclk_cfg0 = 0xfa5cfa5c,
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.pads_refclk_cfg1 = 0xfa5cfa5c,
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.has_pex_clkreq_en = true,
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@ -972,7 +1077,16 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
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.has_cml_clk = true,
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.has_gen2 = true,
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.force_pca_enable = true,
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}
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},
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[TEGRA186_PCIE] = {
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.num_ports = 3,
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.afi_pex2_ctrl = AFI_PEX2_CTRL_T186,
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.pads_refclk_cfg0 = 0x80b880b8,
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.pads_refclk_cfg1 = 0x000480b8,
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.has_pex_clkreq_en = true,
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.has_pex_bias_ctrl = true,
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.has_gen2 = true,
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},
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};
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static int pci_tegra_ofdata_to_platdata(struct udevice *dev)
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@ -996,6 +1110,44 @@ static int pci_tegra_probe(struct udevice *dev)
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struct tegra_pcie *pcie = dev_get_priv(dev);
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int err;
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#ifdef CONFIG_TEGRA186
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err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
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if (err) {
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debug("clk_get_by_name(afi) failed: %d\n", err);
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return err;
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}
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err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
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if (err) {
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debug("clk_get_by_name(pex) failed: %d\n", err);
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return err;
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}
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err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
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if (err) {
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debug("reset_get_by_name(afi) failed: %d\n", err);
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return err;
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}
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err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
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if (err) {
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debug("reset_get_by_name(pex) failed: %d\n", err);
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return err;
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}
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err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
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if (err) {
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debug("reset_get_by_name(pcie_x) failed: %d\n", err);
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return err;
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}
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err = power_domain_get(dev, &pcie->pwrdom);
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if (err) {
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debug("power_domain_get() failed: %d\n", err);
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return err;
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}
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#endif
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err = tegra_pcie_power_on(pcie);
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if (err < 0) {
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error("failed to power on");
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@ -1033,6 +1185,7 @@ static const struct udevice_id pci_tegra_ids[] = {
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{ .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
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{ .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
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{ .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
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{ .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },
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{ }
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};
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